1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2017 Marvell International Ltd.
3 * Copyright(c) 2017 Semihalf.
7 #include <rte_string_fns.h>
8 #include <rte_ethdev_driver.h>
9 #include <rte_kvargs.h>
11 #include <rte_malloc.h>
12 #include <rte_bus_vdev.h>
15 #include <linux/ethtool.h>
16 #include <linux/sockios.h>
18 #include <net/if_arp.h>
19 #include <sys/ioctl.h>
20 #include <sys/socket.h>
22 #include <sys/types.h>
24 #include <rte_mvep_common.h>
25 #include "mrvl_ethdev.h"
27 #include "mrvl_flow.h"
31 /* bitmask with reserved hifs */
32 #define MRVL_MUSDK_HIFS_RESERVED 0x0F
33 /* bitmask with reserved bpools */
34 #define MRVL_MUSDK_BPOOLS_RESERVED 0x07
35 /* bitmask with reserved kernel RSS tables */
36 #define MRVL_MUSDK_RSS_RESERVED 0x01
37 /* maximum number of available hifs */
38 #define MRVL_MUSDK_HIFS_MAX 9
41 #define MRVL_MUSDK_PREFETCH_SHIFT 2
43 /* TCAM has 25 entries reserved for uc/mc filter entries */
44 #define MRVL_MAC_ADDRS_MAX 25
45 #define MRVL_MATCH_LEN 16
46 #define MRVL_PKT_EFFEC_OFFS (MRVL_PKT_OFFS + MV_MH_SIZE)
47 /* Maximum allowable packet size */
48 #define MRVL_PKT_SIZE_MAX (10240 - MV_MH_SIZE)
50 #define MRVL_IFACE_NAME_ARG "iface"
51 #define MRVL_CFG_ARG "cfg"
53 #define MRVL_BURST_SIZE 64
55 #define MRVL_ARP_LENGTH 28
57 #define MRVL_COOKIE_ADDR_INVALID ~0ULL
58 #define MRVL_COOKIE_HIGH_ADDR_MASK 0xffffff0000000000
60 /** Port Rx offload capabilities */
61 #define MRVL_RX_OFFLOADS (DEV_RX_OFFLOAD_VLAN_FILTER | \
62 DEV_RX_OFFLOAD_JUMBO_FRAME | \
63 DEV_RX_OFFLOAD_CHECKSUM)
65 /** Port Tx offloads capabilities */
66 #define MRVL_TX_OFFLOADS (DEV_TX_OFFLOAD_IPV4_CKSUM | \
67 DEV_TX_OFFLOAD_UDP_CKSUM | \
68 DEV_TX_OFFLOAD_TCP_CKSUM | \
69 DEV_TX_OFFLOAD_MULTI_SEGS)
71 static const char * const valid_args[] = {
77 static int used_hifs = MRVL_MUSDK_HIFS_RESERVED;
78 static struct pp2_hif *hifs[RTE_MAX_LCORE];
79 static int used_bpools[PP2_NUM_PKT_PROC] = {
80 [0 ... PP2_NUM_PKT_PROC - 1] = MRVL_MUSDK_BPOOLS_RESERVED
83 static struct pp2_bpool *mrvl_port_to_bpool_lookup[RTE_MAX_ETHPORTS];
84 static int mrvl_port_bpool_size[PP2_NUM_PKT_PROC][PP2_BPOOL_NUM_POOLS][RTE_MAX_LCORE];
85 static uint64_t cookie_addr_high = MRVL_COOKIE_ADDR_INVALID;
90 const char *names[PP2_NUM_ETH_PPIO * PP2_NUM_PKT_PROC];
95 * To use buffer harvesting based on loopback port shadow queue structure
96 * was introduced for buffers information bookkeeping.
98 * Before sending the packet, related buffer information (pp2_buff_inf) is
99 * stored in shadow queue. After packet is transmitted no longer used
100 * packet buffer is released back to it's original hardware pool,
101 * on condition it originated from interface.
102 * In case it was generated by application itself i.e: mbuf->port field is
103 * 0xff then its released to software mempool.
105 struct mrvl_shadow_txq {
106 int head; /* write index - used when sending buffers */
107 int tail; /* read index - used when releasing buffers */
108 u16 size; /* queue occupied size */
109 u16 num_to_release; /* number of descriptors sent, that can be
112 struct buff_release_entry ent[MRVL_PP2_TX_SHADOWQ_SIZE]; /* q entries */
116 struct mrvl_priv *priv;
117 struct rte_mempool *mp;
126 struct mrvl_priv *priv;
130 struct mrvl_shadow_txq shadow_txqs[RTE_MAX_LCORE];
131 int tx_deferred_start;
134 static int mrvl_lcore_first;
135 static int mrvl_lcore_last;
136 static int mrvl_dev_num;
138 static int mrvl_fill_bpool(struct mrvl_rxq *rxq, int num);
139 static inline void mrvl_free_sent_buffers(struct pp2_ppio *ppio,
140 struct pp2_hif *hif, unsigned int core_id,
141 struct mrvl_shadow_txq *sq, int qid, int force);
143 static uint16_t mrvl_tx_pkt_burst(void *txq, struct rte_mbuf **tx_pkts,
145 static uint16_t mrvl_tx_sg_pkt_burst(void *txq, struct rte_mbuf **tx_pkts,
149 #define MRVL_XSTATS_TBL_ENTRY(name) { \
150 #name, offsetof(struct pp2_ppio_statistics, name), \
151 sizeof(((struct pp2_ppio_statistics *)0)->name) \
154 /* Table with xstats data */
159 } mrvl_xstats_tbl[] = {
160 MRVL_XSTATS_TBL_ENTRY(rx_bytes),
161 MRVL_XSTATS_TBL_ENTRY(rx_packets),
162 MRVL_XSTATS_TBL_ENTRY(rx_unicast_packets),
163 MRVL_XSTATS_TBL_ENTRY(rx_errors),
164 MRVL_XSTATS_TBL_ENTRY(rx_fullq_dropped),
165 MRVL_XSTATS_TBL_ENTRY(rx_bm_dropped),
166 MRVL_XSTATS_TBL_ENTRY(rx_early_dropped),
167 MRVL_XSTATS_TBL_ENTRY(rx_fifo_dropped),
168 MRVL_XSTATS_TBL_ENTRY(rx_cls_dropped),
169 MRVL_XSTATS_TBL_ENTRY(tx_bytes),
170 MRVL_XSTATS_TBL_ENTRY(tx_packets),
171 MRVL_XSTATS_TBL_ENTRY(tx_unicast_packets),
172 MRVL_XSTATS_TBL_ENTRY(tx_errors)
176 mrvl_fill_shadowq(struct mrvl_shadow_txq *sq, struct rte_mbuf *buf)
178 sq->ent[sq->head].buff.cookie = (uint64_t)buf;
179 sq->ent[sq->head].buff.addr = buf ?
180 rte_mbuf_data_iova_default(buf) : 0;
182 sq->ent[sq->head].bpool =
183 (unlikely(!buf || buf->port >= RTE_MAX_ETHPORTS ||
184 buf->refcnt > 1)) ? NULL :
185 mrvl_port_to_bpool_lookup[buf->port];
187 sq->head = (sq->head + 1) & MRVL_PP2_TX_SHADOWQ_MASK;
192 mrvl_fill_desc(struct pp2_ppio_desc *desc, struct rte_mbuf *buf)
194 pp2_ppio_outq_desc_reset(desc);
195 pp2_ppio_outq_desc_set_phys_addr(desc, rte_pktmbuf_iova(buf));
196 pp2_ppio_outq_desc_set_pkt_offset(desc, 0);
197 pp2_ppio_outq_desc_set_pkt_len(desc, rte_pktmbuf_data_len(buf));
201 mrvl_get_bpool_size(int pp2_id, int pool_id)
206 for (i = mrvl_lcore_first; i <= mrvl_lcore_last; i++)
207 size += mrvl_port_bpool_size[pp2_id][pool_id][i];
213 mrvl_reserve_bit(int *bitmap, int max)
215 int n = sizeof(*bitmap) * 8 - __builtin_clz(*bitmap);
226 mrvl_init_hif(int core_id)
228 struct pp2_hif_params params;
229 char match[MRVL_MATCH_LEN];
232 ret = mrvl_reserve_bit(&used_hifs, MRVL_MUSDK_HIFS_MAX);
234 MRVL_LOG(ERR, "Failed to allocate hif %d", core_id);
238 snprintf(match, sizeof(match), "hif-%d", ret);
239 memset(¶ms, 0, sizeof(params));
240 params.match = match;
241 params.out_size = MRVL_PP2_AGGR_TXQD_MAX;
242 ret = pp2_hif_init(¶ms, &hifs[core_id]);
244 MRVL_LOG(ERR, "Failed to initialize hif %d", core_id);
251 static inline struct pp2_hif*
252 mrvl_get_hif(struct mrvl_priv *priv, int core_id)
256 if (likely(hifs[core_id] != NULL))
257 return hifs[core_id];
259 rte_spinlock_lock(&priv->lock);
261 ret = mrvl_init_hif(core_id);
263 MRVL_LOG(ERR, "Failed to allocate hif %d", core_id);
267 if (core_id < mrvl_lcore_first)
268 mrvl_lcore_first = core_id;
270 if (core_id > mrvl_lcore_last)
271 mrvl_lcore_last = core_id;
273 rte_spinlock_unlock(&priv->lock);
275 return hifs[core_id];
279 * Set tx burst function according to offload flag
282 * Pointer to Ethernet device structure.
285 mrvl_set_tx_function(struct rte_eth_dev *dev)
287 struct mrvl_priv *priv = dev->data->dev_private;
289 /* Use a simple Tx queue (no offloads, no multi segs) if possible */
290 if (priv->multiseg) {
291 RTE_LOG(INFO, PMD, "Using multi-segment tx callback\n");
292 dev->tx_pkt_burst = mrvl_tx_sg_pkt_burst;
294 RTE_LOG(INFO, PMD, "Using single-segment tx callback\n");
295 dev->tx_pkt_burst = mrvl_tx_pkt_burst;
300 * Configure rss based on dpdk rss configuration.
303 * Pointer to private structure.
305 * Pointer to RSS configuration.
308 * 0 on success, negative error value otherwise.
311 mrvl_configure_rss(struct mrvl_priv *priv, struct rte_eth_rss_conf *rss_conf)
313 if (rss_conf->rss_key)
314 MRVL_LOG(WARNING, "Changing hash key is not supported");
316 if (rss_conf->rss_hf == 0) {
317 priv->ppio_params.inqs_params.hash_type = PP2_PPIO_HASH_T_NONE;
318 } else if (rss_conf->rss_hf & ETH_RSS_IPV4) {
319 priv->ppio_params.inqs_params.hash_type =
320 PP2_PPIO_HASH_T_2_TUPLE;
321 } else if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) {
322 priv->ppio_params.inqs_params.hash_type =
323 PP2_PPIO_HASH_T_5_TUPLE;
324 priv->rss_hf_tcp = 1;
325 } else if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) {
326 priv->ppio_params.inqs_params.hash_type =
327 PP2_PPIO_HASH_T_5_TUPLE;
328 priv->rss_hf_tcp = 0;
337 * Ethernet device configuration.
339 * Prepare the driver for a given number of TX and RX queues and
343 * Pointer to Ethernet device structure.
346 * 0 on success, negative error value otherwise.
349 mrvl_dev_configure(struct rte_eth_dev *dev)
351 struct mrvl_priv *priv = dev->data->dev_private;
355 MRVL_LOG(INFO, "Device reconfiguration is not supported");
359 if (dev->data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_NONE &&
360 dev->data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_RSS) {
361 MRVL_LOG(INFO, "Unsupported rx multi queue mode %d",
362 dev->data->dev_conf.rxmode.mq_mode);
366 if (dev->data->dev_conf.rxmode.split_hdr_size) {
367 MRVL_LOG(INFO, "Split headers not supported");
371 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
372 dev->data->mtu = dev->data->dev_conf.rxmode.max_rx_pkt_len -
373 MRVL_PP2_ETH_HDRS_LEN;
375 if (dev->data->dev_conf.txmode.offloads & DEV_TX_OFFLOAD_MULTI_SEGS)
378 ret = mrvl_configure_rxqs(priv, dev->data->port_id,
379 dev->data->nb_rx_queues);
383 ret = mrvl_configure_txqs(priv, dev->data->port_id,
384 dev->data->nb_tx_queues);
388 priv->ppio_params.outqs_params.num_outqs = dev->data->nb_tx_queues;
389 priv->ppio_params.maintain_stats = 1;
390 priv->nb_rx_queues = dev->data->nb_rx_queues;
392 ret = mrvl_tm_init(dev);
396 if (dev->data->nb_rx_queues == 1 &&
397 dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS) {
398 MRVL_LOG(WARNING, "Disabling hash for 1 rx queue");
399 priv->ppio_params.inqs_params.hash_type = PP2_PPIO_HASH_T_NONE;
404 return mrvl_configure_rss(priv,
405 &dev->data->dev_conf.rx_adv_conf.rss_conf);
409 * DPDK callback to change the MTU.
411 * Setting the MTU affects hardware MRU (packets larger than the MRU
415 * Pointer to Ethernet device structure.
420 * 0 on success, negative error value otherwise.
423 mrvl_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
425 struct mrvl_priv *priv = dev->data->dev_private;
427 uint16_t mbuf_data_size = 0; /* SW buffer size */
430 mru = MRVL_PP2_MTU_TO_MRU(mtu);
432 * min_rx_buf_size is equal to mbuf data size
433 * if pmd didn't set it differently
435 mbuf_data_size = dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM;
437 * - setting mru greater than the mbuf size resulting in
438 * hw and sw buffer size mismatch
439 * - setting mtu that requires the support of scattered packets
440 * when this feature has not been enabled/supported so far
441 * (TODO check scattered_rx flag here once scattered RX is supported).
443 if (mru + MRVL_PKT_OFFS > mbuf_data_size) {
444 mru = mbuf_data_size - MRVL_PKT_OFFS;
445 mtu = MRVL_PP2_MRU_TO_MTU(mru);
446 MRVL_LOG(WARNING, "MTU too big, max MTU possible limitted "
447 "by current mbuf size: %u. Set MTU to %u, MRU to %u",
448 mbuf_data_size, mtu, mru);
451 if (mtu < RTE_ETHER_MIN_MTU || mru > MRVL_PKT_SIZE_MAX) {
452 MRVL_LOG(ERR, "Invalid MTU [%u] or MRU [%u]", mtu, mru);
456 dev->data->mtu = mtu;
457 dev->data->dev_conf.rxmode.max_rx_pkt_len = mru - MV_MH_SIZE;
462 ret = pp2_ppio_set_mru(priv->ppio, mru);
464 MRVL_LOG(ERR, "Failed to change MRU");
468 ret = pp2_ppio_set_mtu(priv->ppio, mtu);
470 MRVL_LOG(ERR, "Failed to change MTU");
478 * DPDK callback to bring the link up.
481 * Pointer to Ethernet device structure.
484 * 0 on success, negative error value otherwise.
487 mrvl_dev_set_link_up(struct rte_eth_dev *dev)
489 struct mrvl_priv *priv = dev->data->dev_private;
495 ret = pp2_ppio_enable(priv->ppio);
500 * mtu/mru can be updated if pp2_ppio_enable() was called at least once
501 * as pp2_ppio_enable() changes port->t_mode from default 0 to
502 * PP2_TRAFFIC_INGRESS_EGRESS.
504 * Set mtu to default DPDK value here.
506 ret = mrvl_mtu_set(dev, dev->data->mtu);
508 pp2_ppio_disable(priv->ppio);
514 * DPDK callback to bring the link down.
517 * Pointer to Ethernet device structure.
520 * 0 on success, negative error value otherwise.
523 mrvl_dev_set_link_down(struct rte_eth_dev *dev)
525 struct mrvl_priv *priv = dev->data->dev_private;
530 return pp2_ppio_disable(priv->ppio);
534 * DPDK callback to start tx queue.
537 * Pointer to Ethernet device structure.
539 * Transmit queue index.
542 * 0 on success, negative error value otherwise.
545 mrvl_tx_queue_start(struct rte_eth_dev *dev, uint16_t queue_id)
547 struct mrvl_priv *priv = dev->data->dev_private;
553 /* passing 1 enables given tx queue */
554 ret = pp2_ppio_set_outq_state(priv->ppio, queue_id, 1);
556 MRVL_LOG(ERR, "Failed to start txq %d", queue_id);
560 dev->data->tx_queue_state[queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
566 * DPDK callback to stop tx queue.
569 * Pointer to Ethernet device structure.
571 * Transmit queue index.
574 * 0 on success, negative error value otherwise.
577 mrvl_tx_queue_stop(struct rte_eth_dev *dev, uint16_t queue_id)
579 struct mrvl_priv *priv = dev->data->dev_private;
585 /* passing 0 disables given tx queue */
586 ret = pp2_ppio_set_outq_state(priv->ppio, queue_id, 0);
588 MRVL_LOG(ERR, "Failed to stop txq %d", queue_id);
592 dev->data->tx_queue_state[queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
598 * DPDK callback to start the device.
601 * Pointer to Ethernet device structure.
604 * 0 on success, negative errno value on failure.
607 mrvl_dev_start(struct rte_eth_dev *dev)
609 struct mrvl_priv *priv = dev->data->dev_private;
610 char match[MRVL_MATCH_LEN];
611 int ret = 0, i, def_init_size;
614 return mrvl_dev_set_link_up(dev);
616 snprintf(match, sizeof(match), "ppio-%d:%d",
617 priv->pp_id, priv->ppio_id);
618 priv->ppio_params.match = match;
621 * Calculate the minimum bpool size for refill feature as follows:
622 * 2 default burst sizes multiply by number of rx queues.
623 * If the bpool size will be below this value, new buffers will
624 * be added to the pool.
626 priv->bpool_min_size = priv->nb_rx_queues * MRVL_BURST_SIZE * 2;
628 /* In case initial bpool size configured in queues setup is
629 * smaller than minimum size add more buffers
631 def_init_size = priv->bpool_min_size + MRVL_BURST_SIZE * 2;
632 if (priv->bpool_init_size < def_init_size) {
633 int buffs_to_add = def_init_size - priv->bpool_init_size;
635 priv->bpool_init_size += buffs_to_add;
636 ret = mrvl_fill_bpool(dev->data->rx_queues[0], buffs_to_add);
638 MRVL_LOG(ERR, "Failed to add buffers to bpool");
642 * Calculate the maximum bpool size for refill feature as follows:
643 * maximum number of descriptors in rx queue multiply by number
644 * of rx queues plus minimum bpool size.
645 * In case the bpool size will exceed this value, superfluous buffers
648 priv->bpool_max_size = (priv->nb_rx_queues * MRVL_PP2_RXD_MAX) +
649 priv->bpool_min_size;
651 ret = pp2_ppio_init(&priv->ppio_params, &priv->ppio);
653 MRVL_LOG(ERR, "Failed to init ppio");
658 * In case there are some some stale uc/mc mac addresses flush them
659 * here. It cannot be done during mrvl_dev_close() as port information
660 * is already gone at that point (due to pp2_ppio_deinit() in
663 if (!priv->uc_mc_flushed) {
664 ret = pp2_ppio_flush_mac_addrs(priv->ppio, 1, 1);
667 "Failed to flush uc/mc filter list");
670 priv->uc_mc_flushed = 1;
673 if (!priv->vlan_flushed) {
674 ret = pp2_ppio_flush_vlan(priv->ppio);
676 MRVL_LOG(ERR, "Failed to flush vlan list");
679 * once pp2_ppio_flush_vlan() is supported jump to out
683 priv->vlan_flushed = 1;
685 ret = mrvl_mtu_set(dev, dev->data->mtu);
687 MRVL_LOG(ERR, "Failed to set MTU to %d", dev->data->mtu);
689 /* For default QoS config, don't start classifier. */
691 mrvl_qos_cfg->port[dev->data->port_id].use_global_defaults == 0) {
692 ret = mrvl_start_qos_mapping(priv);
694 MRVL_LOG(ERR, "Failed to setup QoS mapping");
699 ret = mrvl_dev_set_link_up(dev);
701 MRVL_LOG(ERR, "Failed to set link up");
705 /* start tx queues */
706 for (i = 0; i < dev->data->nb_tx_queues; i++) {
707 struct mrvl_txq *txq = dev->data->tx_queues[i];
709 dev->data->tx_queue_state[i] = RTE_ETH_QUEUE_STATE_STARTED;
711 if (!txq->tx_deferred_start)
715 * All txqs are started by default. Stop them
716 * so that tx_deferred_start works as expected.
718 ret = mrvl_tx_queue_stop(dev, i);
725 mrvl_set_tx_function(dev);
729 MRVL_LOG(ERR, "Failed to start device");
730 pp2_ppio_deinit(priv->ppio);
735 * Flush receive queues.
738 * Pointer to Ethernet device structure.
741 mrvl_flush_rx_queues(struct rte_eth_dev *dev)
745 MRVL_LOG(INFO, "Flushing rx queues");
746 for (i = 0; i < dev->data->nb_rx_queues; i++) {
750 struct mrvl_rxq *q = dev->data->rx_queues[i];
751 struct pp2_ppio_desc descs[MRVL_PP2_RXD_MAX];
753 num = MRVL_PP2_RXD_MAX;
754 ret = pp2_ppio_recv(q->priv->ppio,
755 q->priv->rxq_map[q->queue_id].tc,
756 q->priv->rxq_map[q->queue_id].inq,
757 descs, (uint16_t *)&num);
758 } while (ret == 0 && num);
763 * Flush transmit shadow queues.
766 * Pointer to Ethernet device structure.
769 mrvl_flush_tx_shadow_queues(struct rte_eth_dev *dev)
772 struct mrvl_txq *txq;
774 MRVL_LOG(INFO, "Flushing tx shadow queues");
775 for (i = 0; i < dev->data->nb_tx_queues; i++) {
776 txq = (struct mrvl_txq *)dev->data->tx_queues[i];
778 for (j = 0; j < RTE_MAX_LCORE; j++) {
779 struct mrvl_shadow_txq *sq;
784 sq = &txq->shadow_txqs[j];
785 mrvl_free_sent_buffers(txq->priv->ppio,
786 hifs[j], j, sq, txq->queue_id, 1);
787 while (sq->tail != sq->head) {
788 uint64_t addr = cookie_addr_high |
789 sq->ent[sq->tail].buff.cookie;
791 (struct rte_mbuf *)addr);
792 sq->tail = (sq->tail + 1) &
793 MRVL_PP2_TX_SHADOWQ_MASK;
795 memset(sq, 0, sizeof(*sq));
801 * Flush hardware bpool (buffer-pool).
804 * Pointer to Ethernet device structure.
807 mrvl_flush_bpool(struct rte_eth_dev *dev)
809 struct mrvl_priv *priv = dev->data->dev_private;
813 unsigned int core_id = rte_lcore_id();
815 if (core_id == LCORE_ID_ANY)
818 hif = mrvl_get_hif(priv, core_id);
820 ret = pp2_bpool_get_num_buffs(priv->bpool, &num);
822 MRVL_LOG(ERR, "Failed to get bpool buffers number");
827 struct pp2_buff_inf inf;
830 ret = pp2_bpool_get_buff(hif, priv->bpool, &inf);
834 addr = cookie_addr_high | inf.cookie;
835 rte_pktmbuf_free((struct rte_mbuf *)addr);
840 * DPDK callback to stop the device.
843 * Pointer to Ethernet device structure.
846 mrvl_dev_stop(struct rte_eth_dev *dev)
848 mrvl_dev_set_link_down(dev);
852 * DPDK callback to close the device.
855 * Pointer to Ethernet device structure.
858 mrvl_dev_close(struct rte_eth_dev *dev)
860 struct mrvl_priv *priv = dev->data->dev_private;
863 mrvl_flush_rx_queues(dev);
864 mrvl_flush_tx_shadow_queues(dev);
865 mrvl_flow_deinit(dev);
866 mrvl_mtr_deinit(dev);
868 for (i = 0; i < priv->ppio_params.inqs_params.num_tcs; ++i) {
869 struct pp2_ppio_tc_params *tc_params =
870 &priv->ppio_params.inqs_params.tcs_params[i];
872 if (tc_params->inqs_params) {
873 rte_free(tc_params->inqs_params);
874 tc_params->inqs_params = NULL;
879 pp2_cls_tbl_deinit(priv->cls_tbl);
880 priv->cls_tbl = NULL;
884 pp2_cls_qos_tbl_deinit(priv->qos_tbl);
885 priv->qos_tbl = NULL;
888 mrvl_flush_bpool(dev);
892 pp2_ppio_deinit(priv->ppio);
896 /* policer must be released after ppio deinitialization */
897 if (priv->default_policer) {
898 pp2_cls_plcr_deinit(priv->default_policer);
899 priv->default_policer = NULL;
904 * DPDK callback to retrieve physical link information.
907 * Pointer to Ethernet device structure.
908 * @param wait_to_complete
909 * Wait for request completion (ignored).
912 * 0 on success, negative error value otherwise.
915 mrvl_link_update(struct rte_eth_dev *dev, int wait_to_complete __rte_unused)
919 * once MUSDK provides necessary API use it here
921 struct mrvl_priv *priv = dev->data->dev_private;
922 struct ethtool_cmd edata;
924 int ret, fd, link_up;
929 edata.cmd = ETHTOOL_GSET;
931 strcpy(req.ifr_name, dev->data->name);
932 req.ifr_data = (void *)&edata;
934 fd = socket(AF_INET, SOCK_DGRAM, 0);
938 ret = ioctl(fd, SIOCETHTOOL, &req);
946 switch (ethtool_cmd_speed(&edata)) {
948 dev->data->dev_link.link_speed = ETH_SPEED_NUM_10M;
951 dev->data->dev_link.link_speed = ETH_SPEED_NUM_100M;
954 dev->data->dev_link.link_speed = ETH_SPEED_NUM_1G;
957 dev->data->dev_link.link_speed = ETH_SPEED_NUM_10G;
960 dev->data->dev_link.link_speed = ETH_SPEED_NUM_NONE;
963 dev->data->dev_link.link_duplex = edata.duplex ? ETH_LINK_FULL_DUPLEX :
964 ETH_LINK_HALF_DUPLEX;
965 dev->data->dev_link.link_autoneg = edata.autoneg ? ETH_LINK_AUTONEG :
967 pp2_ppio_get_link_state(priv->ppio, &link_up);
968 dev->data->dev_link.link_status = link_up ? ETH_LINK_UP : ETH_LINK_DOWN;
974 * DPDK callback to enable promiscuous mode.
977 * Pointer to Ethernet device structure.
980 mrvl_promiscuous_enable(struct rte_eth_dev *dev)
982 struct mrvl_priv *priv = dev->data->dev_private;
991 ret = pp2_ppio_set_promisc(priv->ppio, 1);
993 MRVL_LOG(ERR, "Failed to enable promiscuous mode");
997 * DPDK callback to enable allmulti mode.
1000 * Pointer to Ethernet device structure.
1003 mrvl_allmulticast_enable(struct rte_eth_dev *dev)
1005 struct mrvl_priv *priv = dev->data->dev_private;
1014 ret = pp2_ppio_set_mc_promisc(priv->ppio, 1);
1016 MRVL_LOG(ERR, "Failed enable all-multicast mode");
1020 * DPDK callback to disable promiscuous mode.
1023 * Pointer to Ethernet device structure.
1026 mrvl_promiscuous_disable(struct rte_eth_dev *dev)
1028 struct mrvl_priv *priv = dev->data->dev_private;
1034 ret = pp2_ppio_set_promisc(priv->ppio, 0);
1036 MRVL_LOG(ERR, "Failed to disable promiscuous mode");
1040 * DPDK callback to disable allmulticast mode.
1043 * Pointer to Ethernet device structure.
1046 mrvl_allmulticast_disable(struct rte_eth_dev *dev)
1048 struct mrvl_priv *priv = dev->data->dev_private;
1054 ret = pp2_ppio_set_mc_promisc(priv->ppio, 0);
1056 MRVL_LOG(ERR, "Failed to disable all-multicast mode");
1060 * DPDK callback to remove a MAC address.
1063 * Pointer to Ethernet device structure.
1065 * MAC address index.
1068 mrvl_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index)
1070 struct mrvl_priv *priv = dev->data->dev_private;
1071 char buf[RTE_ETHER_ADDR_FMT_SIZE];
1080 ret = pp2_ppio_remove_mac_addr(priv->ppio,
1081 dev->data->mac_addrs[index].addr_bytes);
1083 rte_ether_format_addr(buf, sizeof(buf),
1084 &dev->data->mac_addrs[index]);
1085 MRVL_LOG(ERR, "Failed to remove mac %s", buf);
1090 * DPDK callback to add a MAC address.
1093 * Pointer to Ethernet device structure.
1095 * MAC address to register.
1097 * MAC address index.
1099 * VMDq pool index to associate address with (unused).
1102 * 0 on success, negative error value otherwise.
1105 mrvl_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
1106 uint32_t index, uint32_t vmdq __rte_unused)
1108 struct mrvl_priv *priv = dev->data->dev_private;
1109 char buf[RTE_ETHER_ADDR_FMT_SIZE];
1116 /* For setting index 0, mrvl_mac_addr_set() should be used.*/
1123 * Maximum number of uc addresses can be tuned via kernel module mvpp2x
1124 * parameter uc_filter_max. Maximum number of mc addresses is then
1125 * MRVL_MAC_ADDRS_MAX - uc_filter_max. Currently it defaults to 4 and
1128 * If more than uc_filter_max uc addresses were added to filter list
1129 * then NIC will switch to promiscuous mode automatically.
1131 * If more than MRVL_MAC_ADDRS_MAX - uc_filter_max number mc addresses
1132 * were added to filter list then NIC will switch to all-multicast mode
1135 ret = pp2_ppio_add_mac_addr(priv->ppio, mac_addr->addr_bytes);
1137 rte_ether_format_addr(buf, sizeof(buf), mac_addr);
1138 MRVL_LOG(ERR, "Failed to add mac %s", buf);
1146 * DPDK callback to set the primary MAC address.
1149 * Pointer to Ethernet device structure.
1151 * MAC address to register.
1154 * 0 on success, negative error value otherwise.
1157 mrvl_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr)
1159 struct mrvl_priv *priv = dev->data->dev_private;
1168 ret = pp2_ppio_set_mac_addr(priv->ppio, mac_addr->addr_bytes);
1170 char buf[RTE_ETHER_ADDR_FMT_SIZE];
1171 rte_ether_format_addr(buf, sizeof(buf), mac_addr);
1172 MRVL_LOG(ERR, "Failed to set mac to %s", buf);
1179 * DPDK callback to get device statistics.
1182 * Pointer to Ethernet device structure.
1184 * Stats structure output buffer.
1187 * 0 on success, negative error value otherwise.
1190 mrvl_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1192 struct mrvl_priv *priv = dev->data->dev_private;
1193 struct pp2_ppio_statistics ppio_stats;
1194 uint64_t drop_mac = 0;
1195 unsigned int i, idx, ret;
1200 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1201 struct mrvl_rxq *rxq = dev->data->rx_queues[i];
1202 struct pp2_ppio_inq_statistics rx_stats;
1207 idx = rxq->queue_id;
1208 if (unlikely(idx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)) {
1210 "rx queue %d stats out of range (0 - %d)",
1211 idx, RTE_ETHDEV_QUEUE_STAT_CNTRS - 1);
1215 ret = pp2_ppio_inq_get_statistics(priv->ppio,
1216 priv->rxq_map[idx].tc,
1217 priv->rxq_map[idx].inq,
1219 if (unlikely(ret)) {
1221 "Failed to update rx queue %d stats", idx);
1225 stats->q_ibytes[idx] = rxq->bytes_recv;
1226 stats->q_ipackets[idx] = rx_stats.enq_desc - rxq->drop_mac;
1227 stats->q_errors[idx] = rx_stats.drop_early +
1228 rx_stats.drop_fullq +
1231 stats->ibytes += rxq->bytes_recv;
1232 drop_mac += rxq->drop_mac;
1235 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1236 struct mrvl_txq *txq = dev->data->tx_queues[i];
1237 struct pp2_ppio_outq_statistics tx_stats;
1242 idx = txq->queue_id;
1243 if (unlikely(idx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)) {
1245 "tx queue %d stats out of range (0 - %d)",
1246 idx, RTE_ETHDEV_QUEUE_STAT_CNTRS - 1);
1249 ret = pp2_ppio_outq_get_statistics(priv->ppio, idx,
1251 if (unlikely(ret)) {
1253 "Failed to update tx queue %d stats", idx);
1257 stats->q_opackets[idx] = tx_stats.deq_desc;
1258 stats->q_obytes[idx] = txq->bytes_sent;
1259 stats->obytes += txq->bytes_sent;
1262 ret = pp2_ppio_get_statistics(priv->ppio, &ppio_stats, 0);
1263 if (unlikely(ret)) {
1264 MRVL_LOG(ERR, "Failed to update port statistics");
1268 stats->ipackets += ppio_stats.rx_packets - drop_mac;
1269 stats->opackets += ppio_stats.tx_packets;
1270 stats->imissed += ppio_stats.rx_fullq_dropped +
1271 ppio_stats.rx_bm_dropped +
1272 ppio_stats.rx_early_dropped +
1273 ppio_stats.rx_fifo_dropped +
1274 ppio_stats.rx_cls_dropped;
1275 stats->ierrors = drop_mac;
1281 * DPDK callback to clear device statistics.
1284 * Pointer to Ethernet device structure.
1287 mrvl_stats_reset(struct rte_eth_dev *dev)
1289 struct mrvl_priv *priv = dev->data->dev_private;
1295 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1296 struct mrvl_rxq *rxq = dev->data->rx_queues[i];
1298 pp2_ppio_inq_get_statistics(priv->ppio, priv->rxq_map[i].tc,
1299 priv->rxq_map[i].inq, NULL, 1);
1300 rxq->bytes_recv = 0;
1304 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1305 struct mrvl_txq *txq = dev->data->tx_queues[i];
1307 pp2_ppio_outq_get_statistics(priv->ppio, i, NULL, 1);
1308 txq->bytes_sent = 0;
1311 pp2_ppio_get_statistics(priv->ppio, NULL, 1);
1315 * DPDK callback to get extended statistics.
1318 * Pointer to Ethernet device structure.
1320 * Pointer to xstats table.
1322 * Number of entries in xstats table.
1324 * Negative value on error, number of read xstats otherwise.
1327 mrvl_xstats_get(struct rte_eth_dev *dev,
1328 struct rte_eth_xstat *stats, unsigned int n)
1330 struct mrvl_priv *priv = dev->data->dev_private;
1331 struct pp2_ppio_statistics ppio_stats;
1337 pp2_ppio_get_statistics(priv->ppio, &ppio_stats, 0);
1338 for (i = 0; i < n && i < RTE_DIM(mrvl_xstats_tbl); i++) {
1341 if (mrvl_xstats_tbl[i].size == sizeof(uint32_t))
1342 val = *(uint32_t *)((uint8_t *)&ppio_stats +
1343 mrvl_xstats_tbl[i].offset);
1344 else if (mrvl_xstats_tbl[i].size == sizeof(uint64_t))
1345 val = *(uint64_t *)((uint8_t *)&ppio_stats +
1346 mrvl_xstats_tbl[i].offset);
1351 stats[i].value = val;
1358 * DPDK callback to reset extended statistics.
1361 * Pointer to Ethernet device structure.
1364 mrvl_xstats_reset(struct rte_eth_dev *dev)
1366 mrvl_stats_reset(dev);
1370 * DPDK callback to get extended statistics names.
1372 * @param dev (unused)
1373 * Pointer to Ethernet device structure.
1374 * @param xstats_names
1375 * Pointer to xstats names table.
1377 * Size of the xstats names table.
1379 * Number of read names.
1382 mrvl_xstats_get_names(struct rte_eth_dev *dev __rte_unused,
1383 struct rte_eth_xstat_name *xstats_names,
1389 return RTE_DIM(mrvl_xstats_tbl);
1391 for (i = 0; i < size && i < RTE_DIM(mrvl_xstats_tbl); i++)
1392 strlcpy(xstats_names[i].name, mrvl_xstats_tbl[i].name,
1393 RTE_ETH_XSTATS_NAME_SIZE);
1399 * DPDK callback to get information about the device.
1402 * Pointer to Ethernet device structure (unused).
1404 * Info structure output buffer.
1407 mrvl_dev_infos_get(struct rte_eth_dev *dev __rte_unused,
1408 struct rte_eth_dev_info *info)
1410 info->speed_capa = ETH_LINK_SPEED_10M |
1411 ETH_LINK_SPEED_100M |
1415 info->max_rx_queues = MRVL_PP2_RXQ_MAX;
1416 info->max_tx_queues = MRVL_PP2_TXQ_MAX;
1417 info->max_mac_addrs = MRVL_MAC_ADDRS_MAX;
1419 info->rx_desc_lim.nb_max = MRVL_PP2_RXD_MAX;
1420 info->rx_desc_lim.nb_min = MRVL_PP2_RXD_MIN;
1421 info->rx_desc_lim.nb_align = MRVL_PP2_RXD_ALIGN;
1423 info->tx_desc_lim.nb_max = MRVL_PP2_TXD_MAX;
1424 info->tx_desc_lim.nb_min = MRVL_PP2_TXD_MIN;
1425 info->tx_desc_lim.nb_align = MRVL_PP2_TXD_ALIGN;
1427 info->rx_offload_capa = MRVL_RX_OFFLOADS;
1428 info->rx_queue_offload_capa = MRVL_RX_OFFLOADS;
1430 info->tx_offload_capa = MRVL_TX_OFFLOADS;
1431 info->tx_queue_offload_capa = MRVL_TX_OFFLOADS;
1433 info->flow_type_rss_offloads = ETH_RSS_IPV4 |
1434 ETH_RSS_NONFRAG_IPV4_TCP |
1435 ETH_RSS_NONFRAG_IPV4_UDP;
1437 /* By default packets are dropped if no descriptors are available */
1438 info->default_rxconf.rx_drop_en = 1;
1440 info->max_rx_pktlen = MRVL_PKT_SIZE_MAX;
1444 * Return supported packet types.
1447 * Pointer to Ethernet device structure (unused).
1450 * Const pointer to the table with supported packet types.
1452 static const uint32_t *
1453 mrvl_dev_supported_ptypes_get(struct rte_eth_dev *dev __rte_unused)
1455 static const uint32_t ptypes[] = {
1457 RTE_PTYPE_L2_ETHER_VLAN,
1458 RTE_PTYPE_L2_ETHER_QINQ,
1460 RTE_PTYPE_L3_IPV4_EXT,
1461 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
1463 RTE_PTYPE_L3_IPV6_EXT,
1464 RTE_PTYPE_L2_ETHER_ARP,
1473 * DPDK callback to get information about specific receive queue.
1476 * Pointer to Ethernet device structure.
1477 * @param rx_queue_id
1478 * Receive queue index.
1480 * Receive queue information structure.
1482 static void mrvl_rxq_info_get(struct rte_eth_dev *dev, uint16_t rx_queue_id,
1483 struct rte_eth_rxq_info *qinfo)
1485 struct mrvl_rxq *q = dev->data->rx_queues[rx_queue_id];
1486 struct mrvl_priv *priv = dev->data->dev_private;
1487 int inq = priv->rxq_map[rx_queue_id].inq;
1488 int tc = priv->rxq_map[rx_queue_id].tc;
1489 struct pp2_ppio_tc_params *tc_params =
1490 &priv->ppio_params.inqs_params.tcs_params[tc];
1493 qinfo->nb_desc = tc_params->inqs_params[inq].size;
1497 * DPDK callback to get information about specific transmit queue.
1500 * Pointer to Ethernet device structure.
1501 * @param tx_queue_id
1502 * Transmit queue index.
1504 * Transmit queue information structure.
1506 static void mrvl_txq_info_get(struct rte_eth_dev *dev, uint16_t tx_queue_id,
1507 struct rte_eth_txq_info *qinfo)
1509 struct mrvl_priv *priv = dev->data->dev_private;
1510 struct mrvl_txq *txq = dev->data->tx_queues[tx_queue_id];
1513 priv->ppio_params.outqs_params.outqs_params[tx_queue_id].size;
1514 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
1518 * DPDK callback to Configure a VLAN filter.
1521 * Pointer to Ethernet device structure.
1523 * VLAN ID to filter.
1528 * 0 on success, negative error value otherwise.
1531 mrvl_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1533 struct mrvl_priv *priv = dev->data->dev_private;
1541 return on ? pp2_ppio_add_vlan(priv->ppio, vlan_id) :
1542 pp2_ppio_remove_vlan(priv->ppio, vlan_id);
1546 * Release buffers to hardware bpool (buffer-pool)
1549 * Receive queue pointer.
1551 * Number of buffers to release to bpool.
1554 * 0 on success, negative error value otherwise.
1557 mrvl_fill_bpool(struct mrvl_rxq *rxq, int num)
1559 struct buff_release_entry entries[MRVL_PP2_RXD_MAX];
1560 struct rte_mbuf *mbufs[MRVL_PP2_RXD_MAX];
1562 unsigned int core_id;
1563 struct pp2_hif *hif;
1564 struct pp2_bpool *bpool;
1566 core_id = rte_lcore_id();
1567 if (core_id == LCORE_ID_ANY)
1570 hif = mrvl_get_hif(rxq->priv, core_id);
1574 bpool = rxq->priv->bpool;
1576 ret = rte_pktmbuf_alloc_bulk(rxq->mp, mbufs, num);
1580 if (cookie_addr_high == MRVL_COOKIE_ADDR_INVALID)
1582 (uint64_t)mbufs[0] & MRVL_COOKIE_HIGH_ADDR_MASK;
1584 for (i = 0; i < num; i++) {
1585 if (((uint64_t)mbufs[i] & MRVL_COOKIE_HIGH_ADDR_MASK)
1586 != cookie_addr_high) {
1588 "mbuf virtual addr high 0x%lx out of range",
1589 (uint64_t)mbufs[i] >> 32);
1593 entries[i].buff.addr =
1594 rte_mbuf_data_iova_default(mbufs[i]);
1595 entries[i].buff.cookie = (uint64_t)mbufs[i];
1596 entries[i].bpool = bpool;
1599 pp2_bpool_put_buffs(hif, entries, (uint16_t *)&i);
1600 mrvl_port_bpool_size[bpool->pp2_id][bpool->id][core_id] += i;
1607 for (; i < num; i++)
1608 rte_pktmbuf_free(mbufs[i]);
1614 * DPDK callback to configure the receive queue.
1617 * Pointer to Ethernet device structure.
1621 * Number of descriptors to configure in queue.
1623 * NUMA socket on which memory must be allocated.
1625 * Thresholds parameters.
1627 * Memory pool for buffer allocations.
1630 * 0 on success, negative error value otherwise.
1633 mrvl_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
1634 unsigned int socket,
1635 const struct rte_eth_rxconf *conf,
1636 struct rte_mempool *mp)
1638 struct mrvl_priv *priv = dev->data->dev_private;
1639 struct mrvl_rxq *rxq;
1640 uint32_t frame_size, buf_size = rte_pktmbuf_data_room_size(mp);
1641 uint32_t max_rx_pkt_len = dev->data->dev_conf.rxmode.max_rx_pkt_len;
1645 offloads = conf->offloads | dev->data->dev_conf.rxmode.offloads;
1647 if (priv->rxq_map[idx].tc == MRVL_UNKNOWN_TC) {
1649 * Unknown TC mapping, mapping will not have a correct queue.
1651 MRVL_LOG(ERR, "Unknown TC mapping for queue %hu eth%hhu",
1652 idx, priv->ppio_id);
1656 frame_size = buf_size - RTE_PKTMBUF_HEADROOM - MRVL_PKT_EFFEC_OFFS;
1657 if (frame_size < max_rx_pkt_len) {
1659 "Mbuf size must be increased to %u bytes to hold up "
1660 "to %u bytes of data.",
1661 buf_size + max_rx_pkt_len - frame_size,
1663 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
1664 MRVL_LOG(INFO, "Setting max rx pkt len to %u",
1665 dev->data->dev_conf.rxmode.max_rx_pkt_len);
1668 if (dev->data->rx_queues[idx]) {
1669 rte_free(dev->data->rx_queues[idx]);
1670 dev->data->rx_queues[idx] = NULL;
1673 rxq = rte_zmalloc_socket("rxq", sizeof(*rxq), 0, socket);
1679 rxq->cksum_enabled = offloads & DEV_RX_OFFLOAD_IPV4_CKSUM;
1680 rxq->queue_id = idx;
1681 rxq->port_id = dev->data->port_id;
1682 mrvl_port_to_bpool_lookup[rxq->port_id] = priv->bpool;
1684 tc = priv->rxq_map[rxq->queue_id].tc,
1685 inq = priv->rxq_map[rxq->queue_id].inq;
1686 priv->ppio_params.inqs_params.tcs_params[tc].inqs_params[inq].size =
1689 ret = mrvl_fill_bpool(rxq, desc);
1695 priv->bpool_init_size += desc;
1697 dev->data->rx_queues[idx] = rxq;
1703 * DPDK callback to release the receive queue.
1706 * Generic receive queue pointer.
1709 mrvl_rx_queue_release(void *rxq)
1711 struct mrvl_rxq *q = rxq;
1712 struct pp2_ppio_tc_params *tc_params;
1713 int i, num, tc, inq;
1714 struct pp2_hif *hif;
1715 unsigned int core_id = rte_lcore_id();
1717 if (core_id == LCORE_ID_ANY)
1723 hif = mrvl_get_hif(q->priv, core_id);
1728 tc = q->priv->rxq_map[q->queue_id].tc;
1729 inq = q->priv->rxq_map[q->queue_id].inq;
1730 tc_params = &q->priv->ppio_params.inqs_params.tcs_params[tc];
1731 num = tc_params->inqs_params[inq].size;
1732 for (i = 0; i < num; i++) {
1733 struct pp2_buff_inf inf;
1736 pp2_bpool_get_buff(hif, q->priv->bpool, &inf);
1737 addr = cookie_addr_high | inf.cookie;
1738 rte_pktmbuf_free((struct rte_mbuf *)addr);
1745 * DPDK callback to configure the transmit queue.
1748 * Pointer to Ethernet device structure.
1750 * Transmit queue index.
1752 * Number of descriptors to configure in the queue.
1754 * NUMA socket on which memory must be allocated.
1756 * Tx queue configuration parameters.
1759 * 0 on success, negative error value otherwise.
1762 mrvl_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
1763 unsigned int socket,
1764 const struct rte_eth_txconf *conf)
1766 struct mrvl_priv *priv = dev->data->dev_private;
1767 struct mrvl_txq *txq;
1769 if (dev->data->tx_queues[idx]) {
1770 rte_free(dev->data->tx_queues[idx]);
1771 dev->data->tx_queues[idx] = NULL;
1774 txq = rte_zmalloc_socket("txq", sizeof(*txq), 0, socket);
1779 txq->queue_id = idx;
1780 txq->port_id = dev->data->port_id;
1781 txq->tx_deferred_start = conf->tx_deferred_start;
1782 dev->data->tx_queues[idx] = txq;
1784 priv->ppio_params.outqs_params.outqs_params[idx].size = desc;
1790 * DPDK callback to release the transmit queue.
1793 * Generic transmit queue pointer.
1796 mrvl_tx_queue_release(void *txq)
1798 struct mrvl_txq *q = txq;
1807 * DPDK callback to get flow control configuration.
1810 * Pointer to Ethernet device structure.
1812 * Pointer to the flow control configuration.
1815 * 0 on success, negative error value otherwise.
1818 mrvl_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1820 struct mrvl_priv *priv = dev->data->dev_private;
1826 ret = pp2_ppio_get_rx_pause(priv->ppio, &en);
1828 MRVL_LOG(ERR, "Failed to read rx pause state");
1832 fc_conf->mode = en ? RTE_FC_RX_PAUSE : RTE_FC_NONE;
1838 * DPDK callback to set flow control configuration.
1841 * Pointer to Ethernet device structure.
1843 * Pointer to the flow control configuration.
1846 * 0 on success, negative error value otherwise.
1849 mrvl_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1851 struct mrvl_priv *priv = dev->data->dev_private;
1856 if (fc_conf->high_water ||
1857 fc_conf->low_water ||
1858 fc_conf->pause_time ||
1859 fc_conf->mac_ctrl_frame_fwd ||
1861 MRVL_LOG(ERR, "Flowctrl parameter is not supported");
1866 if (fc_conf->mode == RTE_FC_NONE ||
1867 fc_conf->mode == RTE_FC_RX_PAUSE) {
1870 en = fc_conf->mode == RTE_FC_NONE ? 0 : 1;
1871 ret = pp2_ppio_set_rx_pause(priv->ppio, en);
1874 "Failed to change flowctrl on RX side");
1883 * Update RSS hash configuration
1886 * Pointer to Ethernet device structure.
1888 * Pointer to RSS configuration.
1891 * 0 on success, negative error value otherwise.
1894 mrvl_rss_hash_update(struct rte_eth_dev *dev,
1895 struct rte_eth_rss_conf *rss_conf)
1897 struct mrvl_priv *priv = dev->data->dev_private;
1902 return mrvl_configure_rss(priv, rss_conf);
1906 * DPDK callback to get RSS hash configuration.
1909 * Pointer to Ethernet device structure.
1911 * Pointer to RSS configuration.
1917 mrvl_rss_hash_conf_get(struct rte_eth_dev *dev,
1918 struct rte_eth_rss_conf *rss_conf)
1920 struct mrvl_priv *priv = dev->data->dev_private;
1921 enum pp2_ppio_hash_type hash_type =
1922 priv->ppio_params.inqs_params.hash_type;
1924 rss_conf->rss_key = NULL;
1926 if (hash_type == PP2_PPIO_HASH_T_NONE)
1927 rss_conf->rss_hf = 0;
1928 else if (hash_type == PP2_PPIO_HASH_T_2_TUPLE)
1929 rss_conf->rss_hf = ETH_RSS_IPV4;
1930 else if (hash_type == PP2_PPIO_HASH_T_5_TUPLE && priv->rss_hf_tcp)
1931 rss_conf->rss_hf = ETH_RSS_NONFRAG_IPV4_TCP;
1932 else if (hash_type == PP2_PPIO_HASH_T_5_TUPLE && !priv->rss_hf_tcp)
1933 rss_conf->rss_hf = ETH_RSS_NONFRAG_IPV4_UDP;
1939 * DPDK callback to get rte_flow callbacks.
1942 * Pointer to the device structure.
1946 * Flow filter operation.
1948 * Pointer to pass the flow ops.
1951 * 0 on success, negative error value otherwise.
1954 mrvl_eth_filter_ctrl(struct rte_eth_dev *dev __rte_unused,
1955 enum rte_filter_type filter_type,
1956 enum rte_filter_op filter_op, void *arg)
1958 switch (filter_type) {
1959 case RTE_ETH_FILTER_GENERIC:
1960 if (filter_op != RTE_ETH_FILTER_GET)
1962 *(const void **)arg = &mrvl_flow_ops;
1965 MRVL_LOG(WARNING, "Filter type (%d) not supported",
1972 * DPDK callback to get rte_mtr callbacks.
1975 * Pointer to the device structure.
1977 * Pointer to pass the mtr ops.
1983 mrvl_mtr_ops_get(struct rte_eth_dev *dev __rte_unused, void *ops)
1985 *(const void **)ops = &mrvl_mtr_ops;
1991 * DPDK callback to get rte_tm callbacks.
1994 * Pointer to the device structure.
1996 * Pointer to pass the tm ops.
2002 mrvl_tm_ops_get(struct rte_eth_dev *dev __rte_unused, void *ops)
2004 *(const void **)ops = &mrvl_tm_ops;
2009 static const struct eth_dev_ops mrvl_ops = {
2010 .dev_configure = mrvl_dev_configure,
2011 .dev_start = mrvl_dev_start,
2012 .dev_stop = mrvl_dev_stop,
2013 .dev_set_link_up = mrvl_dev_set_link_up,
2014 .dev_set_link_down = mrvl_dev_set_link_down,
2015 .dev_close = mrvl_dev_close,
2016 .link_update = mrvl_link_update,
2017 .promiscuous_enable = mrvl_promiscuous_enable,
2018 .allmulticast_enable = mrvl_allmulticast_enable,
2019 .promiscuous_disable = mrvl_promiscuous_disable,
2020 .allmulticast_disable = mrvl_allmulticast_disable,
2021 .mac_addr_remove = mrvl_mac_addr_remove,
2022 .mac_addr_add = mrvl_mac_addr_add,
2023 .mac_addr_set = mrvl_mac_addr_set,
2024 .mtu_set = mrvl_mtu_set,
2025 .stats_get = mrvl_stats_get,
2026 .stats_reset = mrvl_stats_reset,
2027 .xstats_get = mrvl_xstats_get,
2028 .xstats_reset = mrvl_xstats_reset,
2029 .xstats_get_names = mrvl_xstats_get_names,
2030 .dev_infos_get = mrvl_dev_infos_get,
2031 .dev_supported_ptypes_get = mrvl_dev_supported_ptypes_get,
2032 .rxq_info_get = mrvl_rxq_info_get,
2033 .txq_info_get = mrvl_txq_info_get,
2034 .vlan_filter_set = mrvl_vlan_filter_set,
2035 .tx_queue_start = mrvl_tx_queue_start,
2036 .tx_queue_stop = mrvl_tx_queue_stop,
2037 .rx_queue_setup = mrvl_rx_queue_setup,
2038 .rx_queue_release = mrvl_rx_queue_release,
2039 .tx_queue_setup = mrvl_tx_queue_setup,
2040 .tx_queue_release = mrvl_tx_queue_release,
2041 .flow_ctrl_get = mrvl_flow_ctrl_get,
2042 .flow_ctrl_set = mrvl_flow_ctrl_set,
2043 .rss_hash_update = mrvl_rss_hash_update,
2044 .rss_hash_conf_get = mrvl_rss_hash_conf_get,
2045 .filter_ctrl = mrvl_eth_filter_ctrl,
2046 .mtr_ops_get = mrvl_mtr_ops_get,
2047 .tm_ops_get = mrvl_tm_ops_get,
2051 * Return packet type information and l3/l4 offsets.
2054 * Pointer to the received packet descriptor.
2061 * Packet type information.
2063 static inline uint64_t
2064 mrvl_desc_to_packet_type_and_offset(struct pp2_ppio_desc *desc,
2065 uint8_t *l3_offset, uint8_t *l4_offset)
2067 enum pp2_inq_l3_type l3_type;
2068 enum pp2_inq_l4_type l4_type;
2069 enum pp2_inq_vlan_tag vlan_tag;
2070 uint64_t packet_type;
2072 pp2_ppio_inq_desc_get_l3_info(desc, &l3_type, l3_offset);
2073 pp2_ppio_inq_desc_get_l4_info(desc, &l4_type, l4_offset);
2074 pp2_ppio_inq_desc_get_vlan_tag(desc, &vlan_tag);
2076 packet_type = RTE_PTYPE_L2_ETHER;
2079 case PP2_INQ_VLAN_TAG_SINGLE:
2080 packet_type |= RTE_PTYPE_L2_ETHER_VLAN;
2082 case PP2_INQ_VLAN_TAG_DOUBLE:
2083 case PP2_INQ_VLAN_TAG_TRIPLE:
2084 packet_type |= RTE_PTYPE_L2_ETHER_QINQ;
2091 case PP2_INQ_L3_TYPE_IPV4_NO_OPTS:
2092 packet_type |= RTE_PTYPE_L3_IPV4;
2094 case PP2_INQ_L3_TYPE_IPV4_OK:
2095 packet_type |= RTE_PTYPE_L3_IPV4_EXT;
2097 case PP2_INQ_L3_TYPE_IPV4_TTL_ZERO:
2098 packet_type |= RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
2100 case PP2_INQ_L3_TYPE_IPV6_NO_EXT:
2101 packet_type |= RTE_PTYPE_L3_IPV6;
2103 case PP2_INQ_L3_TYPE_IPV6_EXT:
2104 packet_type |= RTE_PTYPE_L3_IPV6_EXT;
2106 case PP2_INQ_L3_TYPE_ARP:
2107 packet_type |= RTE_PTYPE_L2_ETHER_ARP;
2109 * In case of ARP l4_offset is set to wrong value.
2110 * Set it to proper one so that later on mbuf->l3_len can be
2111 * calculated subtracting l4_offset and l3_offset.
2113 *l4_offset = *l3_offset + MRVL_ARP_LENGTH;
2116 MRVL_LOG(DEBUG, "Failed to recognise l3 packet type");
2121 case PP2_INQ_L4_TYPE_TCP:
2122 packet_type |= RTE_PTYPE_L4_TCP;
2124 case PP2_INQ_L4_TYPE_UDP:
2125 packet_type |= RTE_PTYPE_L4_UDP;
2128 MRVL_LOG(DEBUG, "Failed to recognise l4 packet type");
2136 * Get offload information from the received packet descriptor.
2139 * Pointer to the received packet descriptor.
2142 * Mbuf offload flags.
2144 static inline uint64_t
2145 mrvl_desc_to_ol_flags(struct pp2_ppio_desc *desc)
2148 enum pp2_inq_desc_status status;
2150 status = pp2_ppio_inq_desc_get_l3_pkt_error(desc);
2151 if (unlikely(status != PP2_DESC_ERR_OK))
2152 flags = PKT_RX_IP_CKSUM_BAD;
2154 flags = PKT_RX_IP_CKSUM_GOOD;
2156 status = pp2_ppio_inq_desc_get_l4_pkt_error(desc);
2157 if (unlikely(status != PP2_DESC_ERR_OK))
2158 flags |= PKT_RX_L4_CKSUM_BAD;
2160 flags |= PKT_RX_L4_CKSUM_GOOD;
2166 * DPDK callback for receive.
2169 * Generic pointer to the receive queue.
2171 * Array to store received packets.
2173 * Maximum number of packets in array.
2176 * Number of packets successfully received.
2179 mrvl_rx_pkt_burst(void *rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
2181 struct mrvl_rxq *q = rxq;
2182 struct pp2_ppio_desc descs[nb_pkts];
2183 struct pp2_bpool *bpool;
2184 int i, ret, rx_done = 0;
2186 struct pp2_hif *hif;
2187 unsigned int core_id = rte_lcore_id();
2189 hif = mrvl_get_hif(q->priv, core_id);
2191 if (unlikely(!q->priv->ppio || !hif))
2194 bpool = q->priv->bpool;
2196 ret = pp2_ppio_recv(q->priv->ppio, q->priv->rxq_map[q->queue_id].tc,
2197 q->priv->rxq_map[q->queue_id].inq, descs, &nb_pkts);
2198 if (unlikely(ret < 0)) {
2199 MRVL_LOG(ERR, "Failed to receive packets");
2202 mrvl_port_bpool_size[bpool->pp2_id][bpool->id][core_id] -= nb_pkts;
2204 for (i = 0; i < nb_pkts; i++) {
2205 struct rte_mbuf *mbuf;
2206 uint8_t l3_offset, l4_offset;
2207 enum pp2_inq_desc_status status;
2210 if (likely(nb_pkts - i > MRVL_MUSDK_PREFETCH_SHIFT)) {
2211 struct pp2_ppio_desc *pref_desc;
2214 pref_desc = &descs[i + MRVL_MUSDK_PREFETCH_SHIFT];
2215 pref_addr = cookie_addr_high |
2216 pp2_ppio_inq_desc_get_cookie(pref_desc);
2217 rte_mbuf_prefetch_part1((struct rte_mbuf *)(pref_addr));
2218 rte_mbuf_prefetch_part2((struct rte_mbuf *)(pref_addr));
2221 addr = cookie_addr_high |
2222 pp2_ppio_inq_desc_get_cookie(&descs[i]);
2223 mbuf = (struct rte_mbuf *)addr;
2224 rte_pktmbuf_reset(mbuf);
2226 /* drop packet in case of mac, overrun or resource error */
2227 status = pp2_ppio_inq_desc_get_l2_pkt_error(&descs[i]);
2228 if (unlikely(status != PP2_DESC_ERR_OK)) {
2229 struct pp2_buff_inf binf = {
2230 .addr = rte_mbuf_data_iova_default(mbuf),
2231 .cookie = (uint64_t)mbuf,
2234 pp2_bpool_put_buff(hif, bpool, &binf);
2235 mrvl_port_bpool_size
2236 [bpool->pp2_id][bpool->id][core_id]++;
2241 mbuf->data_off += MRVL_PKT_EFFEC_OFFS;
2242 mbuf->pkt_len = pp2_ppio_inq_desc_get_pkt_len(&descs[i]);
2243 mbuf->data_len = mbuf->pkt_len;
2244 mbuf->port = q->port_id;
2246 mrvl_desc_to_packet_type_and_offset(&descs[i],
2249 mbuf->l2_len = l3_offset;
2250 mbuf->l3_len = l4_offset - l3_offset;
2252 if (likely(q->cksum_enabled))
2253 mbuf->ol_flags = mrvl_desc_to_ol_flags(&descs[i]);
2255 rx_pkts[rx_done++] = mbuf;
2256 q->bytes_recv += mbuf->pkt_len;
2259 if (rte_spinlock_trylock(&q->priv->lock) == 1) {
2260 num = mrvl_get_bpool_size(bpool->pp2_id, bpool->id);
2262 if (unlikely(num <= q->priv->bpool_min_size ||
2263 (!rx_done && num < q->priv->bpool_init_size))) {
2264 ret = mrvl_fill_bpool(q, MRVL_BURST_SIZE);
2266 MRVL_LOG(ERR, "Failed to fill bpool");
2267 } else if (unlikely(num > q->priv->bpool_max_size)) {
2269 int pkt_to_remove = num - q->priv->bpool_init_size;
2270 struct rte_mbuf *mbuf;
2271 struct pp2_buff_inf buff;
2274 "port-%d:%d: bpool %d oversize - remove %d buffers (pool size: %d -> %d)",
2275 bpool->pp2_id, q->priv->ppio->port_id,
2276 bpool->id, pkt_to_remove, num,
2277 q->priv->bpool_init_size);
2279 for (i = 0; i < pkt_to_remove; i++) {
2280 ret = pp2_bpool_get_buff(hif, bpool, &buff);
2283 mbuf = (struct rte_mbuf *)
2284 (cookie_addr_high | buff.cookie);
2285 rte_pktmbuf_free(mbuf);
2287 mrvl_port_bpool_size
2288 [bpool->pp2_id][bpool->id][core_id] -= i;
2290 rte_spinlock_unlock(&q->priv->lock);
2297 * Prepare offload information.
2301 * @param packet_type
2302 * Packet type bitfield.
2304 * Pointer to the pp2_ouq_l3_type structure.
2306 * Pointer to the pp2_outq_l4_type structure.
2307 * @param gen_l3_cksum
2308 * Will be set to 1 in case l3 checksum is computed.
2310 * Will be set to 1 in case l4 checksum is computed.
2313 * 0 on success, negative error value otherwise.
2316 mrvl_prepare_proto_info(uint64_t ol_flags, uint32_t packet_type,
2317 enum pp2_outq_l3_type *l3_type,
2318 enum pp2_outq_l4_type *l4_type,
2323 * Based on ol_flags prepare information
2324 * for pp2_ppio_outq_desc_set_proto_info() which setups descriptor
2327 if (ol_flags & PKT_TX_IPV4) {
2328 *l3_type = PP2_OUTQ_L3_TYPE_IPV4;
2329 *gen_l3_cksum = ol_flags & PKT_TX_IP_CKSUM ? 1 : 0;
2330 } else if (ol_flags & PKT_TX_IPV6) {
2331 *l3_type = PP2_OUTQ_L3_TYPE_IPV6;
2332 /* no checksum for ipv6 header */
2335 /* if something different then stop processing */
2339 ol_flags &= PKT_TX_L4_MASK;
2340 if ((packet_type & RTE_PTYPE_L4_TCP) &&
2341 ol_flags == PKT_TX_TCP_CKSUM) {
2342 *l4_type = PP2_OUTQ_L4_TYPE_TCP;
2344 } else if ((packet_type & RTE_PTYPE_L4_UDP) &&
2345 ol_flags == PKT_TX_UDP_CKSUM) {
2346 *l4_type = PP2_OUTQ_L4_TYPE_UDP;
2349 *l4_type = PP2_OUTQ_L4_TYPE_OTHER;
2350 /* no checksum for other type */
2358 * Release already sent buffers to bpool (buffer-pool).
2361 * Pointer to the port structure.
2363 * Pointer to the MUSDK hardware interface.
2365 * Pointer to the shadow queue.
2369 * Force releasing packets.
2372 mrvl_free_sent_buffers(struct pp2_ppio *ppio, struct pp2_hif *hif,
2373 unsigned int core_id, struct mrvl_shadow_txq *sq,
2376 struct buff_release_entry *entry;
2377 uint16_t nb_done = 0, num = 0, skip_bufs = 0;
2380 pp2_ppio_get_num_outq_done(ppio, hif, qid, &nb_done);
2382 sq->num_to_release += nb_done;
2384 if (likely(!force &&
2385 sq->num_to_release < MRVL_PP2_BUF_RELEASE_BURST_SIZE))
2388 nb_done = sq->num_to_release;
2389 sq->num_to_release = 0;
2391 for (i = 0; i < nb_done; i++) {
2392 entry = &sq->ent[sq->tail + num];
2393 if (unlikely(!entry->buff.addr)) {
2395 "Shadow memory @%d: cookie(%lx), pa(%lx)!",
2396 sq->tail, (u64)entry->buff.cookie,
2397 (u64)entry->buff.addr);
2402 if (unlikely(!entry->bpool)) {
2403 struct rte_mbuf *mbuf;
2405 mbuf = (struct rte_mbuf *)
2406 (cookie_addr_high | entry->buff.cookie);
2407 rte_pktmbuf_free(mbuf);
2412 mrvl_port_bpool_size
2413 [entry->bpool->pp2_id][entry->bpool->id][core_id]++;
2415 if (unlikely(sq->tail + num == MRVL_PP2_TX_SHADOWQ_SIZE))
2420 pp2_bpool_put_buffs(hif, &sq->ent[sq->tail], &num);
2422 sq->tail = (sq->tail + num) & MRVL_PP2_TX_SHADOWQ_MASK;
2429 pp2_bpool_put_buffs(hif, &sq->ent[sq->tail], &num);
2430 sq->tail = (sq->tail + num) & MRVL_PP2_TX_SHADOWQ_MASK;
2436 * DPDK callback for transmit.
2439 * Generic pointer transmit queue.
2441 * Packets to transmit.
2443 * Number of packets in array.
2446 * Number of packets successfully transmitted.
2449 mrvl_tx_pkt_burst(void *txq, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2451 struct mrvl_txq *q = txq;
2452 struct mrvl_shadow_txq *sq;
2453 struct pp2_hif *hif;
2454 struct pp2_ppio_desc descs[nb_pkts];
2455 unsigned int core_id = rte_lcore_id();
2456 int i, ret, bytes_sent = 0;
2457 uint16_t num, sq_free_size;
2460 hif = mrvl_get_hif(q->priv, core_id);
2461 sq = &q->shadow_txqs[core_id];
2463 if (unlikely(!q->priv->ppio || !hif))
2467 mrvl_free_sent_buffers(q->priv->ppio, hif, core_id,
2468 sq, q->queue_id, 0);
2470 sq_free_size = MRVL_PP2_TX_SHADOWQ_SIZE - sq->size - 1;
2471 if (unlikely(nb_pkts > sq_free_size)) {
2473 "No room in shadow queue for %d packets! %d packets will be sent.",
2474 nb_pkts, sq_free_size);
2475 nb_pkts = sq_free_size;
2478 for (i = 0; i < nb_pkts; i++) {
2479 struct rte_mbuf *mbuf = tx_pkts[i];
2480 int gen_l3_cksum, gen_l4_cksum;
2481 enum pp2_outq_l3_type l3_type;
2482 enum pp2_outq_l4_type l4_type;
2484 if (likely(nb_pkts - i > MRVL_MUSDK_PREFETCH_SHIFT)) {
2485 struct rte_mbuf *pref_pkt_hdr;
2487 pref_pkt_hdr = tx_pkts[i + MRVL_MUSDK_PREFETCH_SHIFT];
2488 rte_mbuf_prefetch_part1(pref_pkt_hdr);
2489 rte_mbuf_prefetch_part2(pref_pkt_hdr);
2492 mrvl_fill_shadowq(sq, mbuf);
2493 mrvl_fill_desc(&descs[i], mbuf);
2495 bytes_sent += rte_pktmbuf_pkt_len(mbuf);
2497 * in case unsupported ol_flags were passed
2498 * do not update descriptor offload information
2500 ret = mrvl_prepare_proto_info(mbuf->ol_flags, mbuf->packet_type,
2501 &l3_type, &l4_type, &gen_l3_cksum,
2506 pp2_ppio_outq_desc_set_proto_info(&descs[i], l3_type, l4_type,
2508 mbuf->l2_len + mbuf->l3_len,
2509 gen_l3_cksum, gen_l4_cksum);
2513 pp2_ppio_send(q->priv->ppio, hif, q->queue_id, descs, &nb_pkts);
2514 /* number of packets that were not sent */
2515 if (unlikely(num > nb_pkts)) {
2516 for (i = nb_pkts; i < num; i++) {
2517 sq->head = (MRVL_PP2_TX_SHADOWQ_SIZE + sq->head - 1) &
2518 MRVL_PP2_TX_SHADOWQ_MASK;
2519 addr = cookie_addr_high | sq->ent[sq->head].buff.cookie;
2521 rte_pktmbuf_pkt_len((struct rte_mbuf *)addr);
2523 sq->size -= num - nb_pkts;
2526 q->bytes_sent += bytes_sent;
2531 /** DPDK callback for S/G transmit.
2534 * Generic pointer transmit queue.
2536 * Packets to transmit.
2538 * Number of packets in array.
2541 * Number of packets successfully transmitted.
2544 mrvl_tx_sg_pkt_burst(void *txq, struct rte_mbuf **tx_pkts,
2547 struct mrvl_txq *q = txq;
2548 struct mrvl_shadow_txq *sq;
2549 struct pp2_hif *hif;
2550 struct pp2_ppio_desc descs[nb_pkts * PP2_PPIO_DESC_NUM_FRAGS];
2551 struct pp2_ppio_sg_pkts pkts;
2552 uint8_t frags[nb_pkts];
2553 unsigned int core_id = rte_lcore_id();
2554 int i, j, ret, bytes_sent = 0;
2555 int tail, tail_first;
2556 uint16_t num, sq_free_size;
2557 uint16_t nb_segs, total_descs = 0;
2560 hif = mrvl_get_hif(q->priv, core_id);
2561 sq = &q->shadow_txqs[core_id];
2565 if (unlikely(!q->priv->ppio || !hif))
2569 mrvl_free_sent_buffers(q->priv->ppio, hif, core_id,
2570 sq, q->queue_id, 0);
2572 /* Save shadow queue free size */
2573 sq_free_size = MRVL_PP2_TX_SHADOWQ_SIZE - sq->size - 1;
2576 for (i = 0; i < nb_pkts; i++) {
2577 struct rte_mbuf *mbuf = tx_pkts[i];
2578 struct rte_mbuf *seg = NULL;
2579 int gen_l3_cksum, gen_l4_cksum;
2580 enum pp2_outq_l3_type l3_type;
2581 enum pp2_outq_l4_type l4_type;
2583 nb_segs = mbuf->nb_segs;
2585 total_descs += nb_segs;
2588 * Check if total_descs does not exceed
2589 * shadow queue free size
2591 if (unlikely(total_descs > sq_free_size)) {
2592 total_descs -= nb_segs;
2594 "No room in shadow queue for %d packets! "
2595 "%d packets will be sent.\n",
2600 /* Check if nb_segs does not exceed the max nb of desc per
2603 if (nb_segs > PP2_PPIO_DESC_NUM_FRAGS) {
2604 total_descs -= nb_segs;
2606 "Too many segments. Packet won't be sent.\n");
2610 if (likely(nb_pkts - i > MRVL_MUSDK_PREFETCH_SHIFT)) {
2611 struct rte_mbuf *pref_pkt_hdr;
2613 pref_pkt_hdr = tx_pkts[i + MRVL_MUSDK_PREFETCH_SHIFT];
2614 rte_mbuf_prefetch_part1(pref_pkt_hdr);
2615 rte_mbuf_prefetch_part2(pref_pkt_hdr);
2618 pkts.frags[pkts.num] = nb_segs;
2622 for (j = 0; j < nb_segs - 1; j++) {
2623 /* For the subsequent segments, set shadow queue
2626 mrvl_fill_shadowq(sq, NULL);
2627 mrvl_fill_desc(&descs[tail], seg);
2632 /* Put first mbuf info in last shadow queue entry */
2633 mrvl_fill_shadowq(sq, mbuf);
2634 /* Update descriptor with last segment */
2635 mrvl_fill_desc(&descs[tail++], seg);
2637 bytes_sent += rte_pktmbuf_pkt_len(mbuf);
2638 /* In case unsupported ol_flags were passed
2639 * do not update descriptor offload information
2641 ret = mrvl_prepare_proto_info(mbuf->ol_flags, mbuf->packet_type,
2642 &l3_type, &l4_type, &gen_l3_cksum,
2647 pp2_ppio_outq_desc_set_proto_info(&descs[tail_first], l3_type,
2648 l4_type, mbuf->l2_len,
2649 mbuf->l2_len + mbuf->l3_len,
2650 gen_l3_cksum, gen_l4_cksum);
2654 pp2_ppio_send_sg(q->priv->ppio, hif, q->queue_id, descs,
2655 &total_descs, &pkts);
2656 /* number of packets that were not sent */
2657 if (unlikely(num > total_descs)) {
2658 for (i = total_descs; i < num; i++) {
2659 sq->head = (MRVL_PP2_TX_SHADOWQ_SIZE + sq->head - 1) &
2660 MRVL_PP2_TX_SHADOWQ_MASK;
2662 addr = sq->ent[sq->head].buff.cookie;
2665 rte_pktmbuf_pkt_len((struct rte_mbuf *)
2666 (cookie_addr_high | addr));
2668 sq->size -= num - total_descs;
2672 q->bytes_sent += bytes_sent;
2678 * Initialize packet processor.
2681 * 0 on success, negative error value otherwise.
2686 struct pp2_init_params init_params;
2688 memset(&init_params, 0, sizeof(init_params));
2689 init_params.hif_reserved_map = MRVL_MUSDK_HIFS_RESERVED;
2690 init_params.bm_pool_reserved_map = MRVL_MUSDK_BPOOLS_RESERVED;
2691 init_params.rss_tbl_reserved_map = MRVL_MUSDK_RSS_RESERVED;
2693 return pp2_init(&init_params);
2697 * Deinitialize packet processor.
2700 * 0 on success, negative error value otherwise.
2703 mrvl_deinit_pp2(void)
2709 * Create private device structure.
2712 * Pointer to the port name passed in the initialization parameters.
2715 * Pointer to the newly allocated private device structure.
2717 static struct mrvl_priv *
2718 mrvl_priv_create(const char *dev_name)
2720 struct pp2_bpool_params bpool_params;
2721 char match[MRVL_MATCH_LEN];
2722 struct mrvl_priv *priv;
2725 priv = rte_zmalloc_socket(dev_name, sizeof(*priv), 0, rte_socket_id());
2729 ret = pp2_netdev_get_ppio_info((char *)(uintptr_t)dev_name,
2730 &priv->pp_id, &priv->ppio_id);
2734 bpool_bit = mrvl_reserve_bit(&used_bpools[priv->pp_id],
2735 PP2_BPOOL_NUM_POOLS);
2738 priv->bpool_bit = bpool_bit;
2740 snprintf(match, sizeof(match), "pool-%d:%d", priv->pp_id,
2742 memset(&bpool_params, 0, sizeof(bpool_params));
2743 bpool_params.match = match;
2744 bpool_params.buff_len = MRVL_PKT_SIZE_MAX + MRVL_PKT_EFFEC_OFFS;
2745 ret = pp2_bpool_init(&bpool_params, &priv->bpool);
2747 goto out_clear_bpool_bit;
2749 priv->ppio_params.type = PP2_PPIO_T_NIC;
2750 rte_spinlock_init(&priv->lock);
2753 out_clear_bpool_bit:
2754 used_bpools[priv->pp_id] &= ~(1 << priv->bpool_bit);
2761 * Create device representing Ethernet port.
2764 * Pointer to the port's name.
2767 * 0 on success, negative error value otherwise.
2770 mrvl_eth_dev_create(struct rte_vdev_device *vdev, const char *name)
2772 int ret, fd = socket(AF_INET, SOCK_DGRAM, 0);
2773 struct rte_eth_dev *eth_dev;
2774 struct mrvl_priv *priv;
2777 eth_dev = rte_eth_dev_allocate(name);
2781 priv = mrvl_priv_create(name);
2786 eth_dev->data->dev_private = priv;
2788 eth_dev->data->mac_addrs =
2789 rte_zmalloc("mac_addrs",
2790 RTE_ETHER_ADDR_LEN * MRVL_MAC_ADDRS_MAX, 0);
2791 if (!eth_dev->data->mac_addrs) {
2792 MRVL_LOG(ERR, "Failed to allocate space for eth addrs");
2797 memset(&req, 0, sizeof(req));
2798 strcpy(req.ifr_name, name);
2799 ret = ioctl(fd, SIOCGIFHWADDR, &req);
2803 memcpy(eth_dev->data->mac_addrs[0].addr_bytes,
2804 req.ifr_addr.sa_data, RTE_ETHER_ADDR_LEN);
2806 eth_dev->data->kdrv = RTE_KDRV_NONE;
2807 eth_dev->device = &vdev->device;
2808 eth_dev->rx_pkt_burst = mrvl_rx_pkt_burst;
2809 mrvl_set_tx_function(eth_dev);
2810 eth_dev->dev_ops = &mrvl_ops;
2812 rte_eth_dev_probing_finish(eth_dev);
2815 rte_eth_dev_release_port(eth_dev);
2821 * Cleanup previously created device representing Ethernet port.
2824 * Pointer to the port name.
2827 mrvl_eth_dev_destroy(const char *name)
2829 struct rte_eth_dev *eth_dev;
2830 struct mrvl_priv *priv;
2832 eth_dev = rte_eth_dev_allocated(name);
2836 priv = eth_dev->data->dev_private;
2837 pp2_bpool_deinit(priv->bpool);
2838 used_bpools[priv->pp_id] &= ~(1 << priv->bpool_bit);
2839 rte_eth_dev_release_port(eth_dev);
2843 * Callback used by rte_kvargs_process() during argument parsing.
2846 * Pointer to the parsed key (unused).
2848 * Pointer to the parsed value.
2850 * Pointer to the extra arguments which contains address of the
2851 * table of pointers to parsed interface names.
2857 mrvl_get_ifnames(const char *key __rte_unused, const char *value,
2860 struct mrvl_ifnames *ifnames = extra_args;
2862 ifnames->names[ifnames->idx++] = value;
2868 * Deinitialize per-lcore MUSDK hardware interfaces (hifs).
2871 mrvl_deinit_hifs(void)
2875 for (i = mrvl_lcore_first; i <= mrvl_lcore_last; i++) {
2877 pp2_hif_deinit(hifs[i]);
2879 used_hifs = MRVL_MUSDK_HIFS_RESERVED;
2880 memset(hifs, 0, sizeof(hifs));
2884 * DPDK callback to register the virtual device.
2887 * Pointer to the virtual device.
2890 * 0 on success, negative error value otherwise.
2893 rte_pmd_mrvl_probe(struct rte_vdev_device *vdev)
2895 struct rte_kvargs *kvlist;
2896 struct mrvl_ifnames ifnames;
2898 uint32_t i, ifnum, cfgnum;
2901 params = rte_vdev_device_args(vdev);
2905 kvlist = rte_kvargs_parse(params, valid_args);
2909 ifnum = rte_kvargs_count(kvlist, MRVL_IFACE_NAME_ARG);
2910 if (ifnum > RTE_DIM(ifnames.names))
2911 goto out_free_kvlist;
2914 rte_kvargs_process(kvlist, MRVL_IFACE_NAME_ARG,
2915 mrvl_get_ifnames, &ifnames);
2919 * The below system initialization should be done only once,
2920 * on the first provided configuration file
2922 if (!mrvl_qos_cfg) {
2923 cfgnum = rte_kvargs_count(kvlist, MRVL_CFG_ARG);
2924 MRVL_LOG(INFO, "Parsing config file!");
2926 MRVL_LOG(ERR, "Cannot handle more than one config file!");
2927 goto out_free_kvlist;
2928 } else if (cfgnum == 1) {
2929 rte_kvargs_process(kvlist, MRVL_CFG_ARG,
2930 mrvl_get_qoscfg, &mrvl_qos_cfg);
2937 MRVL_LOG(INFO, "Perform MUSDK initializations");
2939 ret = rte_mvep_init(MVEP_MOD_T_PP2, kvlist);
2941 goto out_free_kvlist;
2943 ret = mrvl_init_pp2();
2945 MRVL_LOG(ERR, "Failed to init PP!");
2946 rte_mvep_deinit(MVEP_MOD_T_PP2);
2947 goto out_free_kvlist;
2950 memset(mrvl_port_bpool_size, 0, sizeof(mrvl_port_bpool_size));
2951 memset(mrvl_port_to_bpool_lookup, 0, sizeof(mrvl_port_to_bpool_lookup));
2953 mrvl_lcore_first = RTE_MAX_LCORE;
2954 mrvl_lcore_last = 0;
2957 for (i = 0; i < ifnum; i++) {
2958 MRVL_LOG(INFO, "Creating %s", ifnames.names[i]);
2959 ret = mrvl_eth_dev_create(vdev, ifnames.names[i]);
2963 mrvl_dev_num += ifnum;
2965 rte_kvargs_free(kvlist);
2970 mrvl_eth_dev_destroy(ifnames.names[i]);
2972 if (mrvl_dev_num == 0) {
2974 rte_mvep_deinit(MVEP_MOD_T_PP2);
2977 rte_kvargs_free(kvlist);
2983 * DPDK callback to remove virtual device.
2986 * Pointer to the removed virtual device.
2989 * 0 on success, negative error value otherwise.
2992 rte_pmd_mrvl_remove(struct rte_vdev_device *vdev)
2997 name = rte_vdev_device_name(vdev);
3001 MRVL_LOG(INFO, "Removing %s", name);
3003 RTE_ETH_FOREACH_DEV(i) { /* FIXME: removing all devices! */
3004 char ifname[RTE_ETH_NAME_MAX_LEN];
3006 rte_eth_dev_get_name_by_port(i, ifname);
3007 mrvl_eth_dev_destroy(ifname);
3011 if (mrvl_dev_num == 0) {
3012 MRVL_LOG(INFO, "Perform MUSDK deinit");
3015 rte_mvep_deinit(MVEP_MOD_T_PP2);
3021 static struct rte_vdev_driver pmd_mrvl_drv = {
3022 .probe = rte_pmd_mrvl_probe,
3023 .remove = rte_pmd_mrvl_remove,
3026 RTE_PMD_REGISTER_VDEV(net_mvpp2, pmd_mrvl_drv);
3027 RTE_PMD_REGISTER_ALIAS(net_mvpp2, eth_mvpp2);
3029 RTE_INIT(mrvl_init_log)
3031 mrvl_logtype = rte_log_register("pmd.net.mvpp2");
3032 if (mrvl_logtype >= 0)
3033 rte_log_set_level(mrvl_logtype, RTE_LOG_NOTICE);