4 * Copyright 2015 6WIND S.A.
5 * Copyright 2015 Mellanox.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of 6WIND S.A. nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #ifndef RTE_PMD_MLX5_RXTX_H_
35 #define RTE_PMD_MLX5_RXTX_H_
41 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
43 #pragma GCC diagnostic ignored "-Wpedantic"
45 #include <infiniband/verbs.h>
46 #include <infiniband/mlx5_hw.h>
48 #pragma GCC diagnostic error "-Wpedantic"
51 /* DPDK headers don't like -pedantic. */
53 #pragma GCC diagnostic ignored "-Wpedantic"
56 #include <rte_mempool.h>
57 #include <rte_common.h>
59 #pragma GCC diagnostic error "-Wpedantic"
62 #include "mlx5_utils.h"
64 #include "mlx5_autoconf.h"
65 #include "mlx5_defs.h"
68 struct mlx5_rxq_stats {
69 unsigned int idx; /**< Mapping index. */
70 #ifdef MLX5_PMD_SOFT_COUNTERS
71 uint64_t ipackets; /**< Total of successfully received packets. */
72 uint64_t ibytes; /**< Total of successfully received bytes. */
74 uint64_t idropped; /**< Total of packets dropped when RX ring full. */
75 uint64_t rx_nombuf; /**< Total of RX mbuf allocation failures. */
78 struct mlx5_txq_stats {
79 unsigned int idx; /**< Mapping index. */
80 #ifdef MLX5_PMD_SOFT_COUNTERS
81 uint64_t opackets; /**< Total of successfully sent packets. */
82 uint64_t obytes; /**< Total of successfully sent bytes. */
84 uint64_t odropped; /**< Total of packets not sent when TX ring full. */
87 /* Flow director queue structure. */
89 struct ibv_qp *qp; /* Associated RX QP. */
90 struct ibv_exp_rwq_ind_table *ind_table; /* Indirection table. */
91 struct ibv_exp_wq *wq; /* Work queue. */
92 struct ibv_cq *cq; /* Completion queue. */
97 /* Compressed CQE context. */
99 uint16_t ai; /* Array index. */
100 uint16_t ca; /* Current array index. */
101 uint16_t na; /* Next array index. */
102 uint16_t cq_ci; /* The next CQE. */
103 uint32_t cqe_cnt; /* Number of CQEs. */
106 /* RX queue descriptor. */
108 unsigned int csum:1; /* Enable checksum offloading. */
109 unsigned int csum_l2tun:1; /* Same for L2 tunnels. */
110 unsigned int vlan_strip:1; /* Enable VLAN stripping. */
111 unsigned int crc_present:1; /* CRC must be subtracted. */
112 unsigned int sges_n:2; /* Log 2 of SGEs (max buffers per packet). */
113 unsigned int cqe_n:4; /* Log 2 of CQ elements. */
114 unsigned int elts_n:4; /* Log 2 of Mbufs. */
115 unsigned int port_id:8;
116 unsigned int rss_hash:1; /* RSS hash result is enabled. */
117 unsigned int mark:1; /* Marked flow available on the queue. */
118 unsigned int pending_err:1; /* CQE error needs to be handled. */
119 unsigned int trim_elts:1; /* Whether elts needs clean-up. */
120 unsigned int :6; /* Remaining bits. */
121 volatile uint32_t *rq_db;
122 volatile uint32_t *cq_db;
126 volatile struct mlx5_wqe_data_seg(*wqes)[];
127 volatile struct mlx5_cqe(*cqes)[];
128 struct rxq_zip zip; /* Compressed context. */
129 struct rte_mbuf *(*elts)[];
130 struct rte_mempool *mp;
131 struct mlx5_rxq_stats stats;
132 uint64_t mbuf_initializer; /* Default rearm_data for vectorized Rx. */
133 struct rte_mbuf fake_mbuf; /* elts padding for vectorized Rx. */
134 } __rte_cache_aligned;
136 /* RX queue control descriptor. */
138 struct priv *priv; /* Back pointer to private data. */
139 struct ibv_cq *cq; /* Completion Queue. */
140 struct ibv_exp_wq *wq; /* Work Queue. */
141 struct fdir_queue *fdir_queue; /* Flow director queue. */
142 struct ibv_mr *mr; /* Memory Region (for mp). */
143 struct ibv_comp_channel *channel;
144 unsigned int socket; /* CPU socket ID for allocations. */
145 struct rxq rxq; /* Data path structure. */
148 /* Hash RX queue types. */
159 /* Flow structure with Ethernet specification. It is packed to prevent padding
160 * between attr and spec as this layout is expected by libibverbs. */
161 struct flow_attr_spec_eth {
162 struct ibv_exp_flow_attr attr;
163 struct ibv_exp_flow_spec_eth spec;
164 } __attribute__((packed));
166 /* Define a struct flow_attr_spec_eth object as an array of at least
167 * "size" bytes. Room after the first index is normally used to store
168 * extra flow specifications. */
169 #define FLOW_ATTR_SPEC_ETH(name, size) \
170 struct flow_attr_spec_eth name \
171 [((size) / sizeof(struct flow_attr_spec_eth)) + \
172 !!((size) % sizeof(struct flow_attr_spec_eth))]
174 /* Initialization data for hash RX queue. */
175 struct hash_rxq_init {
176 uint64_t hash_fields; /* Fields that participate in the hash. */
177 uint64_t dpdk_rss_hf; /* Matching DPDK RSS hash fields. */
178 unsigned int flow_priority; /* Flow priority to use. */
181 enum ibv_exp_flow_spec_type type;
184 struct ibv_exp_flow_spec_tcp_udp tcp_udp;
185 struct ibv_exp_flow_spec_ipv4 ipv4;
186 struct ibv_exp_flow_spec_ipv6 ipv6;
187 struct ibv_exp_flow_spec_eth eth;
188 } flow_spec; /* Flow specification template. */
189 const struct hash_rxq_init *underlayer; /* Pointer to underlayer. */
192 /* Initialization data for indirection table. */
193 struct ind_table_init {
194 unsigned int max_size; /* Maximum number of WQs. */
195 /* Hash RX queues using this table. */
196 unsigned int hash_types;
197 unsigned int hash_types_n;
200 /* Initialization data for special flows. */
201 struct special_flow_init {
202 uint8_t dst_mac_val[6];
203 uint8_t dst_mac_mask[6];
204 unsigned int hash_types;
205 unsigned int per_vlan:1;
208 enum hash_rxq_flow_type {
209 HASH_RXQ_FLOW_TYPE_PROMISC,
210 HASH_RXQ_FLOW_TYPE_ALLMULTI,
211 HASH_RXQ_FLOW_TYPE_BROADCAST,
212 HASH_RXQ_FLOW_TYPE_IPV6MULTI,
213 HASH_RXQ_FLOW_TYPE_MAC,
217 static inline const char *
218 hash_rxq_flow_type_str(enum hash_rxq_flow_type flow_type)
221 case HASH_RXQ_FLOW_TYPE_PROMISC:
222 return "promiscuous";
223 case HASH_RXQ_FLOW_TYPE_ALLMULTI:
224 return "allmulticast";
225 case HASH_RXQ_FLOW_TYPE_BROADCAST:
227 case HASH_RXQ_FLOW_TYPE_IPV6MULTI:
228 return "IPv6 multicast";
229 case HASH_RXQ_FLOW_TYPE_MAC:
237 struct priv *priv; /* Back pointer to private data. */
238 struct ibv_qp *qp; /* Hash RX QP. */
239 enum hash_rxq_type type; /* Hash RX queue type. */
240 /* MAC flow steering rules, one per VLAN ID. */
241 struct ibv_exp_flow *mac_flow
242 [MLX5_MAX_MAC_ADDRESSES][MLX5_MAX_VLAN_IDS];
243 struct ibv_exp_flow *special_flow
244 [MLX5_MAX_SPECIAL_FLOWS][MLX5_MAX_VLAN_IDS];
247 /* TX queue descriptor. */
250 uint16_t elts_head; /* Current counter in (*elts)[]. */
251 uint16_t elts_tail; /* Counter of first element awaiting completion. */
252 uint16_t elts_comp; /* Counter since last completion request. */
253 uint16_t mpw_comp; /* WQ index since last completion request. */
254 uint16_t cq_ci; /* Consumer index for completion queue. */
255 uint16_t cq_pi; /* Producer index for completion queue. */
256 uint16_t wqe_ci; /* Consumer index for work queue. */
257 uint16_t wqe_pi; /* Producer index for work queue. */
258 uint16_t elts_n:4; /* (*elts)[] length (in log2). */
259 uint16_t cqe_n:4; /* Number of CQ elements (in log2). */
260 uint16_t wqe_n:4; /* Number of of WQ elements (in log2). */
261 uint16_t inline_en:1; /* When set inline is enabled. */
262 uint16_t tso_en:1; /* When set hardware TSO is enabled. */
263 uint16_t tunnel_en:1;
264 /* When set TX offload for tunneled packets are supported. */
265 uint16_t mpw_hdr_dseg:1; /* Enable DSEGs in the title WQEBB. */
266 uint16_t max_inline; /* Multiple of RTE_CACHE_LINE_SIZE to inline. */
267 uint16_t inline_max_packet_sz; /* Max packet size for inlining. */
268 uint32_t qp_num_8s; /* QP number shifted by 8. */
269 uint32_t flags; /* Flags for Tx Queue. */
270 volatile struct mlx5_cqe (*cqes)[]; /* Completion queue. */
271 volatile void *wqes; /* Work queue (use volatile to write into). */
272 volatile uint32_t *qp_db; /* Work queue doorbell. */
273 volatile uint32_t *cq_db; /* Completion queue doorbell. */
274 volatile void *bf_reg; /* Blueflame register. */
276 uintptr_t start; /* Start address of MR */
277 uintptr_t end; /* End address of MR */
278 struct ibv_mr *mr; /* Memory Region (for mp). */
279 uint32_t lkey; /* htonl(mr->lkey) */
280 } mp2mr[MLX5_PMD_TX_MP_CACHE]; /* MP to MR translation table. */
281 uint16_t mr_cache_idx; /* Index of last hit entry. */
282 struct rte_mbuf *(*elts)[]; /* TX elements. */
283 struct mlx5_txq_stats stats; /* TX queue counters. */
284 } __rte_cache_aligned;
286 /* TX queue control descriptor. */
288 struct priv *priv; /* Back pointer to private data. */
289 struct ibv_cq *cq; /* Completion Queue. */
290 struct ibv_qp *qp; /* Queue Pair. */
291 unsigned int socket; /* CPU socket ID for allocations. */
292 struct txq txq; /* Data path structure. */
297 extern const struct hash_rxq_init hash_rxq_init[];
298 extern const unsigned int hash_rxq_init_n;
300 extern uint8_t rss_hash_default_key[];
301 extern const size_t rss_hash_default_key_len;
303 size_t priv_flow_attr(struct priv *, struct ibv_exp_flow_attr *,
304 size_t, enum hash_rxq_type);
305 int priv_create_hash_rxqs(struct priv *);
306 void priv_destroy_hash_rxqs(struct priv *);
307 int priv_allow_flow_type(struct priv *, enum hash_rxq_flow_type);
308 int priv_rehash_flows(struct priv *);
309 void rxq_cleanup(struct rxq_ctrl *);
310 int mlx5_rx_queue_setup(struct rte_eth_dev *, uint16_t, uint16_t, unsigned int,
311 const struct rte_eth_rxconf *, struct rte_mempool *);
312 void mlx5_rx_queue_release(void *);
313 uint16_t mlx5_rx_burst_secondary_setup(void *, struct rte_mbuf **, uint16_t);
314 int priv_rx_intr_vec_enable(struct priv *priv);
315 void priv_rx_intr_vec_disable(struct priv *priv);
316 #ifdef HAVE_UPDATE_CQ_CI
317 int mlx5_rx_intr_enable(struct rte_eth_dev *dev, uint16_t rx_queue_id);
318 int mlx5_rx_intr_disable(struct rte_eth_dev *dev, uint16_t rx_queue_id);
319 #endif /* HAVE_UPDATE_CQ_CI */
323 void txq_cleanup(struct txq_ctrl *);
324 int txq_ctrl_setup(struct rte_eth_dev *, struct txq_ctrl *, uint16_t,
325 unsigned int, const struct rte_eth_txconf *);
326 int mlx5_tx_queue_setup(struct rte_eth_dev *, uint16_t, uint16_t, unsigned int,
327 const struct rte_eth_txconf *);
328 void mlx5_tx_queue_release(void *);
329 uint16_t mlx5_tx_burst_secondary_setup(void *, struct rte_mbuf **, uint16_t);
333 extern uint32_t mlx5_ptype_table[];
335 void mlx5_set_ptype_table(void);
336 uint16_t mlx5_tx_burst(void *, struct rte_mbuf **, uint16_t);
337 uint16_t mlx5_tx_burst_mpw(void *, struct rte_mbuf **, uint16_t);
338 uint16_t mlx5_tx_burst_mpw_inline(void *, struct rte_mbuf **, uint16_t);
339 uint16_t mlx5_tx_burst_empw(void *, struct rte_mbuf **, uint16_t);
340 uint16_t mlx5_rx_burst(void *, struct rte_mbuf **, uint16_t);
341 uint16_t removed_tx_burst(void *, struct rte_mbuf **, uint16_t);
342 uint16_t removed_rx_burst(void *, struct rte_mbuf **, uint16_t);
343 int mlx5_rx_descriptor_status(void *, uint16_t);
344 int mlx5_tx_descriptor_status(void *, uint16_t);
346 /* Vectorized version of mlx5_rxtx.c */
347 int priv_check_raw_vec_tx_support(struct priv *);
348 int priv_check_vec_tx_support(struct priv *);
349 int rxq_check_vec_support(struct rxq *);
350 int priv_check_vec_rx_support(struct priv *);
351 void priv_prep_vec_rx_function(struct priv *);
352 uint16_t mlx5_tx_burst_raw_vec(void *, struct rte_mbuf **, uint16_t);
353 uint16_t mlx5_tx_burst_vec(void *, struct rte_mbuf **, uint16_t);
354 uint16_t mlx5_rx_burst_vec(void *, struct rte_mbuf **, uint16_t);
358 struct ibv_mr *mlx5_mp2mr(struct ibv_pd *, struct rte_mempool *);
359 void txq_mp2mr_iter(struct rte_mempool *, void *);
360 uint32_t txq_mp2mr_reg(struct txq *, struct rte_mempool *, unsigned int);
364 * Verify or set magic value in CQE.
373 check_cqe_seen(volatile struct mlx5_cqe *cqe)
375 static const uint8_t magic[] = "seen";
376 volatile uint8_t (*buf)[sizeof(cqe->rsvd0)] = &cqe->rsvd0;
380 for (i = 0; i < sizeof(magic) && i < sizeof(*buf); ++i)
381 if (!ret || (*buf)[i] != magic[i]) {
383 (*buf)[i] = magic[i];
390 * Check whether CQE is valid.
395 * Size of completion queue.
400 * 0 on success, 1 on failure.
402 static __rte_always_inline int
403 check_cqe(volatile struct mlx5_cqe *cqe,
404 unsigned int cqes_n, const uint16_t ci)
406 uint16_t idx = ci & cqes_n;
407 uint8_t op_own = cqe->op_own;
408 uint8_t op_owner = MLX5_CQE_OWNER(op_own);
409 uint8_t op_code = MLX5_CQE_OPCODE(op_own);
411 if (unlikely((op_owner != (!!(idx))) || (op_code == MLX5_CQE_INVALID)))
412 return 1; /* No CQE. */
414 if ((op_code == MLX5_CQE_RESP_ERR) ||
415 (op_code == MLX5_CQE_REQ_ERR)) {
416 volatile struct mlx5_err_cqe *err_cqe = (volatile void *)cqe;
417 uint8_t syndrome = err_cqe->syndrome;
419 if ((syndrome == MLX5_CQE_SYNDROME_LOCAL_LENGTH_ERR) ||
420 (syndrome == MLX5_CQE_SYNDROME_REMOTE_ABORTED_ERR))
422 if (!check_cqe_seen(cqe))
423 ERROR("unexpected CQE error %u (0x%02x)"
425 op_code, op_code, syndrome);
427 } else if ((op_code != MLX5_CQE_RESP_SEND) &&
428 (op_code != MLX5_CQE_REQ)) {
429 if (!check_cqe_seen(cqe))
430 ERROR("unexpected CQE opcode %u (0x%02x)",
439 * Return the address of the WQE.
442 * Pointer to TX queue structure.
444 * WQE consumer index.
449 static inline uintptr_t *
450 tx_mlx5_wqe(struct txq *txq, uint16_t ci)
452 ci &= ((1 << txq->wqe_n) - 1);
453 return (uintptr_t *)((uintptr_t)txq->wqes + ci * MLX5_WQE_SIZE);
457 * Manage TX completions.
459 * When sending a burst, mlx5_tx_burst() posts several WRs.
462 * Pointer to TX queue structure.
464 static __rte_always_inline void
465 mlx5_tx_complete(struct txq *txq)
467 const uint16_t elts_n = 1 << txq->elts_n;
468 const uint16_t elts_m = elts_n - 1;
469 const unsigned int cqe_n = 1 << txq->cqe_n;
470 const unsigned int cqe_cnt = cqe_n - 1;
471 uint16_t elts_free = txq->elts_tail;
473 uint16_t cq_ci = txq->cq_ci;
474 volatile struct mlx5_cqe *cqe = NULL;
475 volatile struct mlx5_wqe_ctrl *ctrl;
476 struct rte_mbuf *m, *free[elts_n];
477 struct rte_mempool *pool = NULL;
478 unsigned int blk_n = 0;
480 cqe = &(*txq->cqes)[cq_ci & cqe_cnt];
481 if (unlikely(check_cqe(cqe, cqe_n, cq_ci)))
484 if ((MLX5_CQE_OPCODE(cqe->op_own) == MLX5_CQE_RESP_ERR) ||
485 (MLX5_CQE_OPCODE(cqe->op_own) == MLX5_CQE_REQ_ERR)) {
486 if (!check_cqe_seen(cqe))
487 ERROR("unexpected error CQE, TX stopped");
492 txq->wqe_pi = ntohs(cqe->wqe_counter);
493 ctrl = (volatile struct mlx5_wqe_ctrl *)
494 tx_mlx5_wqe(txq, txq->wqe_pi);
495 elts_tail = ctrl->ctrl3;
496 assert((elts_tail & elts_m) < (1 << txq->wqe_n));
498 while (elts_free != elts_tail) {
499 m = rte_pktmbuf_prefree_seg((*txq->elts)[elts_free++ & elts_m]);
500 if (likely(m != NULL)) {
501 if (likely(m->pool == pool)) {
504 if (likely(pool != NULL))
505 rte_mempool_put_bulk(pool,
515 rte_mempool_put_bulk(pool, (void *)free, blk_n);
517 elts_free = txq->elts_tail;
519 while (elts_free != elts_tail) {
520 memset(&(*txq->elts)[elts_free & elts_m],
522 sizeof((*txq->elts)[elts_free & elts_m]));
527 txq->elts_tail = elts_tail;
528 /* Update the consumer index. */
530 *txq->cq_db = htonl(cq_ci);
534 * Get Memory Pool (MP) from mbuf. If mbuf is indirect, the pool from which
535 * the cloned mbuf is allocated is returned instead.
541 * Memory pool where data is located for given mbuf.
543 static struct rte_mempool *
544 mlx5_tx_mb2mp(struct rte_mbuf *buf)
546 if (unlikely(RTE_MBUF_INDIRECT(buf)))
547 return rte_mbuf_from_indirect(buf)->pool;
552 * Get Memory Region (MR) <-> rte_mbuf association from txq->mp2mr[].
553 * Add MP to txq->mp2mr[] if it's not registered yet. If mp2mr[] is full,
554 * remove an entry first.
557 * Pointer to TX queue structure.
559 * Memory Pool for which a Memory Region lkey must be returned.
562 * mr->lkey on success, (uint32_t)-1 on failure.
564 static __rte_always_inline uint32_t
565 mlx5_tx_mb2mr(struct txq *txq, struct rte_mbuf *mb)
567 uint16_t i = txq->mr_cache_idx;
568 uintptr_t addr = rte_pktmbuf_mtod(mb, uintptr_t);
570 assert(i < RTE_DIM(txq->mp2mr));
571 if (likely(txq->mp2mr[i].start <= addr && txq->mp2mr[i].end >= addr))
572 return txq->mp2mr[i].lkey;
573 for (i = 0; (i != RTE_DIM(txq->mp2mr)); ++i) {
574 if (unlikely(txq->mp2mr[i].mr == NULL)) {
575 /* Unknown MP, add a new MR for it. */
578 if (txq->mp2mr[i].start <= addr &&
579 txq->mp2mr[i].end >= addr) {
580 assert(txq->mp2mr[i].lkey != (uint32_t)-1);
581 assert(htonl(txq->mp2mr[i].mr->lkey) ==
583 txq->mr_cache_idx = i;
584 return txq->mp2mr[i].lkey;
587 txq->mr_cache_idx = 0;
588 return txq_mp2mr_reg(txq, mlx5_tx_mb2mp(mb), i);
592 * Ring TX queue doorbell.
595 * Pointer to TX queue structure.
597 * Pointer to the last WQE posted in the NIC.
599 static __rte_always_inline void
600 mlx5_tx_dbrec(struct txq *txq, volatile struct mlx5_wqe *wqe)
602 uint64_t *dst = (uint64_t *)((uintptr_t)txq->bf_reg);
603 volatile uint64_t *src = ((volatile uint64_t *)wqe);
606 *txq->qp_db = htonl(txq->wqe_ci);
607 /* Ensure ordering between DB record and BF copy. */
612 #endif /* RTE_PMD_MLX5_RXTX_H_ */