1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018-2021 Beijing WangXun Technology Co., Ltd.
3 * Copyright(c) 2010-2017 Intel Corporation
7 #include <rte_common.h>
8 #include <ethdev_pci.h>
10 #include <rte_alarm.h>
12 #include "ngbe_logs.h"
14 #include "ngbe_ethdev.h"
15 #include "ngbe_rxtx.h"
17 static int ngbe_dev_close(struct rte_eth_dev *dev);
18 static int ngbe_dev_link_update(struct rte_eth_dev *dev,
19 int wait_to_complete);
21 static void ngbe_dev_link_status_print(struct rte_eth_dev *dev);
22 static int ngbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
23 static int ngbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
24 static int ngbe_dev_misc_interrupt_setup(struct rte_eth_dev *dev);
25 static int ngbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
26 static void ngbe_dev_interrupt_handler(void *param);
27 static void ngbe_dev_interrupt_delayed_handler(void *param);
28 static void ngbe_configure_msix(struct rte_eth_dev *dev);
31 * The set of PCI devices this driver supports
33 static const struct rte_pci_id pci_id_ngbe_map[] = {
34 { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, NGBE_DEV_ID_EM_WX1860A2) },
35 { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, NGBE_DEV_ID_EM_WX1860A2S) },
36 { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, NGBE_DEV_ID_EM_WX1860A4) },
37 { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, NGBE_DEV_ID_EM_WX1860A4S) },
38 { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, NGBE_DEV_ID_EM_WX1860AL2) },
39 { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, NGBE_DEV_ID_EM_WX1860AL2S) },
40 { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, NGBE_DEV_ID_EM_WX1860AL4) },
41 { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, NGBE_DEV_ID_EM_WX1860AL4S) },
42 { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, NGBE_DEV_ID_EM_WX1860NCSI) },
43 { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, NGBE_DEV_ID_EM_WX1860A1) },
44 { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, NGBE_DEV_ID_EM_WX1860A1L) },
45 { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, NGBE_DEV_ID_EM_WX1860AL_W) },
46 { .vendor_id = 0, /* sentinel */ },
49 static const struct rte_eth_desc_lim rx_desc_lim = {
50 .nb_max = NGBE_RING_DESC_MAX,
51 .nb_min = NGBE_RING_DESC_MIN,
52 .nb_align = NGBE_RXD_ALIGN,
55 static const struct rte_eth_desc_lim tx_desc_lim = {
56 .nb_max = NGBE_RING_DESC_MAX,
57 .nb_min = NGBE_RING_DESC_MIN,
58 .nb_align = NGBE_TXD_ALIGN,
59 .nb_seg_max = NGBE_TX_MAX_SEG,
60 .nb_mtu_seg_max = NGBE_TX_MAX_SEG,
63 static const struct eth_dev_ops ngbe_eth_dev_ops;
66 ngbe_pf_reset_hw(struct ngbe_hw *hw)
71 status = hw->mac.reset_hw(hw);
73 ctrl_ext = rd32(hw, NGBE_PORTCTL);
74 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
75 ctrl_ext |= NGBE_PORTCTL_RSTDONE;
76 wr32(hw, NGBE_PORTCTL, ctrl_ext);
79 if (status == NGBE_ERR_SFP_NOT_PRESENT)
85 ngbe_enable_intr(struct rte_eth_dev *dev)
87 struct ngbe_interrupt *intr = ngbe_dev_intr(dev);
88 struct ngbe_hw *hw = ngbe_dev_hw(dev);
90 wr32(hw, NGBE_IENMISC, intr->mask_misc);
91 wr32(hw, NGBE_IMC(0), intr->mask & BIT_MASK32);
96 ngbe_disable_intr(struct ngbe_hw *hw)
98 PMD_INIT_FUNC_TRACE();
100 wr32(hw, NGBE_IMS(0), NGBE_IMS_MASK);
105 * Ensure that all locks are released before first NVM or PHY access
108 ngbe_swfw_lock_reset(struct ngbe_hw *hw)
113 * These ones are more tricky since they are common to all ports; but
114 * swfw_sync retries last long enough (1s) to be almost sure that if
115 * lock can not be taken it is due to an improper lock of the
118 mask = NGBE_MNGSEM_SWPHY |
121 if (hw->mac.acquire_swfw_sync(hw, mask) < 0)
122 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
124 hw->mac.release_swfw_sync(hw, mask);
128 eth_ngbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused)
130 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
131 struct ngbe_hw *hw = ngbe_dev_hw(eth_dev);
132 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
133 const struct rte_memzone *mz;
137 PMD_INIT_FUNC_TRACE();
139 eth_dev->dev_ops = &ngbe_eth_dev_ops;
140 eth_dev->rx_pkt_burst = &ngbe_recv_pkts;
141 eth_dev->tx_pkt_burst = &ngbe_xmit_pkts_simple;
143 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
146 rte_eth_copy_pci_info(eth_dev, pci_dev);
148 /* Vendor and Device ID need to be set before init of shared code */
149 hw->device_id = pci_dev->id.device_id;
150 hw->vendor_id = pci_dev->id.vendor_id;
151 hw->sub_system_id = pci_dev->id.subsystem_device_id;
152 ngbe_map_device_id(hw);
153 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
155 /* Reserve memory for interrupt status block */
156 mz = rte_eth_dma_zone_reserve(eth_dev, "ngbe_driver", -1,
157 NGBE_ISB_SIZE, NGBE_ALIGN, SOCKET_ID_ANY);
161 hw->isb_dma = TMZ_PADDR(mz);
162 hw->isb_mem = TMZ_VADDR(mz);
164 /* Initialize the shared code (base driver) */
165 err = ngbe_init_shared_code(hw);
167 PMD_INIT_LOG(ERR, "Shared code init failed: %d", err);
171 /* Unlock any pending hardware semaphore */
172 ngbe_swfw_lock_reset(hw);
174 err = hw->rom.init_params(hw);
176 PMD_INIT_LOG(ERR, "The EEPROM init failed: %d", err);
180 /* Make sure we have a good EEPROM before we read from it */
181 err = hw->rom.validate_checksum(hw, NULL);
183 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", err);
187 err = hw->mac.init_hw(hw);
189 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", err);
193 /* disable interrupt */
194 ngbe_disable_intr(hw);
196 /* Allocate memory for storing MAC addresses */
197 eth_dev->data->mac_addrs = rte_zmalloc("ngbe", RTE_ETHER_ADDR_LEN *
198 hw->mac.num_rar_entries, 0);
199 if (eth_dev->data->mac_addrs == NULL) {
201 "Failed to allocate %u bytes needed to store MAC addresses",
202 RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries);
206 /* Copy the permanent MAC address */
207 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
208 ð_dev->data->mac_addrs[0]);
210 /* Allocate memory for storing hash filter MAC addresses */
211 eth_dev->data->hash_mac_addrs = rte_zmalloc("ngbe",
212 RTE_ETHER_ADDR_LEN * NGBE_VMDQ_NUM_UC_MAC, 0);
213 if (eth_dev->data->hash_mac_addrs == NULL) {
215 "Failed to allocate %d bytes needed to store MAC addresses",
216 RTE_ETHER_ADDR_LEN * NGBE_VMDQ_NUM_UC_MAC);
217 rte_free(eth_dev->data->mac_addrs);
218 eth_dev->data->mac_addrs = NULL;
222 ctrl_ext = rd32(hw, NGBE_PORTCTL);
223 /* let hardware know driver is loaded */
224 ctrl_ext |= NGBE_PORTCTL_DRVLOAD;
225 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
226 ctrl_ext |= NGBE_PORTCTL_RSTDONE;
227 wr32(hw, NGBE_PORTCTL, ctrl_ext);
230 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
231 (int)hw->mac.type, (int)hw->phy.type);
233 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
234 eth_dev->data->port_id, pci_dev->id.vendor_id,
235 pci_dev->id.device_id);
237 rte_intr_callback_register(intr_handle,
238 ngbe_dev_interrupt_handler, eth_dev);
240 /* enable uio/vfio intr/eventfd mapping */
241 rte_intr_enable(intr_handle);
243 /* enable support intr */
244 ngbe_enable_intr(eth_dev);
250 eth_ngbe_dev_uninit(struct rte_eth_dev *eth_dev)
252 PMD_INIT_FUNC_TRACE();
254 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
257 ngbe_dev_close(eth_dev);
263 eth_ngbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
264 struct rte_pci_device *pci_dev)
266 return rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
267 sizeof(struct ngbe_adapter),
268 eth_dev_pci_specific_init, pci_dev,
269 eth_ngbe_dev_init, NULL);
272 static int eth_ngbe_pci_remove(struct rte_pci_device *pci_dev)
274 struct rte_eth_dev *ethdev;
276 ethdev = rte_eth_dev_allocated(pci_dev->device.name);
280 return rte_eth_dev_destroy(ethdev, eth_ngbe_dev_uninit);
283 static struct rte_pci_driver rte_ngbe_pmd = {
284 .id_table = pci_id_ngbe_map,
285 .drv_flags = RTE_PCI_DRV_NEED_MAPPING |
286 RTE_PCI_DRV_INTR_LSC,
287 .probe = eth_ngbe_pci_probe,
288 .remove = eth_ngbe_pci_remove,
292 ngbe_dev_configure(struct rte_eth_dev *dev)
294 struct ngbe_interrupt *intr = ngbe_dev_intr(dev);
295 struct ngbe_adapter *adapter = ngbe_dev_adapter(dev);
297 PMD_INIT_FUNC_TRACE();
299 /* set flag to update link status after init */
300 intr->flags |= NGBE_FLAG_NEED_LINK_UPDATE;
303 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
304 * allocation Rx preconditions we will reset it.
306 adapter->rx_bulk_alloc_allowed = true;
312 ngbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
314 struct ngbe_hw *hw = ngbe_dev_hw(dev);
315 struct ngbe_interrupt *intr = ngbe_dev_intr(dev);
317 wr32(hw, NGBE_GPIODIR, NGBE_GPIODIR_DDR(1));
318 wr32(hw, NGBE_GPIOINTEN, NGBE_GPIOINTEN_INT(3));
319 wr32(hw, NGBE_GPIOINTTYPE, NGBE_GPIOINTTYPE_LEVEL(0));
320 if (hw->phy.type == ngbe_phy_yt8521s_sfi)
321 wr32(hw, NGBE_GPIOINTPOL, NGBE_GPIOINTPOL_ACT(0));
323 wr32(hw, NGBE_GPIOINTPOL, NGBE_GPIOINTPOL_ACT(3));
325 intr->mask_misc |= NGBE_ICRMISC_GPIO;
329 * Configure device link speed and setup link.
330 * It returns 0 on success.
333 ngbe_dev_start(struct rte_eth_dev *dev)
335 struct ngbe_hw *hw = ngbe_dev_hw(dev);
336 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
337 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
338 uint32_t intr_vector = 0;
340 bool link_up = false, negotiate = false;
342 uint32_t allowed_speeds = 0;
344 uint32_t *link_speeds;
346 PMD_INIT_FUNC_TRACE();
348 /* disable uio/vfio intr/eventfd mapping */
349 rte_intr_disable(intr_handle);
352 hw->adapter_stopped = 0;
355 /* reinitialize adapter, this calls reset and start */
356 hw->nb_rx_queues = dev->data->nb_rx_queues;
357 hw->nb_tx_queues = dev->data->nb_tx_queues;
358 status = ngbe_pf_reset_hw(hw);
361 hw->mac.start_hw(hw);
362 hw->mac.get_link_status = true;
364 ngbe_dev_phy_intr_setup(dev);
366 /* check and configure queue intr-vector mapping */
367 if ((rte_intr_cap_multiple(intr_handle) ||
368 !RTE_ETH_DEV_SRIOV(dev).active) &&
369 dev->data->dev_conf.intr_conf.rxq != 0) {
370 intr_vector = dev->data->nb_rx_queues;
371 if (rte_intr_efd_enable(intr_handle, intr_vector))
375 if (rte_intr_dp_is_en(intr_handle) && intr_handle->intr_vec == NULL) {
376 intr_handle->intr_vec =
377 rte_zmalloc("intr_vec",
378 dev->data->nb_rx_queues * sizeof(int), 0);
379 if (intr_handle->intr_vec == NULL) {
381 "Failed to allocate %d rx_queues intr_vec",
382 dev->data->nb_rx_queues);
387 /* confiugre MSI-X for sleep until Rx interrupt */
388 ngbe_configure_msix(dev);
390 /* initialize transmission unit */
391 ngbe_dev_tx_init(dev);
393 /* This can fail when allocating mbufs for descriptor rings */
394 err = ngbe_dev_rx_init(dev);
396 PMD_INIT_LOG(ERR, "Unable to initialize Rx hardware");
400 err = ngbe_dev_rxtx_start(dev);
402 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
406 err = hw->mac.check_link(hw, &speed, &link_up, 0);
409 dev->data->dev_link.link_status = link_up;
411 link_speeds = &dev->data->dev_conf.link_speeds;
412 if (*link_speeds == ETH_LINK_SPEED_AUTONEG)
415 err = hw->mac.get_link_capabilities(hw, &speed, &negotiate);
420 if (hw->mac.default_speeds & NGBE_LINK_SPEED_1GB_FULL)
421 allowed_speeds |= ETH_LINK_SPEED_1G;
422 if (hw->mac.default_speeds & NGBE_LINK_SPEED_100M_FULL)
423 allowed_speeds |= ETH_LINK_SPEED_100M;
424 if (hw->mac.default_speeds & NGBE_LINK_SPEED_10M_FULL)
425 allowed_speeds |= ETH_LINK_SPEED_10M;
427 if (*link_speeds & ~allowed_speeds) {
428 PMD_INIT_LOG(ERR, "Invalid link setting");
433 if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
434 speed = hw->mac.default_speeds;
436 if (*link_speeds & ETH_LINK_SPEED_1G)
437 speed |= NGBE_LINK_SPEED_1GB_FULL;
438 if (*link_speeds & ETH_LINK_SPEED_100M)
439 speed |= NGBE_LINK_SPEED_100M_FULL;
440 if (*link_speeds & ETH_LINK_SPEED_10M)
441 speed |= NGBE_LINK_SPEED_10M_FULL;
445 err = hw->mac.setup_link(hw, speed, link_up);
449 if (rte_intr_allow_others(intr_handle)) {
450 ngbe_dev_misc_interrupt_setup(dev);
451 /* check if lsc interrupt is enabled */
452 if (dev->data->dev_conf.intr_conf.lsc != 0)
453 ngbe_dev_lsc_interrupt_setup(dev, TRUE);
455 ngbe_dev_lsc_interrupt_setup(dev, FALSE);
456 ngbe_dev_macsec_interrupt_setup(dev);
457 ngbe_set_ivar_map(hw, -1, 1, NGBE_MISC_VEC_ID);
459 rte_intr_callback_unregister(intr_handle,
460 ngbe_dev_interrupt_handler, dev);
461 if (dev->data->dev_conf.intr_conf.lsc != 0)
463 "LSC won't enable because of no intr multiplex");
466 /* check if rxq interrupt is enabled */
467 if (dev->data->dev_conf.intr_conf.rxq != 0 &&
468 rte_intr_dp_is_en(intr_handle))
469 ngbe_dev_rxq_interrupt_setup(dev);
471 /* enable UIO/VFIO intr/eventfd mapping */
472 rte_intr_enable(intr_handle);
474 /* resume enabled intr since HW reset */
475 ngbe_enable_intr(dev);
477 if ((hw->sub_system_id & NGBE_OEM_MASK) == NGBE_LY_M88E1512_SFP ||
478 (hw->sub_system_id & NGBE_OEM_MASK) == NGBE_LY_YT8521S_SFP) {
479 /* gpio0 is used to power on/off control*/
480 wr32(hw, NGBE_GPIODATA, 0);
484 * Update link status right before return, because it may
485 * start link configuration process in a separate thread.
487 ngbe_dev_link_update(dev, 0);
492 PMD_INIT_LOG(ERR, "failure in dev start: %d", err);
493 ngbe_dev_clear_queues(dev);
498 * Stop device: disable rx and tx functions to allow for reconfiguring.
501 ngbe_dev_stop(struct rte_eth_dev *dev)
503 struct rte_eth_link link;
504 struct ngbe_hw *hw = ngbe_dev_hw(dev);
505 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
506 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
508 if (hw->adapter_stopped)
511 PMD_INIT_FUNC_TRACE();
513 if ((hw->sub_system_id & NGBE_OEM_MASK) == NGBE_LY_M88E1512_SFP ||
514 (hw->sub_system_id & NGBE_OEM_MASK) == NGBE_LY_YT8521S_SFP) {
515 /* gpio0 is used to power on/off control*/
516 wr32(hw, NGBE_GPIODATA, NGBE_GPIOBIT_0);
519 /* disable interrupts */
520 ngbe_disable_intr(hw);
523 ngbe_pf_reset_hw(hw);
524 hw->adapter_stopped = 0;
529 ngbe_dev_clear_queues(dev);
531 /* Clear recorded link status */
532 memset(&link, 0, sizeof(link));
533 rte_eth_linkstatus_set(dev, &link);
535 if (!rte_intr_allow_others(intr_handle))
536 /* resume to the default handler */
537 rte_intr_callback_register(intr_handle,
538 ngbe_dev_interrupt_handler,
541 /* Clean datapath event and queue/vec mapping */
542 rte_intr_efd_disable(intr_handle);
543 if (intr_handle->intr_vec != NULL) {
544 rte_free(intr_handle->intr_vec);
545 intr_handle->intr_vec = NULL;
548 hw->adapter_stopped = true;
549 dev->data->dev_started = 0;
555 * Reset and stop device.
558 ngbe_dev_close(struct rte_eth_dev *dev)
560 struct ngbe_hw *hw = ngbe_dev_hw(dev);
561 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
562 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
566 PMD_INIT_FUNC_TRACE();
568 ngbe_pf_reset_hw(hw);
572 ngbe_dev_free_queues(dev);
574 /* reprogram the RAR[0] in case user changed it. */
575 ngbe_set_rar(hw, 0, hw->mac.addr, 0, true);
577 /* Unlock any pending hardware semaphore */
578 ngbe_swfw_lock_reset(hw);
580 /* disable uio intr before callback unregister */
581 rte_intr_disable(intr_handle);
584 ret = rte_intr_callback_unregister(intr_handle,
585 ngbe_dev_interrupt_handler, dev);
586 if (ret >= 0 || ret == -ENOENT) {
588 } else if (ret != -EAGAIN) {
590 "intr callback unregister failed: %d",
594 } while (retries++ < (10 + NGBE_LINK_UP_TIME));
596 rte_free(dev->data->mac_addrs);
597 dev->data->mac_addrs = NULL;
599 rte_free(dev->data->hash_mac_addrs);
600 dev->data->hash_mac_addrs = NULL;
609 ngbe_dev_reset(struct rte_eth_dev *dev)
613 ret = eth_ngbe_dev_uninit(dev);
617 ret = eth_ngbe_dev_init(dev, NULL);
623 ngbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
625 struct ngbe_hw *hw = ngbe_dev_hw(dev);
627 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
628 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
629 dev_info->min_rx_bufsize = 1024;
630 dev_info->max_rx_pktlen = 15872;
632 dev_info->default_rxconf = (struct rte_eth_rxconf) {
634 .pthresh = NGBE_DEFAULT_RX_PTHRESH,
635 .hthresh = NGBE_DEFAULT_RX_HTHRESH,
636 .wthresh = NGBE_DEFAULT_RX_WTHRESH,
638 .rx_free_thresh = NGBE_DEFAULT_RX_FREE_THRESH,
643 dev_info->default_txconf = (struct rte_eth_txconf) {
645 .pthresh = NGBE_DEFAULT_TX_PTHRESH,
646 .hthresh = NGBE_DEFAULT_TX_HTHRESH,
647 .wthresh = NGBE_DEFAULT_TX_WTHRESH,
649 .tx_free_thresh = NGBE_DEFAULT_TX_FREE_THRESH,
653 dev_info->rx_desc_lim = rx_desc_lim;
654 dev_info->tx_desc_lim = tx_desc_lim;
656 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_100M |
659 /* Driver-preferred Rx/Tx parameters */
660 dev_info->default_rxportconf.burst_size = 32;
661 dev_info->default_txportconf.burst_size = 32;
662 dev_info->default_rxportconf.nb_queues = 1;
663 dev_info->default_txportconf.nb_queues = 1;
664 dev_info->default_rxportconf.ring_size = 256;
665 dev_info->default_txportconf.ring_size = 256;
670 /* return 0 means link status changed, -1 means not changed */
672 ngbe_dev_link_update_share(struct rte_eth_dev *dev,
673 int wait_to_complete)
675 struct ngbe_hw *hw = ngbe_dev_hw(dev);
676 struct rte_eth_link link;
677 u32 link_speed = NGBE_LINK_SPEED_UNKNOWN;
679 struct ngbe_interrupt *intr = ngbe_dev_intr(dev);
684 memset(&link, 0, sizeof(link));
685 link.link_status = ETH_LINK_DOWN;
686 link.link_speed = ETH_SPEED_NUM_NONE;
687 link.link_duplex = ETH_LINK_HALF_DUPLEX;
688 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
689 ~ETH_LINK_SPEED_AUTONEG);
691 hw->mac.get_link_status = true;
693 if (intr->flags & NGBE_FLAG_NEED_LINK_CONFIG)
694 return rte_eth_linkstatus_set(dev, &link);
696 /* check if it needs to wait to complete, if lsc interrupt is enabled */
697 if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
700 err = hw->mac.check_link(hw, &link_speed, &link_up, wait);
702 link.link_speed = ETH_SPEED_NUM_NONE;
703 link.link_duplex = ETH_LINK_FULL_DUPLEX;
704 return rte_eth_linkstatus_set(dev, &link);
708 return rte_eth_linkstatus_set(dev, &link);
710 intr->flags &= ~NGBE_FLAG_NEED_LINK_CONFIG;
711 link.link_status = ETH_LINK_UP;
712 link.link_duplex = ETH_LINK_FULL_DUPLEX;
714 switch (link_speed) {
716 case NGBE_LINK_SPEED_UNKNOWN:
717 link.link_speed = ETH_SPEED_NUM_NONE;
720 case NGBE_LINK_SPEED_10M_FULL:
721 link.link_speed = ETH_SPEED_NUM_10M;
725 case NGBE_LINK_SPEED_100M_FULL:
726 link.link_speed = ETH_SPEED_NUM_100M;
730 case NGBE_LINK_SPEED_1GB_FULL:
731 link.link_speed = ETH_SPEED_NUM_1G;
737 wr32m(hw, NGBE_LAN_SPEED, NGBE_LAN_SPEED_MASK, lan_speed);
738 if (link_speed & (NGBE_LINK_SPEED_1GB_FULL |
739 NGBE_LINK_SPEED_100M_FULL |
740 NGBE_LINK_SPEED_10M_FULL)) {
741 wr32m(hw, NGBE_MACTXCFG, NGBE_MACTXCFG_SPEED_MASK,
742 NGBE_MACTXCFG_SPEED_1G | NGBE_MACTXCFG_TE);
746 return rte_eth_linkstatus_set(dev, &link);
750 ngbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
752 return ngbe_dev_link_update_share(dev, wait_to_complete);
756 * It clears the interrupt causes and enables the interrupt.
757 * It will be called once only during NIC initialized.
760 * Pointer to struct rte_eth_dev.
765 * - On success, zero.
766 * - On failure, a negative value.
769 ngbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
771 struct ngbe_interrupt *intr = ngbe_dev_intr(dev);
773 ngbe_dev_link_status_print(dev);
775 intr->mask_misc |= NGBE_ICRMISC_PHY;
776 intr->mask_misc |= NGBE_ICRMISC_GPIO;
778 intr->mask_misc &= ~NGBE_ICRMISC_PHY;
779 intr->mask_misc &= ~NGBE_ICRMISC_GPIO;
786 * It clears the interrupt causes and enables the interrupt.
787 * It will be called once only during NIC initialized.
790 * Pointer to struct rte_eth_dev.
793 * - On success, zero.
794 * - On failure, a negative value.
797 ngbe_dev_misc_interrupt_setup(struct rte_eth_dev *dev)
799 struct ngbe_interrupt *intr = ngbe_dev_intr(dev);
802 mask = NGBE_ICR_MASK;
803 mask &= (1ULL << NGBE_MISC_VEC_ID);
805 intr->mask_misc |= NGBE_ICRMISC_GPIO;
811 * It clears the interrupt causes and enables the interrupt.
812 * It will be called once only during NIC initialized.
815 * Pointer to struct rte_eth_dev.
818 * - On success, zero.
819 * - On failure, a negative value.
822 ngbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
824 struct ngbe_interrupt *intr = ngbe_dev_intr(dev);
827 mask = NGBE_ICR_MASK;
828 mask &= ~((1ULL << NGBE_RX_VEC_START) - 1);
835 * It clears the interrupt causes and enables the interrupt.
836 * It will be called once only during NIC initialized.
839 * Pointer to struct rte_eth_dev.
842 * - On success, zero.
843 * - On failure, a negative value.
846 ngbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
848 struct ngbe_interrupt *intr = ngbe_dev_intr(dev);
850 intr->mask_misc |= NGBE_ICRMISC_LNKSEC;
856 * It reads ICR and sets flag for the link_update.
859 * Pointer to struct rte_eth_dev.
862 * - On success, zero.
863 * - On failure, a negative value.
866 ngbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
869 struct ngbe_hw *hw = ngbe_dev_hw(dev);
870 struct ngbe_interrupt *intr = ngbe_dev_intr(dev);
872 /* clear all cause mask */
873 ngbe_disable_intr(hw);
875 /* read-on-clear nic registers here */
876 eicr = ((u32 *)hw->isb_mem)[NGBE_ISB_MISC];
877 PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
881 /* set flag for async link update */
882 if (eicr & NGBE_ICRMISC_PHY)
883 intr->flags |= NGBE_FLAG_NEED_LINK_UPDATE;
885 if (eicr & NGBE_ICRMISC_VFMBX)
886 intr->flags |= NGBE_FLAG_MAILBOX;
888 if (eicr & NGBE_ICRMISC_LNKSEC)
889 intr->flags |= NGBE_FLAG_MACSEC;
891 if (eicr & NGBE_ICRMISC_GPIO)
892 intr->flags |= NGBE_FLAG_NEED_LINK_UPDATE;
898 * It gets and then prints the link status.
901 * Pointer to struct rte_eth_dev.
904 * - On success, zero.
905 * - On failure, a negative value.
908 ngbe_dev_link_status_print(struct rte_eth_dev *dev)
910 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
911 struct rte_eth_link link;
913 rte_eth_linkstatus_get(dev, &link);
915 if (link.link_status == ETH_LINK_UP) {
916 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
917 (int)(dev->data->port_id),
918 (unsigned int)link.link_speed,
919 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
920 "full-duplex" : "half-duplex");
922 PMD_INIT_LOG(INFO, " Port %d: Link Down",
923 (int)(dev->data->port_id));
925 PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
926 pci_dev->addr.domain,
929 pci_dev->addr.function);
933 * It executes link_update after knowing an interrupt occurred.
936 * Pointer to struct rte_eth_dev.
939 * - On success, zero.
940 * - On failure, a negative value.
943 ngbe_dev_interrupt_action(struct rte_eth_dev *dev)
945 struct ngbe_interrupt *intr = ngbe_dev_intr(dev);
948 PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
950 if (intr->flags & NGBE_FLAG_NEED_LINK_UPDATE) {
951 struct rte_eth_link link;
953 /*get the link status before link update, for predicting later*/
954 rte_eth_linkstatus_get(dev, &link);
956 ngbe_dev_link_update(dev, 0);
959 if (link.link_status != ETH_LINK_UP)
960 /* handle it 1 sec later, wait it being stable */
961 timeout = NGBE_LINK_UP_CHECK_TIMEOUT;
964 /* handle it 4 sec later, wait it being stable */
965 timeout = NGBE_LINK_DOWN_CHECK_TIMEOUT;
967 ngbe_dev_link_status_print(dev);
968 if (rte_eal_alarm_set(timeout * 1000,
969 ngbe_dev_interrupt_delayed_handler,
971 PMD_DRV_LOG(ERR, "Error setting alarm");
973 /* remember original mask */
974 intr->mask_misc_orig = intr->mask_misc;
975 /* only disable lsc interrupt */
976 intr->mask_misc &= ~NGBE_ICRMISC_PHY;
978 intr->mask_orig = intr->mask;
979 /* only disable all misc interrupts */
980 intr->mask &= ~(1ULL << NGBE_MISC_VEC_ID);
984 PMD_DRV_LOG(DEBUG, "enable intr immediately");
985 ngbe_enable_intr(dev);
991 * Interrupt handler which shall be registered for alarm callback for delayed
992 * handling specific interrupt to wait for the stable nic state. As the
993 * NIC interrupt state is not stable for ngbe after link is just down,
994 * it needs to wait 4 seconds to get the stable status.
997 * The address of parameter (struct rte_eth_dev *) registered before.
1000 ngbe_dev_interrupt_delayed_handler(void *param)
1002 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1003 struct ngbe_interrupt *intr = ngbe_dev_intr(dev);
1004 struct ngbe_hw *hw = ngbe_dev_hw(dev);
1007 ngbe_disable_intr(hw);
1009 eicr = ((u32 *)hw->isb_mem)[NGBE_ISB_MISC];
1011 if (intr->flags & NGBE_FLAG_NEED_LINK_UPDATE) {
1012 ngbe_dev_link_update(dev, 0);
1013 intr->flags &= ~NGBE_FLAG_NEED_LINK_UPDATE;
1014 ngbe_dev_link_status_print(dev);
1015 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
1019 if (intr->flags & NGBE_FLAG_MACSEC) {
1020 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
1022 intr->flags &= ~NGBE_FLAG_MACSEC;
1025 /* restore original mask */
1026 intr->mask_misc = intr->mask_misc_orig;
1027 intr->mask_misc_orig = 0;
1028 intr->mask = intr->mask_orig;
1029 intr->mask_orig = 0;
1031 PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
1032 ngbe_enable_intr(dev);
1036 * Interrupt handler triggered by NIC for handling
1037 * specific interrupt.
1040 * The address of parameter (struct rte_eth_dev *) registered before.
1043 ngbe_dev_interrupt_handler(void *param)
1045 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1047 ngbe_dev_interrupt_get_status(dev);
1048 ngbe_dev_interrupt_action(dev);
1052 * Set the IVAR registers, mapping interrupt causes to vectors
1054 * pointer to ngbe_hw struct
1056 * 0 for Rx, 1 for Tx, -1 for other causes
1058 * queue to map the corresponding interrupt to
1060 * the vector to map to the corresponding queue
1063 ngbe_set_ivar_map(struct ngbe_hw *hw, int8_t direction,
1064 uint8_t queue, uint8_t msix_vector)
1068 if (direction == -1) {
1070 msix_vector |= NGBE_IVARMISC_VLD;
1072 tmp = rd32(hw, NGBE_IVARMISC);
1073 tmp &= ~(0xFF << idx);
1074 tmp |= (msix_vector << idx);
1075 wr32(hw, NGBE_IVARMISC, tmp);
1077 /* rx or tx causes */
1078 /* Workround for ICR lost */
1079 idx = ((16 * (queue & 1)) + (8 * direction));
1080 tmp = rd32(hw, NGBE_IVAR(queue >> 1));
1081 tmp &= ~(0xFF << idx);
1082 tmp |= (msix_vector << idx);
1083 wr32(hw, NGBE_IVAR(queue >> 1), tmp);
1088 * Sets up the hardware to properly generate MSI-X interrupts
1090 * board private structure
1093 ngbe_configure_msix(struct rte_eth_dev *dev)
1095 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1096 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1097 struct ngbe_hw *hw = ngbe_dev_hw(dev);
1098 uint32_t queue_id, base = NGBE_MISC_VEC_ID;
1099 uint32_t vec = NGBE_MISC_VEC_ID;
1103 * Won't configure MSI-X register if no mapping is done
1104 * between intr vector and event fd
1105 * but if MSI-X has been enabled already, need to configure
1106 * auto clean, auto mask and throttling.
1108 gpie = rd32(hw, NGBE_GPIE);
1109 if (!rte_intr_dp_is_en(intr_handle) &&
1110 !(gpie & NGBE_GPIE_MSIX))
1113 if (rte_intr_allow_others(intr_handle)) {
1114 base = NGBE_RX_VEC_START;
1118 /* setup GPIE for MSI-X mode */
1119 gpie = rd32(hw, NGBE_GPIE);
1120 gpie |= NGBE_GPIE_MSIX;
1121 wr32(hw, NGBE_GPIE, gpie);
1123 /* Populate the IVAR table and set the ITR values to the
1124 * corresponding register.
1126 if (rte_intr_dp_is_en(intr_handle)) {
1127 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
1129 /* by default, 1:1 mapping */
1130 ngbe_set_ivar_map(hw, 0, queue_id, vec);
1131 intr_handle->intr_vec[queue_id] = vec;
1132 if (vec < base + intr_handle->nb_efd - 1)
1136 ngbe_set_ivar_map(hw, -1, 1, NGBE_MISC_VEC_ID);
1138 wr32(hw, NGBE_ITR(NGBE_MISC_VEC_ID),
1139 NGBE_ITR_IVAL_1G(NGBE_QUEUE_ITR_INTERVAL_DEFAULT)
1143 static const struct eth_dev_ops ngbe_eth_dev_ops = {
1144 .dev_configure = ngbe_dev_configure,
1145 .dev_infos_get = ngbe_dev_info_get,
1146 .dev_start = ngbe_dev_start,
1147 .dev_stop = ngbe_dev_stop,
1148 .dev_close = ngbe_dev_close,
1149 .dev_reset = ngbe_dev_reset,
1150 .link_update = ngbe_dev_link_update,
1151 .rx_queue_start = ngbe_dev_rx_queue_start,
1152 .rx_queue_stop = ngbe_dev_rx_queue_stop,
1153 .tx_queue_start = ngbe_dev_tx_queue_start,
1154 .tx_queue_stop = ngbe_dev_tx_queue_stop,
1155 .rx_queue_setup = ngbe_dev_rx_queue_setup,
1156 .rx_queue_release = ngbe_dev_rx_queue_release,
1157 .tx_queue_setup = ngbe_dev_tx_queue_setup,
1158 .tx_queue_release = ngbe_dev_tx_queue_release,
1161 RTE_PMD_REGISTER_PCI(net_ngbe, rte_ngbe_pmd);
1162 RTE_PMD_REGISTER_PCI_TABLE(net_ngbe, pci_id_ngbe_map);
1163 RTE_PMD_REGISTER_KMOD_DEP(net_ngbe, "* igb_uio | uio_pci_generic | vfio-pci");
1165 RTE_LOG_REGISTER_SUFFIX(ngbe_logtype_init, init, NOTICE);
1166 RTE_LOG_REGISTER_SUFFIX(ngbe_logtype_driver, driver, NOTICE);
1168 #ifdef RTE_ETHDEV_DEBUG_RX
1169 RTE_LOG_REGISTER_SUFFIX(ngbe_logtype_rx, rx, DEBUG);
1171 #ifdef RTE_ETHDEV_DEBUG_TX
1172 RTE_LOG_REGISTER_SUFFIX(ngbe_logtype_tx, tx, DEBUG);