1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2019 Marvell International Ltd.
5 #ifndef __OTX2_TIM_EVDEV_H__
6 #define __OTX2_TIM_EVDEV_H__
8 #include <rte_event_timer_adapter.h>
9 #include <rte_event_timer_adapter_pmd.h>
10 #include <rte_reciprocal.h>
14 #define OTX2_TIM_EVDEV_NAME otx2_tim_eventdev
16 #define otx2_tim_func_trace otx2_tim_dbg
18 #define TIM_LF_RING_AURA (0x0)
19 #define TIM_LF_RING_BASE (0x130)
20 #define TIM_LF_NRSPERR_INT (0x200)
21 #define TIM_LF_NRSPERR_INT_W1S (0x208)
22 #define TIM_LF_NRSPERR_INT_ENA_W1S (0x210)
23 #define TIM_LF_NRSPERR_INT_ENA_W1C (0x218)
24 #define TIM_LF_RAS_INT (0x300)
25 #define TIM_LF_RAS_INT_W1S (0x308)
26 #define TIM_LF_RAS_INT_ENA_W1S (0x310)
27 #define TIM_LF_RAS_INT_ENA_W1C (0x318)
28 #define TIM_LF_RING_REL (0x400)
30 #define TIM_BUCKET_W1_S_CHUNK_REMAINDER (48)
31 #define TIM_BUCKET_W1_M_CHUNK_REMAINDER ((1ULL << (64 - \
32 TIM_BUCKET_W1_S_CHUNK_REMAINDER)) - 1)
33 #define TIM_BUCKET_W1_S_LOCK (40)
34 #define TIM_BUCKET_W1_M_LOCK ((1ULL << \
35 (TIM_BUCKET_W1_S_CHUNK_REMAINDER - \
36 TIM_BUCKET_W1_S_LOCK)) - 1)
37 #define TIM_BUCKET_W1_S_RSVD (35)
38 #define TIM_BUCKET_W1_S_BSK (34)
39 #define TIM_BUCKET_W1_M_BSK ((1ULL << \
40 (TIM_BUCKET_W1_S_RSVD - \
41 TIM_BUCKET_W1_S_BSK)) - 1)
42 #define TIM_BUCKET_W1_S_HBT (33)
43 #define TIM_BUCKET_W1_M_HBT ((1ULL << \
44 (TIM_BUCKET_W1_S_BSK - \
45 TIM_BUCKET_W1_S_HBT)) - 1)
46 #define TIM_BUCKET_W1_S_SBT (32)
47 #define TIM_BUCKET_W1_M_SBT ((1ULL << \
48 (TIM_BUCKET_W1_S_HBT - \
49 TIM_BUCKET_W1_S_SBT)) - 1)
50 #define TIM_BUCKET_W1_S_NUM_ENTRIES (0)
51 #define TIM_BUCKET_W1_M_NUM_ENTRIES ((1ULL << \
52 (TIM_BUCKET_W1_S_SBT - \
53 TIM_BUCKET_W1_S_NUM_ENTRIES)) - 1)
55 #define TIM_BUCKET_SEMA (TIM_BUCKET_CHUNK_REMAIN)
57 #define TIM_BUCKET_CHUNK_REMAIN \
58 (TIM_BUCKET_W1_M_CHUNK_REMAINDER << TIM_BUCKET_W1_S_CHUNK_REMAINDER)
60 #define TIM_BUCKET_LOCK \
61 (TIM_BUCKET_W1_M_LOCK << TIM_BUCKET_W1_S_LOCK)
63 #define TIM_BUCKET_SEMA_WLOCK \
64 (TIM_BUCKET_CHUNK_REMAIN | (1ull << TIM_BUCKET_W1_S_LOCK))
66 #define OTX2_MAX_TIM_RINGS (256)
67 #define OTX2_TIM_MAX_BUCKETS (0xFFFFF)
68 #define OTX2_TIM_RING_DEF_CHUNK_SZ (4096)
69 #define OTX2_TIM_CHUNK_ALIGNMENT (16)
70 #define OTX2_TIM_MAX_BURST (RTE_CACHE_LINE_SIZE / \
71 OTX2_TIM_CHUNK_ALIGNMENT)
72 #define OTX2_TIM_NB_CHUNK_SLOTS(sz) (((sz) / OTX2_TIM_CHUNK_ALIGNMENT) - 1)
73 #define OTX2_TIM_MIN_CHUNK_SLOTS (0x8)
74 #define OTX2_TIM_MAX_CHUNK_SLOTS (0x1FFE)
75 #define OTX2_TIM_MIN_TMO_TKS (256)
77 #define OTX2_TIM_SP 0x1
78 #define OTX2_TIM_MP 0x2
79 #define OTX2_TIM_ENA_FB 0x10
80 #define OTX2_TIM_ENA_DFB 0x20
81 #define OTX2_TIM_ENA_STATS 0x40
83 enum otx2_tim_clk_src {
84 OTX2_TIM_CLK_SRC_10NS = RTE_EVENT_TIMER_ADAPTER_CPU_CLK,
85 OTX2_TIM_CLK_SRC_GPIO = RTE_EVENT_TIMER_ADAPTER_EXT_CLK0,
86 OTX2_TIM_CLK_SRC_GTI = RTE_EVENT_TIMER_ADAPTER_EXT_CLK1,
87 OTX2_TIM_CLK_SRC_PTP = RTE_EVENT_TIMER_ADAPTER_EXT_CLK2,
101 int16_t chunk_remainder;
104 uint64_t current_chunk;
106 } __rte_packed __rte_aligned(32);
108 struct otx2_tim_ent {
113 struct otx2_tim_ctl {
115 uint16_t chunk_slots;
116 uint16_t disable_npa;
117 uint16_t enable_stats;
120 struct otx2_tim_evdev {
121 struct rte_pci_device *pci_dev;
122 struct rte_eventdev *event_dev;
123 struct otx2_mbox *mbox;
129 uint16_t chunk_slots;
130 uint16_t min_ring_cnt;
131 uint8_t enable_stats;
132 uint16_t ring_ctl_cnt;
133 struct otx2_tim_ctl *ring_ctl_data;
136 uint16_t tim_msixoff[OTX2_MAX_TIM_RINGS];
139 struct otx2_tim_ring {
141 uint16_t nb_chunk_slots;
143 uint64_t last_updt_cyc;
144 uint64_t ring_start_cyc;
147 struct otx2_tim_bkt *bkt;
148 struct rte_mempool *chunk_pool;
149 struct rte_reciprocal_u64 fast_div;
150 struct rte_reciprocal_u64 fast_bkt;
152 uint8_t prod_type_sp;
153 uint8_t enable_stats;
156 uint8_t ena_periodic;
164 uint64_t tenns_clk_freq;
165 enum otx2_tim_clk_src clk_src;
166 } __rte_cache_aligned;
168 static inline struct otx2_tim_evdev *
171 const struct rte_memzone *mz;
173 mz = rte_memzone_lookup(RTE_STR(OTX2_TIM_EVDEV_NAME));
180 #ifdef RTE_ARCH_ARM64
181 static inline uint64_t
184 return __rte_arm64_cntvct();
187 static inline uint64_t
190 return __rte_arm64_cntfrq();
193 static inline uint64_t
199 static inline uint64_t
206 #define TIM_ARM_FASTPATH_MODES \
207 FP(sp, 0, 0, 0, OTX2_TIM_ENA_DFB | OTX2_TIM_SP) \
208 FP(mp, 0, 0, 1, OTX2_TIM_ENA_DFB | OTX2_TIM_MP) \
209 FP(fb_sp, 0, 1, 0, OTX2_TIM_ENA_FB | OTX2_TIM_SP) \
210 FP(fb_mp, 0, 1, 1, OTX2_TIM_ENA_FB | OTX2_TIM_MP) \
211 FP(stats_mod_sp, 1, 0, 0, \
212 OTX2_TIM_ENA_STATS | OTX2_TIM_ENA_DFB | OTX2_TIM_SP) \
213 FP(stats_mod_mp, 1, 0, 1, \
214 OTX2_TIM_ENA_STATS | OTX2_TIM_ENA_DFB | OTX2_TIM_MP) \
215 FP(stats_mod_fb_sp, 1, 1, 0, \
216 OTX2_TIM_ENA_STATS | OTX2_TIM_ENA_FB | OTX2_TIM_SP) \
217 FP(stats_mod_fb_mp, 1, 1, 1, \
218 OTX2_TIM_ENA_STATS | OTX2_TIM_ENA_FB | OTX2_TIM_MP)
220 #define TIM_ARM_TMO_FASTPATH_MODES \
221 FP(dfb, 0, 0, OTX2_TIM_ENA_DFB) \
222 FP(fb, 0, 1, OTX2_TIM_ENA_FB) \
223 FP(stats_dfb, 1, 0, OTX2_TIM_ENA_STATS | OTX2_TIM_ENA_DFB) \
224 FP(stats_fb, 1, 1, OTX2_TIM_ENA_STATS | OTX2_TIM_ENA_FB)
226 #define FP(_name, _f3, _f2, _f1, flags) \
227 uint16_t otx2_tim_arm_burst_##_name( \
228 const struct rte_event_timer_adapter *adptr, \
229 struct rte_event_timer **tim, const uint16_t nb_timers);
230 TIM_ARM_FASTPATH_MODES
233 #define FP(_name, _f2, _f1, flags) \
234 uint16_t otx2_tim_arm_tmo_tick_burst_##_name( \
235 const struct rte_event_timer_adapter *adptr, \
236 struct rte_event_timer **tim, const uint64_t timeout_tick, \
237 const uint16_t nb_timers);
238 TIM_ARM_TMO_FASTPATH_MODES
241 uint16_t otx2_tim_timer_cancel_burst(
242 const struct rte_event_timer_adapter *adptr,
243 struct rte_event_timer **tim, const uint16_t nb_timers);
245 int otx2_tim_caps_get(const struct rte_eventdev *dev, uint64_t flags,
247 const struct rte_event_timer_adapter_ops **ops);
249 void otx2_tim_init(struct rte_pci_device *pci_dev, struct otx2_dev *cmn_dev);
250 void otx2_tim_fini(void);
253 int tim_register_irq(uint16_t ring_id);
254 void tim_unregister_irq(uint16_t ring_id);
256 #endif /* __OTX2_TIM_EVDEV_H__ */