1 .. SPDX-License-Identifier: BSD-3-Clause
2 Copyright(c) 2019 Marvell International Ltd.
4 Marvell OCTEON TX2 Platform Guide
5 =================================
7 This document gives an overview of **Marvell OCTEON TX2** RVU H/W block,
8 packet flow and procedure to build DPDK on OCTEON TX2 platform.
10 More information about OCTEON TX2 SoC can be found at `Marvell Official Website
11 <https://www.marvell.com/embedded-processors/infrastructure-processors/>`_.
13 Supported OCTEON TX2 SoCs
14 -------------------------
20 OCTEON TX2 Resource Virtualization Unit architecture
21 ----------------------------------------------------
23 The :numref:`figure_octeontx2_resource_virtualization` diagram depicts the
24 RVU architecture and a resource provisioning example.
26 .. _figure_octeontx2_resource_virtualization:
28 .. figure:: img/octeontx2_resource_virtualization.*
30 OCTEON TX2 Resource virtualization architecture and provisioning example
33 Resource Virtualization Unit (RVU) on Marvell's OCTEON TX2 SoC maps HW
34 resources belonging to the network, crypto and other functional blocks onto
35 PCI-compatible physical and virtual functions.
37 Each functional block has multiple local functions (LFs) for
38 provisioning to different PCIe devices. RVU supports multiple PCIe SRIOV
39 physical functions (PFs) and virtual functions (VFs).
41 The :numref:`table_octeontx2_rvu_dpdk_mapping` shows the various local
42 functions (LFs) provided by the RVU and its functional mapping to
45 .. _table_octeontx2_rvu_dpdk_mapping:
47 .. table:: RVU managed functional blocks and its mapping to DPDK subsystem
49 +---+-----+--------------------------------------------------------------+
50 | # | LF | DPDK subsystem mapping |
51 +===+=====+==============================================================+
52 | 1 | NIX | rte_ethdev, rte_tm, rte_event_eth_[rt]x_adapter, rte_security|
53 +---+-----+--------------------------------------------------------------+
54 | 2 | NPA | rte_mempool |
55 +---+-----+--------------------------------------------------------------+
56 | 3 | NPC | rte_flow |
57 +---+-----+--------------------------------------------------------------+
58 | 4 | CPT | rte_cryptodev, rte_event_crypto_adapter |
59 +---+-----+--------------------------------------------------------------+
60 | 5 | SSO | rte_eventdev |
61 +---+-----+--------------------------------------------------------------+
62 | 6 | TIM | rte_event_timer_adapter |
63 +---+-----+--------------------------------------------------------------+
64 | 7 | LBK | rte_ethdev |
65 +---+-----+--------------------------------------------------------------+
66 | 8 | DPI | rte_rawdev |
67 +---+-----+--------------------------------------------------------------+
69 PF0 is called the administrative / admin function (AF) and has exclusive
70 privileges to provision RVU functional block's LFs to each of the PF/VF.
72 PF/VFs communicates with AF via a shared memory region (mailbox).Upon receiving
73 requests from PF/VF, AF does resource provisioning and other HW configuration.
75 AF is always attached to host, but PF/VFs may be used by host kernel itself,
76 or attached to VMs or to userspace applications like DPDK, etc. So, AF has to
77 handle provisioning/configuration requests sent by any device from any domain.
79 The AF driver does not receive or process any data.
80 It is only a configuration driver used in control path.
82 The :numref:`figure_octeontx2_resource_virtualization` diagram also shows a
83 resource provisioning example where,
85 1. PFx and PFx-VF0 bound to Linux netdev driver.
86 2. PFx-VF1 ethdev driver bound to the first DPDK application.
87 3. PFy ethdev driver, PFy-VF0 ethdev driver, PFz eventdev driver, PFm-VF0 cryptodev driver bound to the second DPDK application.
92 Loopback HW Unit (LBK) receives packets from NIX-RX and sends packets back to NIX-TX.
93 The loopback block has N channels and contains data buffering that is shared across
94 all channels. The LBK HW Unit is abstracted using ethdev subsystem, Where PF0's
95 VFs are exposed as ethdev device and odd-even pairs of VFs are tied together,
96 that is, packets sent on odd VF end up received on even VF and vice versa.
97 This would enable HW accelerated means of communication between two domains
98 where even VF bound to the first domain and odd VF bound to the second domain.
100 Typical application usage models are,
102 #. Communication between the Linux kernel and DPDK application.
103 #. Exception path to Linux kernel from DPDK application as SW ``KNI`` replacement.
104 #. Communication between two different DPDK applications.
106 OCTEON TX2 packet flow
107 ----------------------
109 The :numref:`figure_octeontx2_packet_flow_hw_accelerators` diagram depicts
110 the packet flow on OCTEON TX2 SoC in conjunction with use of various HW accelerators.
112 .. _figure_octeontx2_packet_flow_hw_accelerators:
114 .. figure:: img/octeontx2_packet_flow_hw_accelerators.*
116 OCTEON TX2 packet flow in conjunction with use of HW accelerators
121 This section lists dataplane H/W block(s) available in OCTEON TX2 SoC.
124 See :doc:`../nics/octeontx2` for NIX Ethdev driver information.
126 #. **Mempool Driver**
127 See :doc:`../mempool/octeontx2` for NPA mempool driver information.
129 #. **Event Device Driver**
130 See :doc:`../eventdevs/octeontx2` for SSO event device driver information.
132 #. **DMA Rawdev Driver**
133 See :doc:`../rawdevs/octeontx2_dma` for DMA driver information.
135 Procedure to Setup Platform
136 ---------------------------
138 There are three main prerequisites for setting up DPDK on OCTEON TX2
141 1. **OCTEON TX2 Linux kernel driver**
143 The dependent kernel drivers can be obtained from the
144 `kernel.org <https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/net/ethernet/marvell/octeontx2>`_.
146 Alternatively, the Marvell SDK also provides the required kernel drivers.
148 Linux kernel should be configured with the following features enabled:
150 .. code-block:: console
152 # 64K pages enabled for better performance
153 CONFIG_ARM64_64K_PAGES=y
154 CONFIG_ARM64_VA_BITS_48=y
155 # huge pages support enabled
157 CONFIG_HUGETLB_PAGE=y
158 # VFIO enabled with TYPE1 IOMMU at minimum
159 CONFIG_VFIO_IOMMU_TYPE1=y
162 CONFIG_VFIO_NOIOMMU=y
164 CONFIG_VFIO_PCI_MMAP=y
167 # ARMv8.1 LSE atomics
168 CONFIG_ARM64_LSE_ATOMICS=y
170 CONFIG_OCTEONTX2_MBOX=y
171 CONFIG_OCTEONTX2_AF=y
172 # Enable if netdev PF driver required
173 CONFIG_OCTEONTX2_PF=y
174 # Enable if netdev VF driver required
175 CONFIG_OCTEONTX2_VF=y
176 CONFIG_CRYPTO_DEV_OCTEONTX2_CPT=y
177 # Enable if OCTEONTX2 DMA PF driver required
178 CONFIG_OCTEONTX2_DPI_PF=n
180 2. **ARM64 Linux Tool Chain**
182 For example, the *aarch64* Linaro Toolchain, which can be obtained from
183 `here <https://releases.linaro.org/components/toolchain/binaries/7.4-2019.02/aarch64-linux-gnu/>`_.
185 Alternatively, the Marvell SDK also provides GNU GCC toolchain, which is
186 optimized for OCTEON TX2 CPU.
188 3. **Rootfile system**
190 Any *aarch64* supporting filesystem may be used. For example,
191 Ubuntu 15.10 (Wily) or 16.04 LTS (Xenial) userland which can be obtained
192 from `<http://cdimage.ubuntu.com/ubuntu-base/releases/16.04/release/ubuntu-base-16.04.1-base-arm64.tar.gz>`_.
194 Alternatively, the Marvell SDK provides the buildroot based root filesystem.
195 The SDK includes all the above prerequisites necessary to bring up the OCTEON TX2 board.
197 - Follow the DPDK :doc:`../linux_gsg/index` to setup the basic DPDK environment.
203 .. _table_octeontx2_common_debug_options:
205 .. table:: OCTEON TX2 common debug options
207 +---+------------+-------------------------------------------------------+
208 | # | Component | EAL log command |
209 +===+============+=======================================================+
210 | 1 | Common | --log-level='pmd\.octeontx2\.base,8' |
211 +---+------------+-------------------------------------------------------+
212 | 2 | Mailbox | --log-level='pmd\.octeontx2\.mbox,8' |
213 +---+------------+-------------------------------------------------------+
218 The **OCTEON TX2 Linux kernel driver** provides support to dump RVU blocks
219 context or stats using debugfs.
221 Enable ``debugfs`` by:
223 1. Compile kernel with debugfs enabled, i.e ``CONFIG_DEBUGFS=y``.
224 2. Boot OCTEON TX2 with debugfs supported kernel.
225 3. Verify ``debugfs`` mounted by default "mount | grep -i debugfs" or mount it manually by using.
227 .. code-block:: console
229 # mount -t debugfs none /sys/kernel/debug
231 Currently ``debugfs`` supports the following RVU blocks NIX, NPA, NPC, NDC,
234 The file structure under ``/sys/kernel/debug`` is as follows
236 .. code-block:: console
252 | |-- cpt_engines_info
253 | |-- cpt_engines_sts
260 | |-- ndc_rx_hits_miss
262 | |-- ndc_tx_hits_miss
266 | '-- tx_stall_hwissue
275 | '-- rx_miss_act_stats
281 |-- sso_hwgrp_aq_thresh
282 |-- sso_hwgrp_iaq_walk
284 |-- sso_hwgrp_free_list_walk
285 |-- sso_hwgrp_ient_walk
286 '-- sso_hwgrp_taq_walk
288 RVU block LF allocation:
290 .. code-block:: console
292 cat /sys/kernel/debug/octeontx2/rsrc_alloc
294 pcifunc NPA NIX SSO GROUP SSOWS TIM CPT
301 .. code-block:: console
303 cat /sys/kernel/debug/octeontx2/cgx/cgx2/lmac0/stats
305 =======Link Status======
306 Link is UP 40000 Mbps
307 =======RX_STATS======
309 Octets of received packets: 0
310 Received PAUSE packets: 0
311 Received PAUSE and control packets: 0
312 Filtered DMAC0 (NIX-bound) packets: 0
313 Filtered DMAC0 (NIX-bound) octets: 0
314 Packets dropped due to RX FIFO full: 0
315 Octets dropped due to RX FIFO full: 0
317 Filtered DMAC1 (NCSI-bound) packets: 0
318 Filtered DMAC1 (NCSI-bound) octets: 0
319 NCSI-bound packets dropped: 0
320 NCSI-bound octets dropped: 0
321 =======TX_STATS======
322 Packets dropped due to excessive collisions: 0
323 Packets dropped due to excessive deferral: 0
324 Multiple collisions before successful transmission: 0
325 Single collisions before successful transmission: 0
326 Total octets sent on the interface: 0
327 Total frames sent on the interface: 0
328 Packets sent with an octet count < 64: 0
329 Packets sent with an octet count == 64: 0
330 Packets sent with an octet count of 65127: 0
331 Packets sent with an octet count of 128-255: 0
332 Packets sent with an octet count of 256-511: 0
333 Packets sent with an octet count of 512-1023: 0
334 Packets sent with an octet count of 1024-1518: 0
335 Packets sent with an octet count of > 1518: 0
336 Packets sent to a broadcast DMAC: 0
337 Packets sent to the multicast DMAC: 0
338 Transmit underflow and were truncated: 0
339 Control/PAUSE packets sent: 0
343 .. code-block:: console
345 cat /sys/kernel/debug/octeontx2/cpt/cpt_pc
347 CPT instruction requests 0
348 CPT instruction latency 0
349 CPT NCB read requests 0
350 CPT NCB read latency 0
351 CPT read requests caused by UC fills 0
352 CPT active cycles pc 1395642
353 CPT clock count pc 5579867595493
357 .. code-block:: console
359 Usage: echo <nixlf> [cq number/all] > /sys/kernel/debug/octeontx2/nix/cq_ctx
360 cat /sys/kernel/debug/octeontx2/nix/cq_ctx
361 echo 0 0 > /sys/kernel/debug/octeontx2/nix/cq_ctx
362 cat /sys/kernel/debug/octeontx2/nix/cq_ctx
364 =====cq_ctx for nixlf:0 and qidx:0 is=====
375 W2: update_time 31043
392 .. code-block:: console
394 Usage: echo <npalf> [pool number/all] > /sys/kernel/debug/octeontx2/npa/pool_ctx
395 cat /sys/kernel/debug/octeontx2/npa/pool_ctx
396 echo 0 0 > /sys/kernel/debug/octeontx2/npa/pool_ctx
397 cat /sys/kernel/debug/octeontx2/npa/pool_ctx
399 ======POOL : 0=======
400 W0: Stack base 1375bff00
407 W2: stack_max_pages 24315
408 W2: stack_pages 24314
418 W4: update_time 62993
420 W6: ptr_start 1593adf00
421 W7: ptr_end 180000000
427 W8: thresh_qint_idx 0
432 .. code-block:: console
434 cat /sys/kernel/debug/octeontx2/npc/mcam_info
437 RX keywidth : 224bits
438 TX keywidth : 224bits
450 .. code-block:: console
452 Usage: echo [<hws>/all] > /sys/kernel/debug/octeontx2/sso/hws/sso_hws_info
453 echo 0 > /sys/kernel/debug/octeontx2/sso/hws/sso_hws_info
455 ==================================================
456 SSOW HWS[0] Arbitration State 0x0
457 SSOW HWS[0] Guest Machine Control 0x0
458 SSOW HWS[0] SET[0] Group Mask[0] 0xffffffffffffffff
459 SSOW HWS[0] SET[0] Group Mask[1] 0xffffffffffffffff
460 SSOW HWS[0] SET[0] Group Mask[2] 0xffffffffffffffff
461 SSOW HWS[0] SET[0] Group Mask[3] 0xffffffffffffffff
462 SSOW HWS[0] SET[1] Group Mask[0] 0xffffffffffffffff
463 SSOW HWS[0] SET[1] Group Mask[1] 0xffffffffffffffff
464 SSOW HWS[0] SET[1] Group Mask[2] 0xffffffffffffffff
465 SSOW HWS[0] SET[1] Group Mask[3] 0xffffffffffffffff
466 ==================================================
471 DPDK may be compiled either natively on OCTEON TX2 platform or cross-compiled on
472 an x86 based platform.
480 .. code-block:: console
482 make config T=arm64-octeontx2-linux-gcc
485 The example applications can be compiled using the following:
487 .. code-block:: console
491 export RTE_TARGET=build
492 cd examples/<application>
498 .. code-block:: console
506 Refer to :doc:`../linux_gsg/cross_build_dpdk_for_arm64` for generic arm64 details.
511 .. code-block:: console
513 make config T=arm64-octeontx2-linux-gcc
514 make -j CROSS=aarch64-marvell-linux-gnu- CONFIG_RTE_KNI_KMOD=n
519 .. code-block:: console
521 meson build --cross-file config/arm/arm64_octeontx2_linux_gcc
526 By default, meson cross compilation uses ``aarch64-linux-gnu-gcc`` toolchain,
527 if Marvell toolchain is available then it can be used by overriding the
528 c, cpp, ar, strip ``binaries`` attributes to respective Marvell
529 toolchain binaries in ``config/arm/arm64_octeontx2_linux_gcc`` file.