1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2019 Intel Corporation
8 #include "opae_osdep.h"
10 #define ALTERA_I2C_TFR_CMD 0x00 /* Transfer Command register */
11 #define ALTERA_I2C_TFR_CMD_STA BIT(9) /* send START before byte */
12 #define ALTERA_I2C_TFR_CMD_STO BIT(8) /* send STOP after byte */
13 #define ALTERA_I2C_TFR_CMD_RW_D BIT(0) /* Direction of transfer */
14 #define ALTERA_I2C_RX_DATA 0x04 /* RX data FIFO register */
15 #define ALTERA_I2C_CTRL 0x8 /* Control register */
16 #define ALTERA_I2C_CTRL_RXT_SHFT 4 /* RX FIFO Threshold */
17 #define ALTERA_I2C_CTRL_TCT_SHFT 2 /* TFER CMD FIFO Threshold */
18 #define ALTERA_I2C_CTRL_BSPEED BIT(1) /* Bus Speed */
19 #define ALTERA_I2C_CTRL_EN BIT(0) /* Enable Core */
20 #define ALTERA_I2C_ISER 0xc /* Interrupt Status Enable register */
21 #define ALTERA_I2C_ISER_RXOF_EN BIT(4) /* Enable RX OVERFLOW IRQ */
22 #define ALTERA_I2C_ISER_ARB_EN BIT(3) /* Enable ARB LOST IRQ */
23 #define ALTERA_I2C_ISER_NACK_EN BIT(2) /* Enable NACK DET IRQ */
24 #define ALTERA_I2C_ISER_RXRDY_EN BIT(1) /* Enable RX Ready IRQ */
25 #define ALTERA_I2C_ISER_TXRDY_EN BIT(0) /* Enable TX Ready IRQ */
26 #define ALTERA_I2C_ISR 0x10 /* Interrupt Status register */
27 #define ALTERA_I2C_ISR_RXOF BIT(4) /* RX OVERFLOW */
28 #define ALTERA_I2C_ISR_ARB BIT(3) /* ARB LOST */
29 #define ALTERA_I2C_ISR_NACK BIT(2) /* NACK DET */
30 #define ALTERA_I2C_ISR_RXRDY BIT(1) /* RX Ready */
31 #define ALTERA_I2C_ISR_TXRDY BIT(0) /* TX Ready */
32 #define ALTERA_I2C_STATUS 0x14 /* Status register */
33 #define ALTERA_I2C_STAT_CORE BIT(0) /* Core Status */
34 #define ALTERA_I2C_TC_FIFO_LVL 0x18 /* Transfer FIFO LVL register */
35 #define ALTERA_I2C_RX_FIFO_LVL 0x1c /* Receive FIFO LVL register */
36 #define ALTERA_I2C_SCL_LOW 0x20 /* SCL low count register */
37 #define ALTERA_I2C_SCL_HIGH 0x24 /* SCL high count register */
38 #define ALTERA_I2C_SDA_HOLD 0x28 /* SDA hold count register */
40 #define ALTERA_I2C_ALL_IRQ (ALTERA_I2C_ISR_RXOF | ALTERA_I2C_ISR_ARB | \
41 ALTERA_I2C_ISR_NACK | ALTERA_I2C_ISR_RXRDY | \
44 #define ALTERA_I2C_THRESHOLD 0
45 #define ALTERA_I2C_DFLT_FIFO_SZ 8
46 #define ALTERA_I2C_TIMEOUT_US 250000 /* 250ms */
50 #define I2C_CTRL_R BIT_ULL(9)
51 #define I2C_CTRL_W BIT_ULL(8)
52 #define I2C_CTRL_ADDR_MASK GENMASK_ULL(3, 0)
54 #define I2C_READ_DATA_VALID BIT_ULL(32)
55 #define I2C_READ_DATA_MASK GENMASK_ULL(31, 0)
56 #define I2C_WRITE 0x20
57 #define I2C_WRITE_DATA_MASK GENMASK_ULL(31, 0)
59 #define ALTERA_I2C_100KHZ 0
60 #define ALTERA_I2C_400KHZ 1
62 /* i2c slave using 16bit address */
63 #define I2C_FLAG_ADDR16 1
65 #define I2C_XFER_RETRY 10
67 struct i2c_core_param {
73 /*reference clock of I2C core in MHz*/
75 /*Max I2C interface freq*/
78 /* number of MAC address*/
84 struct altera_i2c_dev {
86 struct i2c_core_param i2c_param;
88 u32 bus_clk_rate; /* i2c bus clock */
89 u32 i2c_clk; /* i2c input clock */
95 int (*xfer)(struct altera_i2c_dev *dev, struct i2c_msg *msg, int num);
100 * struct i2c_msg: an I2C message
109 #define I2C_MAX_OFFSET_LEN 4
112 I2C_M_TEN = 0x0010, /*ten-bit chip address*/
113 I2C_M_RD = 0x0001, /*read data*/
114 I2C_M_STOP = 0x8000, /*send stop after this message*/
117 struct altera_i2c_dev *altera_i2c_probe(void *base);
118 void altera_i2c_remove(struct altera_i2c_dev *dev);
119 int i2c_read(struct altera_i2c_dev *dev, int flags, unsigned int slave_addr,
120 u32 offset, u8 *buf, u32 count);
121 int i2c_write(struct altera_i2c_dev *dev, int flags, unsigned int slave_addr,
122 u32 offset, u8 *buffer, int len);
123 int i2c_read8(struct altera_i2c_dev *dev, unsigned int slave_addr, u32 offset,
125 int i2c_read16(struct altera_i2c_dev *dev, unsigned int slave_addr, u32 offset,
127 int i2c_write8(struct altera_i2c_dev *dev, unsigned int slave_addr, u32 offset,
129 int i2c_write16(struct altera_i2c_dev *dev, unsigned int slave_addr, u32 offset,