1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2019 Intel Corporation
5 #ifndef _OPAE_INTEL_MAX10_H_
6 #define _OPAE_INTEL_MAX10_H_
8 #include "opae_osdep.h"
11 struct max10_compatible_id {
15 #define MAX10_PAC "intel,max10"
16 #define MAX10_PAC_N3000 "intel,max10-pac-n3000"
17 #define MAX10_PAC_END "intel,end"
19 /* max10 capability flags */
20 #define MAX10_FLAGS_NO_I2C2 BIT(0)
21 #define MAX10_FLAGS_NO_BMCIMG_FLASH BIT(1)
22 #define MAX10_FLAGS_DEVICE_TABLE BIT(2)
23 #define MAX10_FLAGS_SPI BIT(3)
24 #define MAX10_FLGAS_NIOS_SPI BIT(4)
25 #define MAX10_FLAGS_PKVL BIT(5)
26 #define MAX10_FLAGS_SECURE BIT(6)
27 #define MAX10_FLAGS_MAC_CACHE BIT(7)
29 /** List of opae sensors */
30 TAILQ_HEAD(opae_sensor_list, opae_sensor_info);
32 struct intel_max10_device {
33 unsigned int flags; /*max10 hardware capability*/
34 struct altera_spi_device *spi_master;
35 struct spi_transaction_dev *spi_tran_dev;
36 struct max10_compatible_id *id; /*max10 compatible*/
38 unsigned int base; /* max10 base address */
40 struct opae_sensor_list opae_sensor_list;
56 struct opae_retimer_info {
57 unsigned int nums_retimer;
58 unsigned int ports_per_retimer;
59 unsigned int nums_fvl;
60 unsigned int ports_per_fvl;
61 enum retimer_speed support_speed;
65 struct opae_retimer_status {
66 enum retimer_speed speed;
68 * retimer line link status bitmap:
69 * bit 0: Retimer0 Port0 link status
70 * bit 1: Retimer0 Port1 link status
71 * bit 2: Retimer0 Port2 link status
72 * bit 3: Retimer0 Port3 link status
74 * bit 4: Retimer1 Port0 link status
75 * bit 5: Retimer1 Port1 link status
76 * bit 6: Retimer1 Port2 link status
77 * bit 7: Retimer1 Port3 link status
79 unsigned int line_link_bitmap;
82 #define FLASH_BASE 0x10000000
83 #define FLASH_OPTION_BITS 0x10000
85 /* System Registers */
86 #define MAX10_BASE_ADDR 0x300400
87 #define MAX10_SEC_BASE_ADDR 0x300800
88 /* Register offset of system registers */
89 #define NIOS2_FW_VERSION 0x0
90 #define MAX10_MACADDR1 0x10
91 #define MAX10_MAC_BYTE4 GENMASK(7, 0)
92 #define MAX10_MAC_BYTE3 GENMASK(15, 8)
93 #define MAX10_MAC_BYTE2 GENMASK(23, 16)
94 #define MAX10_MAC_BYTE1 GENMASK(31, 24)
95 #define MAX10_MACADDR2 0x14
96 #define MAX10_MAC_BYTE6 GENMASK(7, 0)
97 #define MAX10_MAC_BYTE5 GENMASK(15, 8)
98 #define MAX10_MAC_COUNT GENMASK(23, 16)
100 #define FPGA_RECONF_PAGE GENMASK(2, 0)
101 #define FPGA_RP_LOAD BIT(3)
102 #define NIOS2_PRERESET BIT(4)
103 #define NIOS2_HANG BIT(5)
104 #define RSU_ENABLE BIT(6)
105 #define NIOS2_RESET BIT(7)
106 #define NIOS2_I2C2_POLL_STOP BIT(13)
107 #define PKVL_EEPROM_LOAD BIT(31)
108 #define FPGA_RECONF_REG 0x30
109 #define MAX10_TEST_REG 0x3c
110 #define COUNTDOWN_START BIT(18)
111 #define MAX10_BUILD_VER 0x68
112 #define MAX10_VERSION_MAJOR GENMASK(23, 16)
113 #define PCB_INFO GENMASK(31, 24)
114 #define FPGA_PAGE_INFO 0x6c
115 #define DT_AVAIL_REG 0x90
116 #define DT_AVAIL BIT(0)
117 #define DT_BASE_ADDR_REG 0x94
118 #define MAX10_DOORBELL 0x400
119 #define RSU_REQUEST BIT(0)
120 #define SEC_PROGRESS GENMASK(7, 4)
121 #define HOST_STATUS GENMASK(11, 8)
122 #define SEC_STATUS GENMASK(23, 16)
124 /* PKVL related registers, in system register region */
125 #define PKVL_POLLING_CTRL 0x80
126 #define POLLING_MODE GENMASK(15, 0)
127 #define PKVL_A_PRELOAD BIT(16)
128 #define PKVL_A_PRELOAD_TIMEOUT BIT(17)
129 #define PKVL_A_DATA_TOO_BIG BIT(18)
130 #define PKVL_A_HDR_CHECKSUM BIT(20)
131 #define PKVL_B_PRELOAD BIT(24)
132 #define PKVL_B_PRELOAD_TIMEOUT BIT(25)
133 #define PKVL_B_DATA_TOO_BIG BIT(26)
134 #define PKVL_B_HDR_CHECKSUM BIT(28)
135 #define PKVL_EEPROM_UPG_STATUS GENMASK(31, 16)
136 #define PKVL_LINK_STATUS 0x164
137 #define PKVL_A_VERSION 0x254
138 #define PKVL_B_VERSION 0x258
139 #define SERDES_VERSION GENMASK(15, 0)
140 #define SBUS_VERSION GENMASK(31, 16)
142 #define DFT_MAX_SIZE 0x7e0000
144 int max10_reg_read(struct intel_max10_device *dev,
145 unsigned int reg, unsigned int *val);
146 int max10_reg_write(struct intel_max10_device *dev,
147 unsigned int reg, unsigned int val);
148 int max10_sys_read(struct intel_max10_device *dev,
149 unsigned int offset, unsigned int *val);
150 int max10_sys_write(struct intel_max10_device *dev,
151 unsigned int offset, unsigned int val);
152 struct intel_max10_device *
153 intel_max10_device_probe(struct altera_spi_device *spi,
155 int intel_max10_device_remove(struct intel_max10_device *dev);
158 #define SENSOR_REG_VALUE 0x0
159 #define SENSOR_REG_HIGH_WARN 0x1
160 #define SENSOR_REG_HIGH_FATAL 0x2
161 #define SENSOR_REG_LOW_WARN 0x3
162 #define SENSOR_REG_LOW_FATAL 0x4
163 #define SENSOR_REG_HYSTERESIS 0x5
164 #define SENSOR_REG_MAX 0x6
166 static const char * const sensor_reg_name[] = {
180 struct raw_sensor_info {
184 unsigned int multiplier;
185 struct sensor_reg regs[SENSOR_REG_MAX];
188 #define OPAE_SENSOR_VALID 0x1
189 #define OPAE_SENSOR_HIGH_WARN_VALID 0x2
190 #define OPAE_SENSOR_HIGH_FATAL_VALID 0x4
191 #define OPAE_SENSOR_LOW_WARN_VALID 0x8
192 #define OPAE_SENSOR_LOW_FATAL_VALID 0x10
193 #define OPAE_SENSOR_HYSTERESIS_VALID 0x20
195 struct opae_sensor_info {
196 TAILQ_ENTRY(opae_sensor_info) node;
200 unsigned int high_fatal;
201 unsigned int high_warn;
202 unsigned int low_fatal;
203 unsigned int low_warn;
204 unsigned int hysteresis;
205 unsigned int multiplier;
208 unsigned int value_reg;