1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2019 Marvell International Ltd.
5 #ifndef _OTX2_COMMON_H_
6 #define _OTX2_COMMON_H_
8 #include <rte_atomic.h>
9 #include <rte_common.h>
10 #include <rte_cycles.h>
11 #include <rte_memory.h>
12 #include <rte_memzone.h>
15 #include "hw/otx2_rvu.h"
16 #include "hw/otx2_nix.h"
17 #include "hw/otx2_npc.h"
18 #include "hw/otx2_npa.h"
19 #include "hw/otx2_sdp.h"
20 #include "hw/otx2_sso.h"
21 #include "hw/otx2_ssow.h"
22 #include "hw/otx2_tim.h"
25 #define OTX2_ALIGN 128
27 /* Bits manipulation */
29 #define BIT_ULL(nr) (1ULL << (nr))
32 #define BIT(nr) (1UL << (nr))
36 #define BITS_PER_LONG (__SIZEOF_LONG__ * 8)
38 #ifndef BITS_PER_LONG_LONG
39 #define BITS_PER_LONG_LONG (__SIZEOF_LONG_LONG__ * 8)
43 #define GENMASK(h, l) \
44 (((~0UL) << (l)) & (~0UL >> (BITS_PER_LONG - 1 - (h))))
47 #define GENMASK_ULL(h, l) \
48 (((~0ULL) - (1ULL << (l)) + 1) & \
49 (~0ULL >> (BITS_PER_LONG_LONG - 1 - (h))))
52 /* Compiler attributes */
54 #define __hot __attribute__((hot))
57 /* Intra device related functions */
59 struct otx2_idev_cfg {
62 struct otx2_npa_lf *npa_lf;
65 rte_atomic16_t npa_refcnt;
66 uint16_t npa_refcnt_u16;
70 struct otx2_idev_cfg *otx2_intra_dev_get_cfg(void);
71 void otx2_sso_pf_func_set(uint16_t sso_pf_func);
72 uint16_t otx2_sso_pf_func_get(void);
73 uint16_t otx2_npa_pf_func_get(void);
74 struct otx2_npa_lf *otx2_npa_lf_obj_get(void);
75 void otx2_npa_set_defaults(struct otx2_idev_cfg *idev);
76 int otx2_npa_lf_active(void *dev);
77 int otx2_npa_lf_obj_ref(void);
80 extern int otx2_logtype_base;
81 extern int otx2_logtype_mbox;
82 extern int otx2_logtype_npa;
83 extern int otx2_logtype_nix;
84 extern int otx2_logtype_sso;
85 extern int otx2_logtype_npc;
86 extern int otx2_logtype_tm;
87 extern int otx2_logtype_tim;
88 extern int otx2_logtype_dpi;
89 extern int otx2_logtype_ep;
91 #define otx2_err(fmt, args...) \
92 RTE_LOG(ERR, PMD, "%s():%u " fmt "\n", \
93 __func__, __LINE__, ## args)
95 #define otx2_info(fmt, args...) \
96 RTE_LOG(INFO, PMD, fmt"\n", ## args)
98 #define otx2_dbg(subsystem, fmt, args...) \
99 rte_log(RTE_LOG_DEBUG, otx2_logtype_ ## subsystem, \
100 "[%s] %s():%u " fmt "\n", \
101 #subsystem, __func__, __LINE__, ##args)
103 #define otx2_base_dbg(fmt, ...) otx2_dbg(base, fmt, ##__VA_ARGS__)
104 #define otx2_mbox_dbg(fmt, ...) otx2_dbg(mbox, fmt, ##__VA_ARGS__)
105 #define otx2_npa_dbg(fmt, ...) otx2_dbg(npa, fmt, ##__VA_ARGS__)
106 #define otx2_nix_dbg(fmt, ...) otx2_dbg(nix, fmt, ##__VA_ARGS__)
107 #define otx2_sso_dbg(fmt, ...) otx2_dbg(sso, fmt, ##__VA_ARGS__)
108 #define otx2_npc_dbg(fmt, ...) otx2_dbg(npc, fmt, ##__VA_ARGS__)
109 #define otx2_tm_dbg(fmt, ...) otx2_dbg(tm, fmt, ##__VA_ARGS__)
110 #define otx2_tim_dbg(fmt, ...) otx2_dbg(tim, fmt, ##__VA_ARGS__)
111 #define otx2_dpi_dbg(fmt, ...) otx2_dbg(dpi, fmt, ##__VA_ARGS__)
112 #define otx2_sdp_dbg(fmt, ...) otx2_dbg(ep, fmt, ##__VA_ARGS__)
115 #define PCI_VENDOR_ID_CAVIUM 0x177D
116 #define PCI_DEVID_OCTEONTX2_RVU_PF 0xA063
117 #define PCI_DEVID_OCTEONTX2_RVU_VF 0xA064
118 #define PCI_DEVID_OCTEONTX2_RVU_AF 0xA065
119 #define PCI_DEVID_OCTEONTX2_RVU_SSO_TIM_PF 0xA0F9
120 #define PCI_DEVID_OCTEONTX2_RVU_SSO_TIM_VF 0xA0FA
121 #define PCI_DEVID_OCTEONTX2_RVU_NPA_PF 0xA0FB
122 #define PCI_DEVID_OCTEONTX2_RVU_NPA_VF 0xA0FC
123 #define PCI_DEVID_OCTEONTX2_RVU_CPT_PF 0xA0FD
124 #define PCI_DEVID_OCTEONTX2_RVU_CPT_VF 0xA0FE
125 #define PCI_DEVID_OCTEONTX2_RVU_AF_VF 0xA0f8
126 #define PCI_DEVID_OCTEONTX2_DPI_VF 0xA081
127 #define PCI_DEVID_OCTEONTX2_EP_VF 0xB203 /* OCTEON TX2 EP mode */
128 #define PCI_DEVID_OCTEONTX2_RVU_SDP_PF 0xA0f6
129 #define PCI_DEVID_OCTEONTX2_RVU_SDP_VF 0xA0f7
132 * REVID for RVU PCIe devices.
133 * Bits 0..1: minor pass
134 * Bits 3..2: major pass
135 * Bits 7..4: midr id, 0:96, 1:95, 2:loki, f:unknown
138 #define RVU_PCI_REV_MIDR_ID(rev_id) (rev_id >> 4)
139 #define RVU_PCI_REV_MAJOR(rev_id) ((rev_id >> 2) & 0x3)
140 #define RVU_PCI_REV_MINOR(rev_id) (rev_id & 0x3)
142 #define RVU_PCI_CN96XX_MIDR_ID 0x0
143 #define RVU_PCI_CNF95XX_MIDR_ID 0x1
145 /* PCI Config offsets */
146 #define RVU_PCI_REVISION_ID 0x08
149 #define otx2_read64(addr) rte_read64_relaxed((void *)(addr))
150 #define otx2_write64(val, addr) rte_write64_relaxed((val), (void *)(addr))
152 #if defined(RTE_ARCH_ARM64)
153 #include "otx2_io_arm64.h"
155 #include "otx2_io_generic.h"
158 /* Fastpath lookup */
159 #define OTX2_NIX_FASTPATH_LOOKUP_MEM "otx2_nix_fastpath_lookup_mem"
160 #define OTX2_NIX_SA_TBL_START (4096*4 + 69632*2)
162 #endif /* _OTX2_COMMON_H_ */