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38 #include <rte_common.h>
39 #include <rte_byteorder.h>
41 #include <rte_malloc.h>
42 #include <rte_ethdev.h>
44 #include <rte_ether.h>
47 #include <rte_port_ethdev.h>
48 #include <rte_port_ring.h>
49 #include <rte_port_frag.h>
50 #include <rte_table_stub.h>
51 #include <rte_pipeline.h>
56 app_main_loop_pipeline_ipv4_frag(void) {
57 struct rte_pipeline *p;
58 uint32_t port_in_id[APP_MAX_PORTS];
59 uint32_t port_out_id[APP_MAX_PORTS];
60 uint32_t table_id[APP_MAX_PORTS];
63 uint32_t core_id = rte_lcore_id();
64 struct app_core_params *core_params = app_get_core_params(core_id);
66 if ((core_params == NULL) ||
67 (core_params->core_type != APP_CORE_IPV4_FRAG))
68 rte_panic("Core %u misconfiguration\n", core_id);
70 RTE_LOG(INFO, USER1, "Core %u is doing IPv4 fragmentation\n", core_id);
72 /* Pipeline configuration */
73 struct rte_pipeline_params pipeline_params = {
75 .socket_id = rte_socket_id(),
78 p = rte_pipeline_create(&pipeline_params);
80 rte_panic("%s: Unable to configure the pipeline\n", __func__);
82 /* Input port configuration */
83 for (i = 0; i < app.n_ports; i++) {
84 struct rte_port_ring_reader_ipv4_frag_params
86 .ring = app.rings[core_params->swq_in[i]],
88 .metadata_size = sizeof(struct app_pkt_metadata),
89 .pool_direct = app.pool,
90 .pool_indirect = app.indirect_pool,
93 struct rte_pipeline_port_in_params port_params = {
94 .ops = &rte_port_ring_reader_ipv4_frag_ops,
95 .arg_create = (void *) &port_frag_params,
98 .burst_size = app.bsz_swq_rd,
101 if (rte_pipeline_port_in_create(p, &port_params,
103 rte_panic("%s: Unable to configure input port %i\n",
107 /* Output port configuration */
108 for (i = 0; i < app.n_ports; i++) {
109 struct rte_port_ring_writer_params port_ring_params = {
110 .ring = app.rings[core_params->swq_out[i]],
111 .tx_burst_sz = app.bsz_swq_wr,
114 struct rte_pipeline_port_out_params port_params = {
115 .ops = &rte_port_ring_writer_ops,
116 .arg_create = (void *) &port_ring_params,
118 .f_action_bulk = NULL,
122 if (rte_pipeline_port_out_create(p, &port_params,
124 rte_panic("%s: Unable to configure output port %i\n",
128 /* Table configuration */
129 for (i = 0; i < app.n_ports; i++) {
130 struct rte_pipeline_table_params table_params = {
131 .ops = &rte_table_stub_ops,
133 .f_action_hit = NULL,
134 .f_action_miss = NULL,
136 .action_data_size = 0,
139 if (rte_pipeline_table_create(p, &table_params, &table_id[i]))
140 rte_panic("%s: Unable to configure table %u\n",
141 __func__, table_id[i]);
144 /* Interconnecting ports and tables */
145 for (i = 0; i < app.n_ports; i++)
146 if (rte_pipeline_port_in_connect_to_table(p, port_in_id[i],
148 rte_panic("%s: Unable to connect input port %u to "
149 "table %u\n", __func__, port_in_id[i],
152 /* Add entries to tables */
153 for (i = 0; i < app.n_ports; i++) {
154 struct rte_pipeline_table_entry default_entry = {
155 .action = RTE_PIPELINE_ACTION_PORT,
156 {.port_id = port_out_id[i]},
159 struct rte_pipeline_table_entry *default_entry_ptr;
161 if (rte_pipeline_table_default_entry_add(p, table_id[i],
162 &default_entry, &default_entry_ptr))
163 rte_panic("%s: Unable to add default entry to "
164 "table %u\n", __func__, table_id[i]);
167 /* Enable input ports */
168 for (i = 0; i < app.n_ports; i++)
169 if (rte_pipeline_port_in_enable(p, port_in_id[i]))
170 rte_panic("Unable to enable input port %u\n",
173 /* Check pipeline consistency */
174 if (rte_pipeline_check(p) < 0)
175 rte_panic("%s: Pipeline consistency check failed\n", __func__);
181 if ((i & APP_FLUSH) == 0)
182 rte_pipeline_flush(p);