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38 #include <rte_common.h>
39 #include <rte_byteorder.h>
41 #include <rte_malloc.h>
42 #include <rte_ethdev.h>
44 #include <rte_ether.h>
47 #include <rte_port_ethdev.h>
48 #include <rte_port_ring.h>
49 #include <rte_table_stub.h>
50 #include <rte_pipeline.h>
54 static struct ether_addr local_ether_addr = {
55 .addr_bytes = {0, 1, 2, 3, 4, 5},
59 app_pkt_metadata_flush(struct rte_mbuf *pkt)
61 struct app_pkt_metadata *pkt_meta = (struct app_pkt_metadata *)
62 RTE_MBUF_METADATA_UINT8_PTR(pkt, 0);
63 struct ether_hdr *ether_hdr = (struct ether_hdr *)
64 rte_pktmbuf_prepend(pkt, (uint16_t) sizeof(struct ether_hdr));
66 ether_addr_copy(&pkt_meta->nh_arp, ðer_hdr->d_addr);
67 ether_addr_copy(&local_ether_addr, ðer_hdr->s_addr);
68 ether_hdr->ether_type = rte_bswap16(ETHER_TYPE_IPv4);
69 pkt->l2_len = sizeof(struct ether_hdr);
73 app_pipeline_tx_port_in_action_handler(
74 struct rte_mbuf **pkts,
77 __rte_unused void *arg)
81 for (i = 0; i < n; i++) {
82 struct rte_mbuf *m = pkts[i];
84 app_pkt_metadata_flush(m);
87 *pkts_mask = (~0LLU) >> (64 - n);
93 app_main_loop_pipeline_tx(void) {
94 struct rte_pipeline *p;
95 uint32_t port_in_id[APP_MAX_PORTS];
96 uint32_t port_out_id[APP_MAX_PORTS];
97 uint32_t table_id[APP_MAX_PORTS];
100 uint32_t core_id = rte_lcore_id();
101 struct app_core_params *core_params = app_get_core_params(core_id);
103 if ((core_params == NULL) || (core_params->core_type != APP_CORE_TX))
104 rte_panic("Core %u misconfiguration\n", core_id);
106 RTE_LOG(INFO, USER1, "Core %u is doing TX\n", core_id);
108 /* Pipeline configuration */
109 struct rte_pipeline_params pipeline_params = {
111 .socket_id = rte_socket_id(),
114 p = rte_pipeline_create(&pipeline_params);
116 rte_panic("%s: Unable to configure the pipeline\n", __func__);
118 /* Input port configuration */
119 for (i = 0; i < app.n_ports; i++) {
120 struct rte_port_ring_reader_params port_ring_params = {
121 .ring = app.rings[core_params->swq_in[i]],
124 struct rte_pipeline_port_in_params port_params = {
125 .ops = &rte_port_ring_reader_ops,
126 .arg_create = (void *) &port_ring_params,
127 .f_action = (app.ether_hdr_pop_push) ?
128 app_pipeline_tx_port_in_action_handler : NULL,
130 .burst_size = app.bsz_swq_rd,
133 if (rte_pipeline_port_in_create(p, &port_params,
135 rte_panic("%s: Unable to configure input port for "
136 "ring TX %i\n", __func__, i);
140 /* Output port configuration */
141 for (i = 0; i < app.n_ports; i++) {
142 struct rte_port_ethdev_writer_params port_ethdev_params = {
143 .port_id = app.ports[i],
145 .tx_burst_sz = app.bsz_hwq_wr,
148 struct rte_pipeline_port_out_params port_params = {
149 .ops = &rte_port_ethdev_writer_ops,
150 .arg_create = (void *) &port_ethdev_params,
152 .f_action_bulk = NULL,
156 if (rte_pipeline_port_out_create(p, &port_params,
158 rte_panic("%s: Unable to configure output port for "
159 "port %d\n", __func__, app.ports[i]);
163 /* Table configuration */
164 for (i = 0; i < app.n_ports; i++) {
165 struct rte_pipeline_table_params table_params = {
166 .ops = &rte_table_stub_ops,
168 .f_action_hit = NULL,
169 .f_action_miss = NULL,
171 .action_data_size = 0,
174 if (rte_pipeline_table_create(p, &table_params, &table_id[i])) {
175 rte_panic("%s: Unable to configure table %u\n",
176 __func__, table_id[i]);
180 /* Interconnecting ports and tables */
181 for (i = 0; i < app.n_ports; i++)
182 if (rte_pipeline_port_in_connect_to_table(p, port_in_id[i],
184 rte_panic("%s: Unable to connect input port %u to "
185 "table %u\n", __func__, port_in_id[i],
188 /* Add entries to tables */
189 for (i = 0; i < app.n_ports; i++) {
190 struct rte_pipeline_table_entry default_entry = {
191 .action = RTE_PIPELINE_ACTION_PORT,
192 {.port_id = port_out_id[i]},
195 struct rte_pipeline_table_entry *default_entry_ptr;
197 if (rte_pipeline_table_default_entry_add(p, table_id[i],
198 &default_entry, &default_entry_ptr))
199 rte_panic("%s: Unable to add default entry to "
200 "table %u\n", __func__, table_id[i]);
203 /* Enable input ports */
204 for (i = 0; i < app.n_ports; i++)
205 if (rte_pipeline_port_in_enable(p, port_in_id[i]))
206 rte_panic("Unable to enable input port %u\n",
209 /* Check pipeline consistency */
210 if (rte_pipeline_check(p) < 0)
211 rte_panic("%s: Pipeline consistency check failed\n", __func__);
217 if ((i & APP_FLUSH) == 0)
218 rte_pipeline_flush(p);
223 app_main_loop_tx(void) {
224 struct app_mbuf_array *m[APP_MAX_PORTS];
227 uint32_t core_id = rte_lcore_id();
228 struct app_core_params *core_params = app_get_core_params(core_id);
230 if ((core_params == NULL) || (core_params->core_type != APP_CORE_TX))
231 rte_panic("Core %u misconfiguration\n", core_id);
233 RTE_LOG(INFO, USER1, "Core %u is doing TX (no pipeline)\n", core_id);
235 for (i = 0; i < APP_MAX_PORTS; i++) {
236 m[i] = rte_malloc_socket(NULL, sizeof(struct app_mbuf_array),
237 CACHE_LINE_SIZE, rte_socket_id());
239 rte_panic("%s: Cannot allocate buffer space\n",
243 for (i = 0; ; i = ((i + 1) & (app.n_ports - 1))) {
244 uint32_t n_mbufs, n_pkts;
247 n_mbufs = m[i]->n_mbufs;
249 ret = rte_ring_sc_dequeue_bulk(
250 app.rings[core_params->swq_in[i]],
251 (void **) &m[i]->array[n_mbufs],
257 n_mbufs += app.bsz_swq_rd;
259 if (n_mbufs < app.bsz_hwq_wr) {
260 m[i]->n_mbufs = n_mbufs;
264 n_pkts = rte_eth_tx_burst(
270 if (n_pkts < n_mbufs) {
273 for (k = n_pkts; k < n_mbufs; k++) {
274 struct rte_mbuf *pkt_to_free;
276 pkt_to_free = m[i]->array[k];
277 rte_pktmbuf_free(pkt_to_free);