4 * Copyright(c) 2015-2016 Intel Corporation. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 #include <sys/queue.h>
43 #include <rte_common.h>
45 #include <rte_debug.h>
46 #include <rte_memory.h>
47 #include <rte_memzone.h>
48 #include <rte_tailq.h>
49 #include <rte_ether.h>
50 #include <rte_malloc.h>
51 #include <rte_launch.h>
53 #include <rte_per_lcore.h>
54 #include <rte_lcore.h>
55 #include <rte_atomic.h>
56 #include <rte_branch_prediction.h>
57 #include <rte_mempool.h>
59 #include <rte_string_fns.h>
60 #include <rte_spinlock.h>
61 #include <rte_hexdump.h>
62 #include <rte_crypto_sym.h>
63 #include <openssl/evp.h>
67 #include "qat_crypto.h"
68 #include "adf_transport_access_macros.h"
73 qat_is_cipher_alg_supported(enum rte_crypto_cipher_algorithm algo,
74 struct qat_pmd_private *internals) {
76 const struct rte_cryptodev_capabilities *capability;
78 while ((capability = &(internals->qat_dev_capabilities[i++]))->op !=
79 RTE_CRYPTO_OP_TYPE_UNDEFINED) {
80 if (capability->op != RTE_CRYPTO_OP_TYPE_SYMMETRIC)
83 if (capability->sym.xform_type != RTE_CRYPTO_SYM_XFORM_CIPHER)
86 if (capability->sym.cipher.algo == algo)
93 qat_is_auth_alg_supported(enum rte_crypto_auth_algorithm algo,
94 struct qat_pmd_private *internals) {
96 const struct rte_cryptodev_capabilities *capability;
98 while ((capability = &(internals->qat_dev_capabilities[i++]))->op !=
99 RTE_CRYPTO_OP_TYPE_UNDEFINED) {
100 if (capability->op != RTE_CRYPTO_OP_TYPE_SYMMETRIC)
103 if (capability->sym.xform_type != RTE_CRYPTO_SYM_XFORM_AUTH)
106 if (capability->sym.auth.algo == algo)
112 /** Encrypt a single partial block
113 * Depends on openssl libcrypto
114 * Uses ECB+XOR to do CFB encryption, same result, more performant
117 bpi_cipher_encrypt(uint8_t *src, uint8_t *dst,
118 uint8_t *iv, int ivlen, int srclen,
121 EVP_CIPHER_CTX *ctx = (EVP_CIPHER_CTX *)bpi_ctx;
123 uint8_t encrypted_iv[16];
126 /* ECB method: encrypt the IV, then XOR this with plaintext */
127 if (EVP_EncryptUpdate(ctx, encrypted_iv, &encrypted_ivlen, iv, ivlen)
129 goto cipher_encrypt_err;
131 for (i = 0; i < srclen; i++)
132 *(dst+i) = *(src+i)^(encrypted_iv[i]);
137 PMD_DRV_LOG(ERR, "libcrypto ECB cipher encrypt failed");
141 /** Decrypt a single partial block
142 * Depends on openssl libcrypto
143 * Uses ECB+XOR to do CFB encryption, same result, more performant
146 bpi_cipher_decrypt(uint8_t *src, uint8_t *dst,
147 uint8_t *iv, int ivlen, int srclen,
150 EVP_CIPHER_CTX *ctx = (EVP_CIPHER_CTX *)bpi_ctx;
152 uint8_t encrypted_iv[16];
155 /* ECB method: encrypt (not decrypt!) the IV, then XOR with plaintext */
156 if (EVP_EncryptUpdate(ctx, encrypted_iv, &encrypted_ivlen, iv, ivlen)
158 goto cipher_decrypt_err;
160 for (i = 0; i < srclen; i++)
161 *(dst+i) = *(src+i)^(encrypted_iv[i]);
166 PMD_DRV_LOG(ERR, "libcrypto ECB cipher encrypt for BPI IV failed");
170 /** Creates a context in either AES or DES in ECB mode
171 * Depends on openssl libcrypto
174 bpi_cipher_ctx_init(enum rte_crypto_cipher_algorithm cryptodev_algo,
175 enum rte_crypto_cipher_operation direction __rte_unused,
178 const EVP_CIPHER *algo = NULL;
179 EVP_CIPHER_CTX *ctx = EVP_CIPHER_CTX_new();
184 if (cryptodev_algo == RTE_CRYPTO_CIPHER_DES_DOCSISBPI)
185 algo = EVP_des_ecb();
187 algo = EVP_aes_128_ecb();
189 /* IV will be ECB encrypted whether direction is encrypt or decrypt*/
190 if (EVP_EncryptInit_ex(ctx, algo, NULL, key, 0) != 1)
197 EVP_CIPHER_CTX_free(ctx);
201 /** Frees a context previously created
202 * Depends on openssl libcrypto
205 bpi_cipher_ctx_free(void *bpi_ctx)
208 EVP_CIPHER_CTX_free((EVP_CIPHER_CTX *)bpi_ctx);
211 static inline uint32_t
212 adf_modulo(uint32_t data, uint32_t shift);
215 qat_write_hw_desc_entry(struct rte_crypto_op *op, uint8_t *out_msg,
216 struct qat_crypto_op_cookie *qat_op_cookie);
218 void qat_crypto_sym_clear_session(struct rte_cryptodev *dev,
221 struct qat_session *sess = session;
222 phys_addr_t cd_paddr;
224 PMD_INIT_FUNC_TRACE();
227 bpi_cipher_ctx_free(sess->bpi_ctx);
228 sess->bpi_ctx = NULL;
230 cd_paddr = sess->cd_paddr;
231 memset(sess, 0, qat_crypto_sym_get_session_private_size(dev));
232 sess->cd_paddr = cd_paddr;
234 PMD_DRV_LOG(ERR, "NULL session");
238 qat_get_cmd_id(const struct rte_crypto_sym_xform *xform)
241 if (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER && xform->next == NULL)
242 return ICP_QAT_FW_LA_CMD_CIPHER;
244 /* Authentication Only */
245 if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH && xform->next == NULL)
246 return ICP_QAT_FW_LA_CMD_AUTH;
248 if (xform->next == NULL)
251 /* Cipher then Authenticate */
252 if (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER &&
253 xform->next->type == RTE_CRYPTO_SYM_XFORM_AUTH)
254 return ICP_QAT_FW_LA_CMD_CIPHER_HASH;
256 /* Authenticate then Cipher */
257 if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH &&
258 xform->next->type == RTE_CRYPTO_SYM_XFORM_CIPHER)
259 return ICP_QAT_FW_LA_CMD_HASH_CIPHER;
264 static struct rte_crypto_auth_xform *
265 qat_get_auth_xform(struct rte_crypto_sym_xform *xform)
268 if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH)
277 static struct rte_crypto_cipher_xform *
278 qat_get_cipher_xform(struct rte_crypto_sym_xform *xform)
281 if (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER)
282 return &xform->cipher;
290 qat_crypto_sym_configure_session_cipher(struct rte_cryptodev *dev,
291 struct rte_crypto_sym_xform *xform, void *session_private)
293 struct qat_session *session = session_private;
294 struct qat_pmd_private *internals = dev->data->dev_private;
295 struct rte_crypto_cipher_xform *cipher_xform = NULL;
297 /* Get cipher xform from crypto xform chain */
298 cipher_xform = qat_get_cipher_xform(xform);
300 switch (cipher_xform->algo) {
301 case RTE_CRYPTO_CIPHER_AES_CBC:
302 if (qat_alg_validate_aes_key(cipher_xform->key.length,
303 &session->qat_cipher_alg) != 0) {
304 PMD_DRV_LOG(ERR, "Invalid AES cipher key size");
307 session->qat_mode = ICP_QAT_HW_CIPHER_CBC_MODE;
309 case RTE_CRYPTO_CIPHER_AES_GCM:
310 if (qat_alg_validate_aes_key(cipher_xform->key.length,
311 &session->qat_cipher_alg) != 0) {
312 PMD_DRV_LOG(ERR, "Invalid AES cipher key size");
315 session->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE;
317 case RTE_CRYPTO_CIPHER_AES_CTR:
318 if (qat_alg_validate_aes_key(cipher_xform->key.length,
319 &session->qat_cipher_alg) != 0) {
320 PMD_DRV_LOG(ERR, "Invalid AES cipher key size");
323 session->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE;
325 case RTE_CRYPTO_CIPHER_SNOW3G_UEA2:
326 if (qat_alg_validate_snow3g_key(cipher_xform->key.length,
327 &session->qat_cipher_alg) != 0) {
328 PMD_DRV_LOG(ERR, "Invalid SNOW 3G cipher key size");
331 session->qat_mode = ICP_QAT_HW_CIPHER_ECB_MODE;
333 case RTE_CRYPTO_CIPHER_NULL:
334 session->qat_mode = ICP_QAT_HW_CIPHER_ECB_MODE;
336 case RTE_CRYPTO_CIPHER_KASUMI_F8:
337 if (qat_alg_validate_kasumi_key(cipher_xform->key.length,
338 &session->qat_cipher_alg) != 0) {
339 PMD_DRV_LOG(ERR, "Invalid KASUMI cipher key size");
342 session->qat_mode = ICP_QAT_HW_CIPHER_F8_MODE;
344 case RTE_CRYPTO_CIPHER_3DES_CBC:
345 if (qat_alg_validate_3des_key(cipher_xform->key.length,
346 &session->qat_cipher_alg) != 0) {
347 PMD_DRV_LOG(ERR, "Invalid 3DES cipher key size");
350 session->qat_mode = ICP_QAT_HW_CIPHER_CBC_MODE;
352 case RTE_CRYPTO_CIPHER_DES_CBC:
353 if (qat_alg_validate_des_key(cipher_xform->key.length,
354 &session->qat_cipher_alg) != 0) {
355 PMD_DRV_LOG(ERR, "Invalid DES cipher key size");
358 session->qat_mode = ICP_QAT_HW_CIPHER_CBC_MODE;
360 case RTE_CRYPTO_CIPHER_3DES_CTR:
361 if (qat_alg_validate_3des_key(cipher_xform->key.length,
362 &session->qat_cipher_alg) != 0) {
363 PMD_DRV_LOG(ERR, "Invalid 3DES cipher key size");
366 session->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE;
368 case RTE_CRYPTO_CIPHER_DES_DOCSISBPI:
369 session->bpi_ctx = bpi_cipher_ctx_init(
372 cipher_xform->key.data);
373 if (session->bpi_ctx == NULL) {
374 PMD_DRV_LOG(ERR, "failed to create DES BPI ctx");
377 if (qat_alg_validate_des_key(cipher_xform->key.length,
378 &session->qat_cipher_alg) != 0) {
379 PMD_DRV_LOG(ERR, "Invalid DES cipher key size");
382 session->qat_mode = ICP_QAT_HW_CIPHER_CBC_MODE;
384 case RTE_CRYPTO_CIPHER_AES_DOCSISBPI:
385 session->bpi_ctx = bpi_cipher_ctx_init(
388 cipher_xform->key.data);
389 if (session->bpi_ctx == NULL) {
390 PMD_DRV_LOG(ERR, "failed to create AES BPI ctx");
393 if (qat_alg_validate_aes_docsisbpi_key(cipher_xform->key.length,
394 &session->qat_cipher_alg) != 0) {
395 PMD_DRV_LOG(ERR, "Invalid AES DOCSISBPI key size");
398 session->qat_mode = ICP_QAT_HW_CIPHER_CBC_MODE;
400 case RTE_CRYPTO_CIPHER_ZUC_EEA3:
401 if (!qat_is_cipher_alg_supported(
402 cipher_xform->algo, internals)) {
403 PMD_DRV_LOG(ERR, "%s not supported on this device",
404 rte_crypto_cipher_algorithm_strings
405 [cipher_xform->algo]);
408 if (qat_alg_validate_zuc_key(cipher_xform->key.length,
409 &session->qat_cipher_alg) != 0) {
410 PMD_DRV_LOG(ERR, "Invalid ZUC cipher key size");
413 session->qat_mode = ICP_QAT_HW_CIPHER_ECB_MODE;
415 case RTE_CRYPTO_CIPHER_3DES_ECB:
416 case RTE_CRYPTO_CIPHER_AES_ECB:
417 case RTE_CRYPTO_CIPHER_AES_CCM:
418 case RTE_CRYPTO_CIPHER_AES_F8:
419 case RTE_CRYPTO_CIPHER_AES_XTS:
420 case RTE_CRYPTO_CIPHER_ARC4:
421 PMD_DRV_LOG(ERR, "Crypto QAT PMD: Unsupported Cipher alg %u",
425 PMD_DRV_LOG(ERR, "Crypto: Undefined Cipher specified %u\n",
430 if (cipher_xform->op == RTE_CRYPTO_CIPHER_OP_ENCRYPT)
431 session->qat_dir = ICP_QAT_HW_CIPHER_ENCRYPT;
433 session->qat_dir = ICP_QAT_HW_CIPHER_DECRYPT;
435 if (qat_alg_aead_session_create_content_desc_cipher(session,
436 cipher_xform->key.data,
437 cipher_xform->key.length))
443 if (session->bpi_ctx) {
444 bpi_cipher_ctx_free(session->bpi_ctx);
445 session->bpi_ctx = NULL;
452 qat_crypto_sym_configure_session(struct rte_cryptodev *dev,
453 struct rte_crypto_sym_xform *xform, void *session_private)
455 struct qat_session *session = session_private;
458 PMD_INIT_FUNC_TRACE();
460 /* Get requested QAT command id */
461 qat_cmd_id = qat_get_cmd_id(xform);
462 if (qat_cmd_id < 0 || qat_cmd_id >= ICP_QAT_FW_LA_CMD_DELIMITER) {
463 PMD_DRV_LOG(ERR, "Unsupported xform chain requested");
466 session->qat_cmd = (enum icp_qat_fw_la_cmd_id)qat_cmd_id;
467 switch (session->qat_cmd) {
468 case ICP_QAT_FW_LA_CMD_CIPHER:
469 session = qat_crypto_sym_configure_session_cipher(dev, xform, session);
471 case ICP_QAT_FW_LA_CMD_AUTH:
472 session = qat_crypto_sym_configure_session_auth(dev, xform, session);
474 case ICP_QAT_FW_LA_CMD_CIPHER_HASH:
475 session = qat_crypto_sym_configure_session_cipher(dev, xform, session);
476 session = qat_crypto_sym_configure_session_auth(dev, xform, session);
478 case ICP_QAT_FW_LA_CMD_HASH_CIPHER:
479 session = qat_crypto_sym_configure_session_auth(dev, xform, session);
480 session = qat_crypto_sym_configure_session_cipher(dev, xform, session);
482 case ICP_QAT_FW_LA_CMD_TRNG_GET_RANDOM:
483 case ICP_QAT_FW_LA_CMD_TRNG_TEST:
484 case ICP_QAT_FW_LA_CMD_SSL3_KEY_DERIVE:
485 case ICP_QAT_FW_LA_CMD_TLS_V1_1_KEY_DERIVE:
486 case ICP_QAT_FW_LA_CMD_TLS_V1_2_KEY_DERIVE:
487 case ICP_QAT_FW_LA_CMD_MGF1:
488 case ICP_QAT_FW_LA_CMD_AUTH_PRE_COMP:
489 case ICP_QAT_FW_LA_CMD_CIPHER_PRE_COMP:
490 case ICP_QAT_FW_LA_CMD_DELIMITER:
491 PMD_DRV_LOG(ERR, "Unsupported Service %u",
495 PMD_DRV_LOG(ERR, "Unsupported Service %u",
507 qat_crypto_sym_configure_session_auth(struct rte_cryptodev *dev,
508 struct rte_crypto_sym_xform *xform,
509 struct qat_session *session_private)
512 struct qat_session *session = session_private;
513 struct rte_crypto_auth_xform *auth_xform = NULL;
514 struct rte_crypto_cipher_xform *cipher_xform = NULL;
515 struct qat_pmd_private *internals = dev->data->dev_private;
516 auth_xform = qat_get_auth_xform(xform);
518 switch (auth_xform->algo) {
519 case RTE_CRYPTO_AUTH_SHA1_HMAC:
520 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA1;
522 case RTE_CRYPTO_AUTH_SHA224_HMAC:
523 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA224;
525 case RTE_CRYPTO_AUTH_SHA256_HMAC:
526 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA256;
528 case RTE_CRYPTO_AUTH_SHA384_HMAC:
529 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA384;
531 case RTE_CRYPTO_AUTH_SHA512_HMAC:
532 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA512;
534 case RTE_CRYPTO_AUTH_AES_XCBC_MAC:
535 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC;
537 case RTE_CRYPTO_AUTH_AES_GCM:
538 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_GALOIS_128;
540 case RTE_CRYPTO_AUTH_AES_GMAC:
541 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_GALOIS_128;
543 case RTE_CRYPTO_AUTH_SNOW3G_UIA2:
544 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2;
546 case RTE_CRYPTO_AUTH_MD5_HMAC:
547 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_MD5;
549 case RTE_CRYPTO_AUTH_NULL:
550 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_NULL;
552 case RTE_CRYPTO_AUTH_KASUMI_F9:
553 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_KASUMI_F9;
555 case RTE_CRYPTO_AUTH_ZUC_EIA3:
556 if (!qat_is_auth_alg_supported(auth_xform->algo, internals)) {
557 PMD_DRV_LOG(ERR, "%s not supported on this device",
558 rte_crypto_auth_algorithm_strings
562 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_ZUC_3G_128_EIA3;
564 case RTE_CRYPTO_AUTH_SHA1:
565 case RTE_CRYPTO_AUTH_SHA256:
566 case RTE_CRYPTO_AUTH_SHA512:
567 case RTE_CRYPTO_AUTH_SHA224:
568 case RTE_CRYPTO_AUTH_SHA384:
569 case RTE_CRYPTO_AUTH_MD5:
570 case RTE_CRYPTO_AUTH_AES_CCM:
571 case RTE_CRYPTO_AUTH_AES_CMAC:
572 case RTE_CRYPTO_AUTH_AES_CBC_MAC:
573 PMD_DRV_LOG(ERR, "Crypto: Unsupported hash alg %u",
577 PMD_DRV_LOG(ERR, "Crypto: Undefined Hash algo %u specified",
581 cipher_xform = qat_get_cipher_xform(xform);
583 if ((session->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_128) ||
584 (session->qat_hash_alg ==
585 ICP_QAT_HW_AUTH_ALGO_GALOIS_64)) {
586 if (qat_alg_aead_session_create_content_desc_auth(session,
587 cipher_xform->key.data,
588 cipher_xform->key.length,
589 auth_xform->add_auth_data_length,
590 auth_xform->digest_length,
594 if (qat_alg_aead_session_create_content_desc_auth(session,
595 auth_xform->key.data,
596 auth_xform->key.length,
597 auth_xform->add_auth_data_length,
598 auth_xform->digest_length,
608 unsigned qat_crypto_sym_get_session_private_size(
609 struct rte_cryptodev *dev __rte_unused)
611 return RTE_ALIGN_CEIL(sizeof(struct qat_session), 8);
614 static inline uint32_t
615 qat_bpicipher_preprocess(struct qat_session *ctx,
616 struct rte_crypto_op *op)
618 uint8_t block_len = qat_cipher_get_block_size(ctx->qat_cipher_alg);
619 struct rte_crypto_sym_op *sym_op = op->sym;
620 uint8_t last_block_len = sym_op->cipher.data.length % block_len;
622 if (last_block_len &&
623 ctx->qat_dir == ICP_QAT_HW_CIPHER_DECRYPT) {
625 /* Decrypt last block */
626 uint8_t *last_block, *dst, *iv;
627 uint32_t last_block_offset = sym_op->cipher.data.offset +
628 sym_op->cipher.data.length - last_block_len;
629 last_block = (uint8_t *) rte_pktmbuf_mtod_offset(sym_op->m_src,
630 uint8_t *, last_block_offset);
632 if (unlikely(sym_op->m_dst != NULL))
633 /* out-of-place operation (OOP) */
634 dst = (uint8_t *) rte_pktmbuf_mtod_offset(sym_op->m_dst,
635 uint8_t *, last_block_offset);
639 if (last_block_len < sym_op->cipher.data.length)
640 /* use previous block ciphertext as IV */
641 iv = last_block - block_len;
643 /* runt block, i.e. less than one full block */
644 iv = sym_op->cipher.iv.data;
646 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX
647 rte_hexdump(stdout, "BPI: src before pre-process:", last_block,
649 if (sym_op->m_dst != NULL)
650 rte_hexdump(stdout, "BPI: dst before pre-process:", dst,
653 bpi_cipher_decrypt(last_block, dst, iv, block_len,
654 last_block_len, ctx->bpi_ctx);
655 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX
656 rte_hexdump(stdout, "BPI: src after pre-process:", last_block,
658 if (sym_op->m_dst != NULL)
659 rte_hexdump(stdout, "BPI: dst after pre-process:", dst,
664 return sym_op->cipher.data.length - last_block_len;
667 static inline uint32_t
668 qat_bpicipher_postprocess(struct qat_session *ctx,
669 struct rte_crypto_op *op)
671 uint8_t block_len = qat_cipher_get_block_size(ctx->qat_cipher_alg);
672 struct rte_crypto_sym_op *sym_op = op->sym;
673 uint8_t last_block_len = sym_op->cipher.data.length % block_len;
675 if (last_block_len > 0 &&
676 ctx->qat_dir == ICP_QAT_HW_CIPHER_ENCRYPT) {
678 /* Encrypt last block */
679 uint8_t *last_block, *dst, *iv;
680 uint32_t last_block_offset;
682 last_block_offset = sym_op->cipher.data.offset +
683 sym_op->cipher.data.length - last_block_len;
684 last_block = (uint8_t *) rte_pktmbuf_mtod_offset(sym_op->m_src,
685 uint8_t *, last_block_offset);
687 if (unlikely(sym_op->m_dst != NULL))
688 /* out-of-place operation (OOP) */
689 dst = (uint8_t *) rte_pktmbuf_mtod_offset(sym_op->m_dst,
690 uint8_t *, last_block_offset);
694 if (last_block_len < sym_op->cipher.data.length)
695 /* use previous block ciphertext as IV */
696 iv = dst - block_len;
698 /* runt block, i.e. less than one full block */
699 iv = sym_op->cipher.iv.data;
701 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_RX
702 rte_hexdump(stdout, "BPI: src before post-process:", last_block,
704 if (sym_op->m_dst != NULL)
705 rte_hexdump(stdout, "BPI: dst before post-process:",
706 dst, last_block_len);
708 bpi_cipher_encrypt(last_block, dst, iv, block_len,
709 last_block_len, ctx->bpi_ctx);
710 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_RX
711 rte_hexdump(stdout, "BPI: src after post-process:", last_block,
713 if (sym_op->m_dst != NULL)
714 rte_hexdump(stdout, "BPI: dst after post-process:", dst,
718 return sym_op->cipher.data.length - last_block_len;
722 qat_pmd_enqueue_op_burst(void *qp, struct rte_crypto_op **ops,
725 register struct qat_queue *queue;
726 struct qat_qp *tmp_qp = (struct qat_qp *)qp;
727 register uint32_t nb_ops_sent = 0;
728 register struct rte_crypto_op **cur_op = ops;
730 uint16_t nb_ops_possible = nb_ops;
731 register uint8_t *base_addr;
732 register uint32_t tail;
735 if (unlikely(nb_ops == 0))
738 /* read params used a lot in main loop into registers */
739 queue = &(tmp_qp->tx_q);
740 base_addr = (uint8_t *)queue->base_addr;
743 /* Find how many can actually fit on the ring */
744 overflow = rte_atomic16_add_return(&tmp_qp->inflights16, nb_ops)
745 - queue->max_inflights;
747 rte_atomic16_sub(&tmp_qp->inflights16, overflow);
748 nb_ops_possible = nb_ops - overflow;
749 if (nb_ops_possible == 0)
753 while (nb_ops_sent != nb_ops_possible) {
754 ret = qat_write_hw_desc_entry(*cur_op, base_addr + tail,
755 tmp_qp->op_cookies[tail / queue->msg_size]);
757 tmp_qp->stats.enqueue_err_count++;
759 * This message cannot be enqueued,
760 * decrease number of ops that wasnt sent
762 rte_atomic16_sub(&tmp_qp->inflights16,
763 nb_ops_possible - nb_ops_sent);
764 if (nb_ops_sent == 0)
769 tail = adf_modulo(tail + queue->msg_size, queue->modulo);
774 WRITE_CSR_RING_TAIL(tmp_qp->mmap_bar_addr, queue->hw_bundle_number,
775 queue->hw_queue_number, tail);
777 tmp_qp->stats.enqueued_count += nb_ops_sent;
782 qat_pmd_dequeue_op_burst(void *qp, struct rte_crypto_op **ops,
785 struct qat_queue *queue;
786 struct qat_qp *tmp_qp = (struct qat_qp *)qp;
787 uint32_t msg_counter = 0;
788 struct rte_crypto_op *rx_op;
789 struct icp_qat_fw_comn_resp *resp_msg;
791 queue = &(tmp_qp->rx_q);
792 resp_msg = (struct icp_qat_fw_comn_resp *)
793 ((uint8_t *)queue->base_addr + queue->head);
795 while (*(uint32_t *)resp_msg != ADF_RING_EMPTY_SIG &&
796 msg_counter != nb_ops) {
797 rx_op = (struct rte_crypto_op *)(uintptr_t)
798 (resp_msg->opaque_data);
800 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_RX
801 rte_hexdump(stdout, "qat_response:", (uint8_t *)resp_msg,
802 sizeof(struct icp_qat_fw_comn_resp));
805 if (ICP_QAT_FW_COMN_STATUS_FLAG_OK !=
806 ICP_QAT_FW_COMN_RESP_CRYPTO_STAT_GET(
807 resp_msg->comn_hdr.comn_status)) {
808 rx_op->status = RTE_CRYPTO_OP_STATUS_AUTH_FAILED;
810 struct qat_session *sess = (struct qat_session *)
811 (rx_op->sym->session->_private);
813 qat_bpicipher_postprocess(sess, rx_op);
814 rx_op->status = RTE_CRYPTO_OP_STATUS_SUCCESS;
817 *(uint32_t *)resp_msg = ADF_RING_EMPTY_SIG;
818 queue->head = adf_modulo(queue->head +
820 ADF_RING_SIZE_MODULO(queue->queue_size));
821 resp_msg = (struct icp_qat_fw_comn_resp *)
822 ((uint8_t *)queue->base_addr +
828 if (msg_counter > 0) {
829 WRITE_CSR_RING_HEAD(tmp_qp->mmap_bar_addr,
830 queue->hw_bundle_number,
831 queue->hw_queue_number, queue->head);
832 rte_atomic16_sub(&tmp_qp->inflights16, msg_counter);
833 tmp_qp->stats.dequeued_count += msg_counter;
839 qat_sgl_fill_array(struct rte_mbuf *buf, uint64_t buff_start,
840 struct qat_alg_buf_list *list, uint32_t data_len)
844 uint32_t buf_len = rte_pktmbuf_mtophys(buf) -
845 buff_start + rte_pktmbuf_data_len(buf);
847 list->bufers[0].addr = buff_start;
848 list->bufers[0].resrvd = 0;
849 list->bufers[0].len = buf_len;
851 if (data_len <= buf_len) {
853 list->bufers[0].len = data_len;
859 if (unlikely(nr == QAT_SGL_MAX_NUMBER)) {
860 PMD_DRV_LOG(ERR, "QAT PMD exceeded size of QAT SGL"
866 list->bufers[nr].len = rte_pktmbuf_data_len(buf);
867 list->bufers[nr].resrvd = 0;
868 list->bufers[nr].addr = rte_pktmbuf_mtophys(buf);
870 buf_len += list->bufers[nr].len;
873 if (buf_len > data_len) {
874 list->bufers[nr].len -=
886 qat_write_hw_desc_entry(struct rte_crypto_op *op, uint8_t *out_msg,
887 struct qat_crypto_op_cookie *qat_op_cookie)
890 struct qat_session *ctx;
891 struct icp_qat_fw_la_cipher_req_params *cipher_param;
892 struct icp_qat_fw_la_auth_req_params *auth_param;
893 register struct icp_qat_fw_la_bulk_req *qat_req;
894 uint8_t do_auth = 0, do_cipher = 0;
895 uint32_t cipher_len = 0, cipher_ofs = 0;
896 uint32_t auth_len = 0, auth_ofs = 0;
897 uint32_t min_ofs = 0;
898 uint64_t src_buf_start = 0, dst_buf_start = 0;
902 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX
903 if (unlikely(op->type != RTE_CRYPTO_OP_TYPE_SYMMETRIC)) {
904 PMD_DRV_LOG(ERR, "QAT PMD only supports symmetric crypto "
905 "operation requests, op (%p) is not a "
906 "symmetric operation.", op);
910 if (unlikely(op->sym->sess_type == RTE_CRYPTO_SYM_OP_SESSIONLESS)) {
911 PMD_DRV_LOG(ERR, "QAT PMD only supports session oriented"
912 " requests, op (%p) is sessionless.", op);
916 if (unlikely(op->sym->session->dev_type != RTE_CRYPTODEV_QAT_SYM_PMD)) {
917 PMD_DRV_LOG(ERR, "Session was not created for this device");
921 ctx = (struct qat_session *)op->sym->session->_private;
922 qat_req = (struct icp_qat_fw_la_bulk_req *)out_msg;
923 rte_mov128((uint8_t *)qat_req, (const uint8_t *)&(ctx->fw_req));
924 qat_req->comn_mid.opaque_data = (uint64_t)(uintptr_t)op;
925 cipher_param = (void *)&qat_req->serv_specif_rqpars;
926 auth_param = (void *)((uint8_t *)cipher_param + sizeof(*cipher_param));
928 if (ctx->qat_cmd == ICP_QAT_FW_LA_CMD_HASH_CIPHER ||
929 ctx->qat_cmd == ICP_QAT_FW_LA_CMD_CIPHER_HASH) {
932 } else if (ctx->qat_cmd == ICP_QAT_FW_LA_CMD_AUTH) {
935 } else if (ctx->qat_cmd == ICP_QAT_FW_LA_CMD_CIPHER) {
942 if (ctx->qat_cipher_alg ==
943 ICP_QAT_HW_CIPHER_ALGO_SNOW_3G_UEA2 ||
944 ctx->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_KASUMI ||
945 ctx->qat_cipher_alg ==
946 ICP_QAT_HW_CIPHER_ALGO_ZUC_3G_128_EEA3) {
949 (cipher_param->cipher_length % BYTE_LENGTH != 0)
950 || (cipher_param->cipher_offset
951 % BYTE_LENGTH != 0))) {
953 "SNOW3G/KASUMI/ZUC in QAT PMD only supports byte aligned values");
954 op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
957 cipher_len = op->sym->cipher.data.length >> 3;
958 cipher_ofs = op->sym->cipher.data.offset >> 3;
960 } else if (ctx->bpi_ctx) {
961 /* DOCSIS - only send complete blocks to device
962 * Process any partial block using CFB mode.
963 * Even if 0 complete blocks, still send this to device
964 * to get into rx queue for post-process and dequeuing
966 cipher_len = qat_bpicipher_preprocess(ctx, op);
967 cipher_ofs = op->sym->cipher.data.offset;
969 cipher_len = op->sym->cipher.data.length;
970 cipher_ofs = op->sym->cipher.data.offset;
973 /* copy IV into request if it fits */
975 * If IV length is zero do not copy anything but still
976 * use request descriptor embedded IV
979 if (op->sym->cipher.iv.length) {
980 if (op->sym->cipher.iv.length <=
981 sizeof(cipher_param->u.cipher_IV_array)) {
982 rte_memcpy(cipher_param->u.cipher_IV_array,
983 op->sym->cipher.iv.data,
984 op->sym->cipher.iv.length);
986 ICP_QAT_FW_LA_CIPH_IV_FLD_FLAG_SET(
987 qat_req->comn_hdr.serv_specif_flags,
988 ICP_QAT_FW_CIPH_IV_64BIT_PTR);
989 cipher_param->u.s.cipher_IV_ptr =
990 op->sym->cipher.iv.phys_addr;
993 min_ofs = cipher_ofs;
998 if (ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2 ||
999 ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_KASUMI_F9 ||
1000 ctx->qat_hash_alg ==
1001 ICP_QAT_HW_AUTH_ALGO_ZUC_3G_128_EIA3) {
1002 if (unlikely((auth_param->auth_off % BYTE_LENGTH != 0)
1003 || (auth_param->auth_len % BYTE_LENGTH != 0))) {
1005 "For SNOW3G/KASUMI/ZUC, QAT PMD only supports byte aligned values");
1006 op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
1009 auth_ofs = op->sym->auth.data.offset >> 3;
1010 auth_len = op->sym->auth.data.length >> 3;
1012 if (ctx->qat_hash_alg ==
1013 ICP_QAT_HW_AUTH_ALGO_KASUMI_F9) {
1015 auth_len = auth_len + auth_ofs + 1 -
1016 ICP_QAT_HW_KASUMI_BLK_SZ;
1017 auth_ofs = ICP_QAT_HW_KASUMI_BLK_SZ;
1019 auth_len = auth_len + auth_ofs + 1;
1024 } else if (ctx->qat_hash_alg ==
1025 ICP_QAT_HW_AUTH_ALGO_GALOIS_128 ||
1026 ctx->qat_hash_alg ==
1027 ICP_QAT_HW_AUTH_ALGO_GALOIS_64) {
1028 auth_ofs = op->sym->cipher.data.offset;
1029 auth_len = op->sym->cipher.data.length;
1031 auth_ofs = op->sym->auth.data.offset;
1032 auth_len = op->sym->auth.data.length;
1036 auth_param->auth_res_addr = op->sym->auth.digest.phys_addr;
1038 auth_param->u1.aad_adr = op->sym->auth.aad.phys_addr;
1042 if (op->sym->m_src->next || (op->sym->m_dst && op->sym->m_dst->next))
1045 /* adjust for chain case */
1046 if (do_cipher && do_auth)
1047 min_ofs = cipher_ofs < auth_ofs ? cipher_ofs : auth_ofs;
1049 if (unlikely(min_ofs >= rte_pktmbuf_data_len(op->sym->m_src) && do_sgl))
1052 if (unlikely(op->sym->m_dst != NULL)) {
1053 /* Out-of-place operation (OOP)
1054 * Don't align DMA start. DMA the minimum data-set
1055 * so as not to overwrite data in dest buffer
1058 rte_pktmbuf_mtophys_offset(op->sym->m_src, min_ofs);
1060 rte_pktmbuf_mtophys_offset(op->sym->m_dst, min_ofs);
1063 /* In-place operation
1064 * Start DMA at nearest aligned address below min_ofs
1067 rte_pktmbuf_mtophys_offset(op->sym->m_src, min_ofs)
1068 & QAT_64_BTYE_ALIGN_MASK;
1070 if (unlikely((rte_pktmbuf_mtophys(op->sym->m_src) -
1071 rte_pktmbuf_headroom(op->sym->m_src))
1073 /* alignment has pushed addr ahead of start of mbuf
1074 * so revert and take the performance hit
1077 rte_pktmbuf_mtophys_offset(op->sym->m_src,
1080 dst_buf_start = src_buf_start;
1084 cipher_param->cipher_offset =
1085 (uint32_t)rte_pktmbuf_mtophys_offset(
1086 op->sym->m_src, cipher_ofs) - src_buf_start;
1087 cipher_param->cipher_length = cipher_len;
1089 cipher_param->cipher_offset = 0;
1090 cipher_param->cipher_length = 0;
1093 auth_param->auth_off = (uint32_t)rte_pktmbuf_mtophys_offset(
1094 op->sym->m_src, auth_ofs) - src_buf_start;
1095 auth_param->auth_len = auth_len;
1097 auth_param->auth_off = 0;
1098 auth_param->auth_len = 0;
1100 qat_req->comn_mid.dst_length =
1101 qat_req->comn_mid.src_length =
1102 (cipher_param->cipher_offset + cipher_param->cipher_length)
1103 > (auth_param->auth_off + auth_param->auth_len) ?
1104 (cipher_param->cipher_offset + cipher_param->cipher_length)
1105 : (auth_param->auth_off + auth_param->auth_len);
1109 ICP_QAT_FW_COMN_PTR_TYPE_SET(qat_req->comn_hdr.comn_req_flags,
1110 QAT_COMN_PTR_TYPE_SGL);
1111 ret = qat_sgl_fill_array(op->sym->m_src, src_buf_start,
1112 &qat_op_cookie->qat_sgl_list_src,
1113 qat_req->comn_mid.src_length);
1115 PMD_DRV_LOG(ERR, "QAT PMD Cannot fill sgl array");
1119 if (likely(op->sym->m_dst == NULL))
1120 qat_req->comn_mid.dest_data_addr =
1121 qat_req->comn_mid.src_data_addr =
1122 qat_op_cookie->qat_sgl_src_phys_addr;
1124 ret = qat_sgl_fill_array(op->sym->m_dst,
1126 &qat_op_cookie->qat_sgl_list_dst,
1127 qat_req->comn_mid.dst_length);
1130 PMD_DRV_LOG(ERR, "QAT PMD Cannot "
1135 qat_req->comn_mid.src_data_addr =
1136 qat_op_cookie->qat_sgl_src_phys_addr;
1137 qat_req->comn_mid.dest_data_addr =
1138 qat_op_cookie->qat_sgl_dst_phys_addr;
1141 qat_req->comn_mid.src_data_addr = src_buf_start;
1142 qat_req->comn_mid.dest_data_addr = dst_buf_start;
1145 if (ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_128 ||
1146 ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_64) {
1147 if (op->sym->cipher.iv.length == 12) {
1149 * For GCM a 12 bit IV is allowed,
1150 * but we need to inform the f/w
1152 ICP_QAT_FW_LA_GCM_IV_LEN_FLAG_SET(
1153 qat_req->comn_hdr.serv_specif_flags,
1154 ICP_QAT_FW_LA_GCM_IV_LEN_12_OCTETS);
1156 if (op->sym->cipher.data.length == 0) {
1160 qat_req->comn_mid.dest_data_addr =
1161 qat_req->comn_mid.src_data_addr =
1162 op->sym->auth.aad.phys_addr;
1163 qat_req->comn_mid.dst_length =
1164 qat_req->comn_mid.src_length =
1165 rte_pktmbuf_data_len(op->sym->m_src);
1166 cipher_param->cipher_length = 0;
1167 cipher_param->cipher_offset = 0;
1168 auth_param->u1.aad_adr = 0;
1169 auth_param->auth_len = op->sym->auth.aad.length;
1170 auth_param->auth_off = op->sym->auth.data.offset;
1171 auth_param->u2.aad_sz = 0;
1175 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX
1176 rte_hexdump(stdout, "qat_req:", qat_req,
1177 sizeof(struct icp_qat_fw_la_bulk_req));
1178 rte_hexdump(stdout, "src_data:",
1179 rte_pktmbuf_mtod(op->sym->m_src, uint8_t*),
1180 rte_pktmbuf_data_len(op->sym->m_src));
1181 rte_hexdump(stdout, "iv:", op->sym->cipher.iv.data,
1182 op->sym->cipher.iv.length);
1183 rte_hexdump(stdout, "digest:", op->sym->auth.digest.data,
1184 op->sym->auth.digest.length);
1185 rte_hexdump(stdout, "aad:", op->sym->auth.aad.data,
1186 op->sym->auth.aad.length);
1191 static inline uint32_t adf_modulo(uint32_t data, uint32_t shift)
1193 uint32_t div = data >> shift;
1194 uint32_t mult = div << shift;
1199 void qat_crypto_sym_session_init(struct rte_mempool *mp, void *sym_sess)
1201 struct rte_cryptodev_sym_session *sess = sym_sess;
1202 struct qat_session *s = (void *)sess->_private;
1204 PMD_INIT_FUNC_TRACE();
1205 s->cd_paddr = rte_mempool_virt2phy(mp, sess) +
1206 offsetof(struct qat_session, cd) +
1207 offsetof(struct rte_cryptodev_sym_session, _private);
1210 int qat_dev_config(__rte_unused struct rte_cryptodev *dev,
1211 __rte_unused struct rte_cryptodev_config *config)
1213 PMD_INIT_FUNC_TRACE();
1217 int qat_dev_start(__rte_unused struct rte_cryptodev *dev)
1219 PMD_INIT_FUNC_TRACE();
1223 void qat_dev_stop(__rte_unused struct rte_cryptodev *dev)
1225 PMD_INIT_FUNC_TRACE();
1228 int qat_dev_close(struct rte_cryptodev *dev)
1232 PMD_INIT_FUNC_TRACE();
1234 for (i = 0; i < dev->data->nb_queue_pairs; i++) {
1235 ret = qat_crypto_sym_qp_release(dev, i);
1243 void qat_dev_info_get(__rte_unused struct rte_cryptodev *dev,
1244 struct rte_cryptodev_info *info)
1246 struct qat_pmd_private *internals = dev->data->dev_private;
1248 PMD_INIT_FUNC_TRACE();
1250 info->max_nb_queue_pairs =
1251 ADF_NUM_SYM_QPS_PER_BUNDLE *
1252 ADF_NUM_BUNDLES_PER_DEV;
1253 info->feature_flags = dev->feature_flags;
1254 info->capabilities = internals->qat_dev_capabilities;
1255 info->sym.max_nb_sessions = internals->max_nb_sessions;
1256 info->dev_type = RTE_CRYPTODEV_QAT_SYM_PMD;
1260 void qat_crypto_sym_stats_get(struct rte_cryptodev *dev,
1261 struct rte_cryptodev_stats *stats)
1264 struct qat_qp **qp = (struct qat_qp **)(dev->data->queue_pairs);
1266 PMD_INIT_FUNC_TRACE();
1267 if (stats == NULL) {
1268 PMD_DRV_LOG(ERR, "invalid stats ptr NULL");
1271 for (i = 0; i < dev->data->nb_queue_pairs; i++) {
1272 if (qp[i] == NULL) {
1273 PMD_DRV_LOG(DEBUG, "Uninitialised queue pair");
1277 stats->enqueued_count += qp[i]->stats.enqueued_count;
1278 stats->dequeued_count += qp[i]->stats.dequeued_count;
1279 stats->enqueue_err_count += qp[i]->stats.enqueue_err_count;
1280 stats->dequeue_err_count += qp[i]->stats.dequeue_err_count;
1284 void qat_crypto_sym_stats_reset(struct rte_cryptodev *dev)
1287 struct qat_qp **qp = (struct qat_qp **)(dev->data->queue_pairs);
1289 PMD_INIT_FUNC_TRACE();
1290 for (i = 0; i < dev->data->nb_queue_pairs; i++)
1291 memset(&(qp[i]->stats), 0, sizeof(qp[i]->stats));
1292 PMD_DRV_LOG(DEBUG, "QAT crypto: stats cleared");