4 * Copyright(c) 2015-2017 Intel Corporation. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 #include <sys/queue.h>
43 #include <rte_common.h>
45 #include <rte_debug.h>
46 #include <rte_memory.h>
47 #include <rte_memzone.h>
48 #include <rte_tailq.h>
49 #include <rte_ether.h>
50 #include <rte_malloc.h>
51 #include <rte_launch.h>
53 #include <rte_per_lcore.h>
54 #include <rte_lcore.h>
55 #include <rte_atomic.h>
56 #include <rte_branch_prediction.h>
57 #include <rte_mempool.h>
59 #include <rte_string_fns.h>
60 #include <rte_spinlock.h>
61 #include <rte_hexdump.h>
62 #include <rte_crypto_sym.h>
63 #include <rte_cryptodev_pci.h>
64 #include <openssl/evp.h>
68 #include "qat_crypto.h"
69 #include "adf_transport_access_macros.h"
74 qat_is_cipher_alg_supported(enum rte_crypto_cipher_algorithm algo,
75 struct qat_pmd_private *internals) {
77 const struct rte_cryptodev_capabilities *capability;
79 while ((capability = &(internals->qat_dev_capabilities[i++]))->op !=
80 RTE_CRYPTO_OP_TYPE_UNDEFINED) {
81 if (capability->op != RTE_CRYPTO_OP_TYPE_SYMMETRIC)
84 if (capability->sym.xform_type != RTE_CRYPTO_SYM_XFORM_CIPHER)
87 if (capability->sym.cipher.algo == algo)
94 qat_is_auth_alg_supported(enum rte_crypto_auth_algorithm algo,
95 struct qat_pmd_private *internals) {
97 const struct rte_cryptodev_capabilities *capability;
99 while ((capability = &(internals->qat_dev_capabilities[i++]))->op !=
100 RTE_CRYPTO_OP_TYPE_UNDEFINED) {
101 if (capability->op != RTE_CRYPTO_OP_TYPE_SYMMETRIC)
104 if (capability->sym.xform_type != RTE_CRYPTO_SYM_XFORM_AUTH)
107 if (capability->sym.auth.algo == algo)
113 /** Encrypt a single partial block
114 * Depends on openssl libcrypto
115 * Uses ECB+XOR to do CFB encryption, same result, more performant
118 bpi_cipher_encrypt(uint8_t *src, uint8_t *dst,
119 uint8_t *iv, int ivlen, int srclen,
122 EVP_CIPHER_CTX *ctx = (EVP_CIPHER_CTX *)bpi_ctx;
124 uint8_t encrypted_iv[16];
127 /* ECB method: encrypt the IV, then XOR this with plaintext */
128 if (EVP_EncryptUpdate(ctx, encrypted_iv, &encrypted_ivlen, iv, ivlen)
130 goto cipher_encrypt_err;
132 for (i = 0; i < srclen; i++)
133 *(dst+i) = *(src+i)^(encrypted_iv[i]);
138 PMD_DRV_LOG(ERR, "libcrypto ECB cipher encrypt failed");
142 /** Decrypt a single partial block
143 * Depends on openssl libcrypto
144 * Uses ECB+XOR to do CFB encryption, same result, more performant
147 bpi_cipher_decrypt(uint8_t *src, uint8_t *dst,
148 uint8_t *iv, int ivlen, int srclen,
151 EVP_CIPHER_CTX *ctx = (EVP_CIPHER_CTX *)bpi_ctx;
153 uint8_t encrypted_iv[16];
156 /* ECB method: encrypt (not decrypt!) the IV, then XOR with plaintext */
157 if (EVP_EncryptUpdate(ctx, encrypted_iv, &encrypted_ivlen, iv, ivlen)
159 goto cipher_decrypt_err;
161 for (i = 0; i < srclen; i++)
162 *(dst+i) = *(src+i)^(encrypted_iv[i]);
167 PMD_DRV_LOG(ERR, "libcrypto ECB cipher encrypt for BPI IV failed");
171 /** Creates a context in either AES or DES in ECB mode
172 * Depends on openssl libcrypto
175 bpi_cipher_ctx_init(enum rte_crypto_cipher_algorithm cryptodev_algo,
176 enum rte_crypto_cipher_operation direction __rte_unused,
179 const EVP_CIPHER *algo = NULL;
180 EVP_CIPHER_CTX *ctx = EVP_CIPHER_CTX_new();
185 if (cryptodev_algo == RTE_CRYPTO_CIPHER_DES_DOCSISBPI)
186 algo = EVP_des_ecb();
188 algo = EVP_aes_128_ecb();
190 /* IV will be ECB encrypted whether direction is encrypt or decrypt*/
191 if (EVP_EncryptInit_ex(ctx, algo, NULL, key, 0) != 1)
198 EVP_CIPHER_CTX_free(ctx);
202 /** Frees a context previously created
203 * Depends on openssl libcrypto
206 bpi_cipher_ctx_free(void *bpi_ctx)
209 EVP_CIPHER_CTX_free((EVP_CIPHER_CTX *)bpi_ctx);
212 static inline uint32_t
213 adf_modulo(uint32_t data, uint32_t shift);
216 qat_write_hw_desc_entry(struct rte_crypto_op *op, uint8_t *out_msg,
217 struct qat_crypto_op_cookie *qat_op_cookie);
220 qat_crypto_sym_clear_session(struct rte_cryptodev *dev,
221 struct rte_cryptodev_sym_session *sess)
223 PMD_INIT_FUNC_TRACE();
224 uint8_t index = dev->driver_id;
225 void *sess_priv = get_session_private_data(sess, index);
226 struct qat_session *s = (struct qat_session *)sess_priv;
230 bpi_cipher_ctx_free(s->bpi_ctx);
231 memset(s, 0, qat_crypto_sym_get_session_private_size(dev));
232 struct rte_mempool *sess_mp = rte_mempool_from_obj(sess_priv);
233 set_session_private_data(sess, index, NULL);
234 rte_mempool_put(sess_mp, sess_priv);
239 qat_get_cmd_id(const struct rte_crypto_sym_xform *xform)
242 if (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER && xform->next == NULL)
243 return ICP_QAT_FW_LA_CMD_CIPHER;
245 /* Authentication Only */
246 if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH && xform->next == NULL)
247 return ICP_QAT_FW_LA_CMD_AUTH;
250 if (xform->type == RTE_CRYPTO_SYM_XFORM_AEAD) {
251 if (xform->aead.op == RTE_CRYPTO_AEAD_OP_ENCRYPT)
252 return ICP_QAT_FW_LA_CMD_CIPHER_HASH;
254 return ICP_QAT_FW_LA_CMD_HASH_CIPHER;
257 if (xform->next == NULL)
260 /* Cipher then Authenticate */
261 if (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER &&
262 xform->next->type == RTE_CRYPTO_SYM_XFORM_AUTH)
263 return ICP_QAT_FW_LA_CMD_CIPHER_HASH;
265 /* Authenticate then Cipher */
266 if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH &&
267 xform->next->type == RTE_CRYPTO_SYM_XFORM_CIPHER)
268 return ICP_QAT_FW_LA_CMD_HASH_CIPHER;
273 static struct rte_crypto_auth_xform *
274 qat_get_auth_xform(struct rte_crypto_sym_xform *xform)
277 if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH)
286 static struct rte_crypto_cipher_xform *
287 qat_get_cipher_xform(struct rte_crypto_sym_xform *xform)
290 if (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER)
291 return &xform->cipher;
299 qat_crypto_sym_configure_session_cipher(struct rte_cryptodev *dev,
300 struct rte_crypto_sym_xform *xform, void *session_private)
302 struct qat_session *session = session_private;
303 struct qat_pmd_private *internals = dev->data->dev_private;
304 struct rte_crypto_cipher_xform *cipher_xform = NULL;
306 /* Get cipher xform from crypto xform chain */
307 cipher_xform = qat_get_cipher_xform(xform);
309 session->cipher_iv.offset = cipher_xform->iv.offset;
310 session->cipher_iv.length = cipher_xform->iv.length;
312 switch (cipher_xform->algo) {
313 case RTE_CRYPTO_CIPHER_AES_CBC:
314 if (qat_alg_validate_aes_key(cipher_xform->key.length,
315 &session->qat_cipher_alg) != 0) {
316 PMD_DRV_LOG(ERR, "Invalid AES cipher key size");
319 session->qat_mode = ICP_QAT_HW_CIPHER_CBC_MODE;
321 case RTE_CRYPTO_CIPHER_AES_CTR:
322 if (qat_alg_validate_aes_key(cipher_xform->key.length,
323 &session->qat_cipher_alg) != 0) {
324 PMD_DRV_LOG(ERR, "Invalid AES cipher key size");
327 session->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE;
329 case RTE_CRYPTO_CIPHER_SNOW3G_UEA2:
330 if (qat_alg_validate_snow3g_key(cipher_xform->key.length,
331 &session->qat_cipher_alg) != 0) {
332 PMD_DRV_LOG(ERR, "Invalid SNOW 3G cipher key size");
335 session->qat_mode = ICP_QAT_HW_CIPHER_ECB_MODE;
337 case RTE_CRYPTO_CIPHER_NULL:
338 session->qat_mode = ICP_QAT_HW_CIPHER_ECB_MODE;
340 case RTE_CRYPTO_CIPHER_KASUMI_F8:
341 if (qat_alg_validate_kasumi_key(cipher_xform->key.length,
342 &session->qat_cipher_alg) != 0) {
343 PMD_DRV_LOG(ERR, "Invalid KASUMI cipher key size");
346 session->qat_mode = ICP_QAT_HW_CIPHER_F8_MODE;
348 case RTE_CRYPTO_CIPHER_3DES_CBC:
349 if (qat_alg_validate_3des_key(cipher_xform->key.length,
350 &session->qat_cipher_alg) != 0) {
351 PMD_DRV_LOG(ERR, "Invalid 3DES cipher key size");
354 session->qat_mode = ICP_QAT_HW_CIPHER_CBC_MODE;
356 case RTE_CRYPTO_CIPHER_DES_CBC:
357 if (qat_alg_validate_des_key(cipher_xform->key.length,
358 &session->qat_cipher_alg) != 0) {
359 PMD_DRV_LOG(ERR, "Invalid DES cipher key size");
362 session->qat_mode = ICP_QAT_HW_CIPHER_CBC_MODE;
364 case RTE_CRYPTO_CIPHER_3DES_CTR:
365 if (qat_alg_validate_3des_key(cipher_xform->key.length,
366 &session->qat_cipher_alg) != 0) {
367 PMD_DRV_LOG(ERR, "Invalid 3DES cipher key size");
370 session->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE;
372 case RTE_CRYPTO_CIPHER_DES_DOCSISBPI:
373 session->bpi_ctx = bpi_cipher_ctx_init(
376 cipher_xform->key.data);
377 if (session->bpi_ctx == NULL) {
378 PMD_DRV_LOG(ERR, "failed to create DES BPI ctx");
381 if (qat_alg_validate_des_key(cipher_xform->key.length,
382 &session->qat_cipher_alg) != 0) {
383 PMD_DRV_LOG(ERR, "Invalid DES cipher key size");
386 session->qat_mode = ICP_QAT_HW_CIPHER_CBC_MODE;
388 case RTE_CRYPTO_CIPHER_AES_DOCSISBPI:
389 session->bpi_ctx = bpi_cipher_ctx_init(
392 cipher_xform->key.data);
393 if (session->bpi_ctx == NULL) {
394 PMD_DRV_LOG(ERR, "failed to create AES BPI ctx");
397 if (qat_alg_validate_aes_docsisbpi_key(cipher_xform->key.length,
398 &session->qat_cipher_alg) != 0) {
399 PMD_DRV_LOG(ERR, "Invalid AES DOCSISBPI key size");
402 session->qat_mode = ICP_QAT_HW_CIPHER_CBC_MODE;
404 case RTE_CRYPTO_CIPHER_ZUC_EEA3:
405 if (!qat_is_cipher_alg_supported(
406 cipher_xform->algo, internals)) {
407 PMD_DRV_LOG(ERR, "%s not supported on this device",
408 rte_crypto_cipher_algorithm_strings
409 [cipher_xform->algo]);
412 if (qat_alg_validate_zuc_key(cipher_xform->key.length,
413 &session->qat_cipher_alg) != 0) {
414 PMD_DRV_LOG(ERR, "Invalid ZUC cipher key size");
417 session->qat_mode = ICP_QAT_HW_CIPHER_ECB_MODE;
419 case RTE_CRYPTO_CIPHER_3DES_ECB:
420 case RTE_CRYPTO_CIPHER_AES_ECB:
421 case RTE_CRYPTO_CIPHER_AES_F8:
422 case RTE_CRYPTO_CIPHER_AES_XTS:
423 case RTE_CRYPTO_CIPHER_ARC4:
424 PMD_DRV_LOG(ERR, "Crypto QAT PMD: Unsupported Cipher alg %u",
428 PMD_DRV_LOG(ERR, "Crypto: Undefined Cipher specified %u\n",
433 if (cipher_xform->op == RTE_CRYPTO_CIPHER_OP_ENCRYPT)
434 session->qat_dir = ICP_QAT_HW_CIPHER_ENCRYPT;
436 session->qat_dir = ICP_QAT_HW_CIPHER_DECRYPT;
438 if (qat_alg_aead_session_create_content_desc_cipher(session,
439 cipher_xform->key.data,
440 cipher_xform->key.length))
446 if (session->bpi_ctx) {
447 bpi_cipher_ctx_free(session->bpi_ctx);
448 session->bpi_ctx = NULL;
454 qat_crypto_sym_configure_session(struct rte_cryptodev *dev,
455 struct rte_crypto_sym_xform *xform,
456 struct rte_cryptodev_sym_session *sess,
457 struct rte_mempool *mempool)
459 void *sess_private_data;
461 if (rte_mempool_get(mempool, &sess_private_data)) {
463 "Couldn't get object from session mempool");
467 if (qat_crypto_set_session_parameters(dev, xform, sess_private_data) != 0) {
468 PMD_DRV_LOG(ERR, "Crypto QAT PMD: failed to configure "
469 "session parameters");
471 /* Return session to mempool */
472 rte_mempool_put(mempool, sess_private_data);
476 set_session_private_data(sess, dev->driver_id,
483 qat_crypto_set_session_parameters(struct rte_cryptodev *dev,
484 struct rte_crypto_sym_xform *xform, void *session_private)
486 struct qat_session *session = session_private;
489 PMD_INIT_FUNC_TRACE();
491 /* Set context descriptor physical address */
492 session->cd_paddr = rte_mempool_virt2phy(NULL, session) +
493 offsetof(struct qat_session, cd);
495 /* Get requested QAT command id */
496 qat_cmd_id = qat_get_cmd_id(xform);
497 if (qat_cmd_id < 0 || qat_cmd_id >= ICP_QAT_FW_LA_CMD_DELIMITER) {
498 PMD_DRV_LOG(ERR, "Unsupported xform chain requested");
501 session->qat_cmd = (enum icp_qat_fw_la_cmd_id)qat_cmd_id;
502 switch (session->qat_cmd) {
503 case ICP_QAT_FW_LA_CMD_CIPHER:
504 session = qat_crypto_sym_configure_session_cipher(dev, xform, session);
506 case ICP_QAT_FW_LA_CMD_AUTH:
507 session = qat_crypto_sym_configure_session_auth(dev, xform, session);
509 case ICP_QAT_FW_LA_CMD_CIPHER_HASH:
510 if (xform->type == RTE_CRYPTO_SYM_XFORM_AEAD)
511 session = qat_crypto_sym_configure_session_aead(xform,
514 session = qat_crypto_sym_configure_session_cipher(dev,
516 session = qat_crypto_sym_configure_session_auth(dev,
520 case ICP_QAT_FW_LA_CMD_HASH_CIPHER:
521 if (xform->type == RTE_CRYPTO_SYM_XFORM_AEAD)
522 session = qat_crypto_sym_configure_session_aead(xform,
525 session = qat_crypto_sym_configure_session_auth(dev,
527 session = qat_crypto_sym_configure_session_cipher(dev,
531 case ICP_QAT_FW_LA_CMD_TRNG_GET_RANDOM:
532 case ICP_QAT_FW_LA_CMD_TRNG_TEST:
533 case ICP_QAT_FW_LA_CMD_SSL3_KEY_DERIVE:
534 case ICP_QAT_FW_LA_CMD_TLS_V1_1_KEY_DERIVE:
535 case ICP_QAT_FW_LA_CMD_TLS_V1_2_KEY_DERIVE:
536 case ICP_QAT_FW_LA_CMD_MGF1:
537 case ICP_QAT_FW_LA_CMD_AUTH_PRE_COMP:
538 case ICP_QAT_FW_LA_CMD_CIPHER_PRE_COMP:
539 case ICP_QAT_FW_LA_CMD_DELIMITER:
540 PMD_DRV_LOG(ERR, "Unsupported Service %u",
544 PMD_DRV_LOG(ERR, "Unsupported Service %u",
556 qat_crypto_sym_configure_session_auth(struct rte_cryptodev *dev,
557 struct rte_crypto_sym_xform *xform,
558 struct qat_session *session_private)
561 struct qat_session *session = session_private;
562 struct rte_crypto_auth_xform *auth_xform = NULL;
563 struct qat_pmd_private *internals = dev->data->dev_private;
564 auth_xform = qat_get_auth_xform(xform);
565 uint8_t *key_data = auth_xform->key.data;
566 uint8_t key_length = auth_xform->key.length;
568 switch (auth_xform->algo) {
569 case RTE_CRYPTO_AUTH_SHA1_HMAC:
570 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA1;
572 case RTE_CRYPTO_AUTH_SHA224_HMAC:
573 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA224;
575 case RTE_CRYPTO_AUTH_SHA256_HMAC:
576 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA256;
578 case RTE_CRYPTO_AUTH_SHA384_HMAC:
579 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA384;
581 case RTE_CRYPTO_AUTH_SHA512_HMAC:
582 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA512;
584 case RTE_CRYPTO_AUTH_AES_XCBC_MAC:
585 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC;
587 case RTE_CRYPTO_AUTH_AES_GMAC:
588 if (qat_alg_validate_aes_key(auth_xform->key.length,
589 &session->qat_cipher_alg) != 0) {
590 PMD_DRV_LOG(ERR, "Invalid AES key size");
593 session->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE;
594 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_GALOIS_128;
597 case RTE_CRYPTO_AUTH_SNOW3G_UIA2:
598 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2;
600 case RTE_CRYPTO_AUTH_MD5_HMAC:
601 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_MD5;
603 case RTE_CRYPTO_AUTH_NULL:
604 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_NULL;
606 case RTE_CRYPTO_AUTH_KASUMI_F9:
607 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_KASUMI_F9;
609 case RTE_CRYPTO_AUTH_ZUC_EIA3:
610 if (!qat_is_auth_alg_supported(auth_xform->algo, internals)) {
611 PMD_DRV_LOG(ERR, "%s not supported on this device",
612 rte_crypto_auth_algorithm_strings
616 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_ZUC_3G_128_EIA3;
618 case RTE_CRYPTO_AUTH_SHA1:
619 case RTE_CRYPTO_AUTH_SHA256:
620 case RTE_CRYPTO_AUTH_SHA512:
621 case RTE_CRYPTO_AUTH_SHA224:
622 case RTE_CRYPTO_AUTH_SHA384:
623 case RTE_CRYPTO_AUTH_MD5:
624 case RTE_CRYPTO_AUTH_AES_CMAC:
625 case RTE_CRYPTO_AUTH_AES_CBC_MAC:
626 PMD_DRV_LOG(ERR, "Crypto: Unsupported hash alg %u",
630 PMD_DRV_LOG(ERR, "Crypto: Undefined Hash algo %u specified",
635 session->auth_iv.offset = auth_xform->iv.offset;
636 session->auth_iv.length = auth_xform->iv.length;
638 if (auth_xform->algo == RTE_CRYPTO_AUTH_AES_GMAC) {
639 if (auth_xform->op == RTE_CRYPTO_AUTH_OP_GENERATE) {
640 session->qat_cmd = ICP_QAT_FW_LA_CMD_CIPHER_HASH;
641 session->qat_dir = ICP_QAT_HW_CIPHER_ENCRYPT;
643 * It needs to create cipher desc content first,
644 * then authentication
646 if (qat_alg_aead_session_create_content_desc_cipher(session,
647 auth_xform->key.data,
648 auth_xform->key.length))
651 if (qat_alg_aead_session_create_content_desc_auth(session,
655 auth_xform->digest_length,
659 session->qat_cmd = ICP_QAT_FW_LA_CMD_HASH_CIPHER;
660 session->qat_dir = ICP_QAT_HW_CIPHER_DECRYPT;
662 * It needs to create authentication desc content first,
665 if (qat_alg_aead_session_create_content_desc_auth(session,
669 auth_xform->digest_length,
673 if (qat_alg_aead_session_create_content_desc_cipher(session,
674 auth_xform->key.data,
675 auth_xform->key.length))
678 /* Restore to authentication only only */
679 session->qat_cmd = ICP_QAT_FW_LA_CMD_AUTH;
681 if (qat_alg_aead_session_create_content_desc_auth(session,
685 auth_xform->digest_length,
690 session->digest_length = auth_xform->digest_length;
698 qat_crypto_sym_configure_session_aead(struct rte_crypto_sym_xform *xform,
699 struct qat_session *session_private)
701 struct qat_session *session = session_private;
702 struct rte_crypto_aead_xform *aead_xform = &xform->aead;
705 * Store AEAD IV parameters as cipher IV,
706 * to avoid unnecessary memory usage
708 session->cipher_iv.offset = xform->aead.iv.offset;
709 session->cipher_iv.length = xform->aead.iv.length;
711 switch (aead_xform->algo) {
712 case RTE_CRYPTO_AEAD_AES_GCM:
713 if (qat_alg_validate_aes_key(aead_xform->key.length,
714 &session->qat_cipher_alg) != 0) {
715 PMD_DRV_LOG(ERR, "Invalid AES key size");
718 session->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE;
719 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_GALOIS_128;
721 case RTE_CRYPTO_AEAD_AES_CCM:
722 PMD_DRV_LOG(ERR, "Crypto QAT PMD: Unsupported AEAD alg %u",
726 PMD_DRV_LOG(ERR, "Crypto: Undefined AEAD specified %u\n",
731 if (aead_xform->op == RTE_CRYPTO_AEAD_OP_ENCRYPT) {
732 session->qat_dir = ICP_QAT_HW_CIPHER_ENCRYPT;
734 * It needs to create cipher desc content first,
735 * then authentication
737 if (qat_alg_aead_session_create_content_desc_cipher(session,
738 aead_xform->key.data,
739 aead_xform->key.length))
742 if (qat_alg_aead_session_create_content_desc_auth(session,
743 aead_xform->key.data,
744 aead_xform->key.length,
745 aead_xform->add_auth_data_length,
746 aead_xform->digest_length,
747 RTE_CRYPTO_AUTH_OP_GENERATE))
750 session->qat_dir = ICP_QAT_HW_CIPHER_DECRYPT;
752 * It needs to create authentication desc content first,
755 if (qat_alg_aead_session_create_content_desc_auth(session,
756 aead_xform->key.data,
757 aead_xform->key.length,
758 aead_xform->add_auth_data_length,
759 aead_xform->digest_length,
760 RTE_CRYPTO_AUTH_OP_VERIFY))
763 if (qat_alg_aead_session_create_content_desc_cipher(session,
764 aead_xform->key.data,
765 aead_xform->key.length))
769 session->digest_length = aead_xform->digest_length;
776 unsigned qat_crypto_sym_get_session_private_size(
777 struct rte_cryptodev *dev __rte_unused)
779 return RTE_ALIGN_CEIL(sizeof(struct qat_session), 8);
782 static inline uint32_t
783 qat_bpicipher_preprocess(struct qat_session *ctx,
784 struct rte_crypto_op *op)
786 uint8_t block_len = qat_cipher_get_block_size(ctx->qat_cipher_alg);
787 struct rte_crypto_sym_op *sym_op = op->sym;
788 uint8_t last_block_len = block_len > 0 ?
789 sym_op->cipher.data.length % block_len : 0;
791 if (last_block_len &&
792 ctx->qat_dir == ICP_QAT_HW_CIPHER_DECRYPT) {
794 /* Decrypt last block */
795 uint8_t *last_block, *dst, *iv;
796 uint32_t last_block_offset = sym_op->cipher.data.offset +
797 sym_op->cipher.data.length - last_block_len;
798 last_block = (uint8_t *) rte_pktmbuf_mtod_offset(sym_op->m_src,
799 uint8_t *, last_block_offset);
801 if (unlikely(sym_op->m_dst != NULL))
802 /* out-of-place operation (OOP) */
803 dst = (uint8_t *) rte_pktmbuf_mtod_offset(sym_op->m_dst,
804 uint8_t *, last_block_offset);
808 if (last_block_len < sym_op->cipher.data.length)
809 /* use previous block ciphertext as IV */
810 iv = last_block - block_len;
812 /* runt block, i.e. less than one full block */
813 iv = rte_crypto_op_ctod_offset(op, uint8_t *,
814 ctx->cipher_iv.offset);
816 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX
817 rte_hexdump(stdout, "BPI: src before pre-process:", last_block,
819 if (sym_op->m_dst != NULL)
820 rte_hexdump(stdout, "BPI: dst before pre-process:", dst,
823 bpi_cipher_decrypt(last_block, dst, iv, block_len,
824 last_block_len, ctx->bpi_ctx);
825 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX
826 rte_hexdump(stdout, "BPI: src after pre-process:", last_block,
828 if (sym_op->m_dst != NULL)
829 rte_hexdump(stdout, "BPI: dst after pre-process:", dst,
834 return sym_op->cipher.data.length - last_block_len;
837 static inline uint32_t
838 qat_bpicipher_postprocess(struct qat_session *ctx,
839 struct rte_crypto_op *op)
841 uint8_t block_len = qat_cipher_get_block_size(ctx->qat_cipher_alg);
842 struct rte_crypto_sym_op *sym_op = op->sym;
843 uint8_t last_block_len = block_len > 0 ?
844 sym_op->cipher.data.length % block_len : 0;
846 if (last_block_len > 0 &&
847 ctx->qat_dir == ICP_QAT_HW_CIPHER_ENCRYPT) {
849 /* Encrypt last block */
850 uint8_t *last_block, *dst, *iv;
851 uint32_t last_block_offset;
853 last_block_offset = sym_op->cipher.data.offset +
854 sym_op->cipher.data.length - last_block_len;
855 last_block = (uint8_t *) rte_pktmbuf_mtod_offset(sym_op->m_src,
856 uint8_t *, last_block_offset);
858 if (unlikely(sym_op->m_dst != NULL))
859 /* out-of-place operation (OOP) */
860 dst = (uint8_t *) rte_pktmbuf_mtod_offset(sym_op->m_dst,
861 uint8_t *, last_block_offset);
865 if (last_block_len < sym_op->cipher.data.length)
866 /* use previous block ciphertext as IV */
867 iv = dst - block_len;
869 /* runt block, i.e. less than one full block */
870 iv = rte_crypto_op_ctod_offset(op, uint8_t *,
871 ctx->cipher_iv.offset);
873 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_RX
874 rte_hexdump(stdout, "BPI: src before post-process:", last_block,
876 if (sym_op->m_dst != NULL)
877 rte_hexdump(stdout, "BPI: dst before post-process:",
878 dst, last_block_len);
880 bpi_cipher_encrypt(last_block, dst, iv, block_len,
881 last_block_len, ctx->bpi_ctx);
882 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_RX
883 rte_hexdump(stdout, "BPI: src after post-process:", last_block,
885 if (sym_op->m_dst != NULL)
886 rte_hexdump(stdout, "BPI: dst after post-process:", dst,
890 return sym_op->cipher.data.length - last_block_len;
894 qat_pmd_enqueue_op_burst(void *qp, struct rte_crypto_op **ops,
897 register struct qat_queue *queue;
898 struct qat_qp *tmp_qp = (struct qat_qp *)qp;
899 register uint32_t nb_ops_sent = 0;
900 register struct rte_crypto_op **cur_op = ops;
902 uint16_t nb_ops_possible = nb_ops;
903 register uint8_t *base_addr;
904 register uint32_t tail;
907 if (unlikely(nb_ops == 0))
910 /* read params used a lot in main loop into registers */
911 queue = &(tmp_qp->tx_q);
912 base_addr = (uint8_t *)queue->base_addr;
915 /* Find how many can actually fit on the ring */
916 overflow = rte_atomic16_add_return(&tmp_qp->inflights16, nb_ops)
917 - queue->max_inflights;
919 rte_atomic16_sub(&tmp_qp->inflights16, overflow);
920 nb_ops_possible = nb_ops - overflow;
921 if (nb_ops_possible == 0)
925 while (nb_ops_sent != nb_ops_possible) {
926 ret = qat_write_hw_desc_entry(*cur_op, base_addr + tail,
927 tmp_qp->op_cookies[tail / queue->msg_size]);
929 tmp_qp->stats.enqueue_err_count++;
931 * This message cannot be enqueued,
932 * decrease number of ops that wasn't sent
934 rte_atomic16_sub(&tmp_qp->inflights16,
935 nb_ops_possible - nb_ops_sent);
936 if (nb_ops_sent == 0)
941 tail = adf_modulo(tail + queue->msg_size, queue->modulo);
946 WRITE_CSR_RING_TAIL(tmp_qp->mmap_bar_addr, queue->hw_bundle_number,
947 queue->hw_queue_number, tail);
949 tmp_qp->stats.enqueued_count += nb_ops_sent;
954 qat_pmd_dequeue_op_burst(void *qp, struct rte_crypto_op **ops,
957 struct qat_queue *queue;
958 struct qat_qp *tmp_qp = (struct qat_qp *)qp;
959 uint32_t msg_counter = 0;
960 struct rte_crypto_op *rx_op;
961 struct icp_qat_fw_comn_resp *resp_msg;
963 queue = &(tmp_qp->rx_q);
964 resp_msg = (struct icp_qat_fw_comn_resp *)
965 ((uint8_t *)queue->base_addr + queue->head);
967 while (*(uint32_t *)resp_msg != ADF_RING_EMPTY_SIG &&
968 msg_counter != nb_ops) {
969 rx_op = (struct rte_crypto_op *)(uintptr_t)
970 (resp_msg->opaque_data);
972 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_RX
973 rte_hexdump(stdout, "qat_response:", (uint8_t *)resp_msg,
974 sizeof(struct icp_qat_fw_comn_resp));
977 if (ICP_QAT_FW_COMN_STATUS_FLAG_OK !=
978 ICP_QAT_FW_COMN_RESP_CRYPTO_STAT_GET(
979 resp_msg->comn_hdr.comn_status)) {
980 rx_op->status = RTE_CRYPTO_OP_STATUS_AUTH_FAILED;
982 struct qat_session *sess = (struct qat_session *)
983 get_session_private_data(
985 cryptodev_qat_driver_id);
988 qat_bpicipher_postprocess(sess, rx_op);
989 rx_op->status = RTE_CRYPTO_OP_STATUS_SUCCESS;
992 *(uint32_t *)resp_msg = ADF_RING_EMPTY_SIG;
993 queue->head = adf_modulo(queue->head +
995 ADF_RING_SIZE_MODULO(queue->queue_size));
996 resp_msg = (struct icp_qat_fw_comn_resp *)
997 ((uint8_t *)queue->base_addr +
1003 if (msg_counter > 0) {
1004 WRITE_CSR_RING_HEAD(tmp_qp->mmap_bar_addr,
1005 queue->hw_bundle_number,
1006 queue->hw_queue_number, queue->head);
1007 rte_atomic16_sub(&tmp_qp->inflights16, msg_counter);
1008 tmp_qp->stats.dequeued_count += msg_counter;
1014 qat_sgl_fill_array(struct rte_mbuf *buf, uint64_t buff_start,
1015 struct qat_alg_buf_list *list, uint32_t data_len)
1019 uint32_t buf_len = rte_pktmbuf_mtophys(buf) -
1020 buff_start + rte_pktmbuf_data_len(buf);
1022 list->bufers[0].addr = buff_start;
1023 list->bufers[0].resrvd = 0;
1024 list->bufers[0].len = buf_len;
1026 if (data_len <= buf_len) {
1027 list->num_bufs = nr;
1028 list->bufers[0].len = data_len;
1034 if (unlikely(nr == QAT_SGL_MAX_NUMBER)) {
1035 PMD_DRV_LOG(ERR, "QAT PMD exceeded size of QAT SGL"
1037 QAT_SGL_MAX_NUMBER);
1041 list->bufers[nr].len = rte_pktmbuf_data_len(buf);
1042 list->bufers[nr].resrvd = 0;
1043 list->bufers[nr].addr = rte_pktmbuf_mtophys(buf);
1045 buf_len += list->bufers[nr].len;
1048 if (buf_len > data_len) {
1049 list->bufers[nr].len -=
1055 list->num_bufs = nr;
1061 set_cipher_iv(uint16_t iv_length, uint16_t iv_offset,
1062 struct icp_qat_fw_la_cipher_req_params *cipher_param,
1063 struct rte_crypto_op *op,
1064 struct icp_qat_fw_la_bulk_req *qat_req)
1066 /* copy IV into request if it fits */
1067 if (iv_length <= sizeof(cipher_param->u.cipher_IV_array)) {
1068 rte_memcpy(cipher_param->u.cipher_IV_array,
1069 rte_crypto_op_ctod_offset(op, uint8_t *,
1073 ICP_QAT_FW_LA_CIPH_IV_FLD_FLAG_SET(
1074 qat_req->comn_hdr.serv_specif_flags,
1075 ICP_QAT_FW_CIPH_IV_64BIT_PTR);
1076 cipher_param->u.s.cipher_IV_ptr =
1077 rte_crypto_op_ctophys_offset(op,
1083 qat_write_hw_desc_entry(struct rte_crypto_op *op, uint8_t *out_msg,
1084 struct qat_crypto_op_cookie *qat_op_cookie)
1087 struct qat_session *ctx;
1088 struct icp_qat_fw_la_cipher_req_params *cipher_param;
1089 struct icp_qat_fw_la_auth_req_params *auth_param;
1090 register struct icp_qat_fw_la_bulk_req *qat_req;
1091 uint8_t do_auth = 0, do_cipher = 0, do_aead = 0;
1092 uint32_t cipher_len = 0, cipher_ofs = 0;
1093 uint32_t auth_len = 0, auth_ofs = 0;
1094 uint32_t min_ofs = 0;
1095 uint64_t src_buf_start = 0, dst_buf_start = 0;
1098 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX
1099 if (unlikely(op->type != RTE_CRYPTO_OP_TYPE_SYMMETRIC)) {
1100 PMD_DRV_LOG(ERR, "QAT PMD only supports symmetric crypto "
1101 "operation requests, op (%p) is not a "
1102 "symmetric operation.", op);
1106 if (unlikely(op->sess_type == RTE_CRYPTO_OP_SESSIONLESS)) {
1107 PMD_DRV_LOG(ERR, "QAT PMD only supports session oriented"
1108 " requests, op (%p) is sessionless.", op);
1112 ctx = (struct qat_session *)get_session_private_data(
1113 op->sym->session, cryptodev_qat_driver_id);
1115 if (unlikely(ctx == NULL)) {
1116 PMD_DRV_LOG(ERR, "Session was not created for this device");
1120 qat_req = (struct icp_qat_fw_la_bulk_req *)out_msg;
1121 rte_mov128((uint8_t *)qat_req, (const uint8_t *)&(ctx->fw_req));
1122 qat_req->comn_mid.opaque_data = (uint64_t)(uintptr_t)op;
1123 cipher_param = (void *)&qat_req->serv_specif_rqpars;
1124 auth_param = (void *)((uint8_t *)cipher_param + sizeof(*cipher_param));
1126 if (ctx->qat_cmd == ICP_QAT_FW_LA_CMD_HASH_CIPHER ||
1127 ctx->qat_cmd == ICP_QAT_FW_LA_CMD_CIPHER_HASH) {
1129 if (ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_128 ||
1130 ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_64) {
1136 } else if (ctx->qat_cmd == ICP_QAT_FW_LA_CMD_AUTH) {
1139 } else if (ctx->qat_cmd == ICP_QAT_FW_LA_CMD_CIPHER) {
1146 if (ctx->qat_cipher_alg ==
1147 ICP_QAT_HW_CIPHER_ALGO_SNOW_3G_UEA2 ||
1148 ctx->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_KASUMI ||
1149 ctx->qat_cipher_alg ==
1150 ICP_QAT_HW_CIPHER_ALGO_ZUC_3G_128_EEA3) {
1153 (cipher_param->cipher_length % BYTE_LENGTH != 0)
1154 || (cipher_param->cipher_offset
1155 % BYTE_LENGTH != 0))) {
1157 "SNOW3G/KASUMI/ZUC in QAT PMD only supports byte aligned values");
1158 op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
1161 cipher_len = op->sym->cipher.data.length >> 3;
1162 cipher_ofs = op->sym->cipher.data.offset >> 3;
1164 } else if (ctx->bpi_ctx) {
1165 /* DOCSIS - only send complete blocks to device
1166 * Process any partial block using CFB mode.
1167 * Even if 0 complete blocks, still send this to device
1168 * to get into rx queue for post-process and dequeuing
1170 cipher_len = qat_bpicipher_preprocess(ctx, op);
1171 cipher_ofs = op->sym->cipher.data.offset;
1173 cipher_len = op->sym->cipher.data.length;
1174 cipher_ofs = op->sym->cipher.data.offset;
1177 set_cipher_iv(ctx->cipher_iv.length, ctx->cipher_iv.offset,
1178 cipher_param, op, qat_req);
1179 min_ofs = cipher_ofs;
1184 if (ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2 ||
1185 ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_KASUMI_F9 ||
1186 ctx->qat_hash_alg ==
1187 ICP_QAT_HW_AUTH_ALGO_ZUC_3G_128_EIA3) {
1188 if (unlikely((auth_param->auth_off % BYTE_LENGTH != 0)
1189 || (auth_param->auth_len % BYTE_LENGTH != 0))) {
1191 "For SNOW3G/KASUMI/ZUC, QAT PMD only supports byte aligned values");
1192 op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
1195 auth_ofs = op->sym->auth.data.offset >> 3;
1196 auth_len = op->sym->auth.data.length >> 3;
1198 if (ctx->qat_hash_alg ==
1199 ICP_QAT_HW_AUTH_ALGO_KASUMI_F9) {
1201 auth_len = auth_len + auth_ofs + 1 -
1202 ICP_QAT_HW_KASUMI_BLK_SZ;
1203 auth_ofs = ICP_QAT_HW_KASUMI_BLK_SZ;
1205 auth_len = auth_len + auth_ofs + 1;
1209 auth_param->u1.aad_adr =
1210 rte_crypto_op_ctophys_offset(op,
1211 ctx->auth_iv.offset);
1213 } else if (ctx->qat_hash_alg ==
1214 ICP_QAT_HW_AUTH_ALGO_GALOIS_128 ||
1215 ctx->qat_hash_alg ==
1216 ICP_QAT_HW_AUTH_ALGO_GALOIS_64) {
1218 set_cipher_iv(ctx->auth_iv.length,
1219 ctx->auth_iv.offset,
1220 cipher_param, op, qat_req);
1222 auth_ofs = op->sym->auth.data.offset;
1223 auth_len = op->sym->auth.data.length;
1228 auth_param->auth_res_addr = op->sym->auth.digest.phys_addr;
1233 cipher_len = op->sym->aead.data.length;
1234 cipher_ofs = op->sym->aead.data.offset;
1235 auth_len = op->sym->aead.data.length;
1236 auth_ofs = op->sym->aead.data.offset;
1238 auth_param->u1.aad_adr = op->sym->aead.aad.phys_addr;
1239 auth_param->auth_res_addr = op->sym->aead.digest.phys_addr;
1240 set_cipher_iv(ctx->cipher_iv.length, ctx->cipher_iv.offset,
1241 cipher_param, op, qat_req);
1242 min_ofs = op->sym->aead.data.offset;
1245 if (op->sym->m_src->next || (op->sym->m_dst && op->sym->m_dst->next))
1248 /* adjust for chain case */
1249 if (do_cipher && do_auth)
1250 min_ofs = cipher_ofs < auth_ofs ? cipher_ofs : auth_ofs;
1252 if (unlikely(min_ofs >= rte_pktmbuf_data_len(op->sym->m_src) && do_sgl))
1255 if (unlikely(op->sym->m_dst != NULL)) {
1256 /* Out-of-place operation (OOP)
1257 * Don't align DMA start. DMA the minimum data-set
1258 * so as not to overwrite data in dest buffer
1261 rte_pktmbuf_mtophys_offset(op->sym->m_src, min_ofs);
1263 rte_pktmbuf_mtophys_offset(op->sym->m_dst, min_ofs);
1266 /* In-place operation
1267 * Start DMA at nearest aligned address below min_ofs
1270 rte_pktmbuf_mtophys_offset(op->sym->m_src, min_ofs)
1271 & QAT_64_BTYE_ALIGN_MASK;
1273 if (unlikely((rte_pktmbuf_mtophys(op->sym->m_src) -
1274 rte_pktmbuf_headroom(op->sym->m_src))
1276 /* alignment has pushed addr ahead of start of mbuf
1277 * so revert and take the performance hit
1280 rte_pktmbuf_mtophys_offset(op->sym->m_src,
1283 dst_buf_start = src_buf_start;
1286 if (do_cipher || do_aead) {
1287 cipher_param->cipher_offset =
1288 (uint32_t)rte_pktmbuf_mtophys_offset(
1289 op->sym->m_src, cipher_ofs) - src_buf_start;
1290 cipher_param->cipher_length = cipher_len;
1292 cipher_param->cipher_offset = 0;
1293 cipher_param->cipher_length = 0;
1296 if (do_auth || do_aead) {
1297 auth_param->auth_off = (uint32_t)rte_pktmbuf_mtophys_offset(
1298 op->sym->m_src, auth_ofs) - src_buf_start;
1299 auth_param->auth_len = auth_len;
1301 auth_param->auth_off = 0;
1302 auth_param->auth_len = 0;
1305 qat_req->comn_mid.dst_length =
1306 qat_req->comn_mid.src_length =
1307 (cipher_param->cipher_offset + cipher_param->cipher_length)
1308 > (auth_param->auth_off + auth_param->auth_len) ?
1309 (cipher_param->cipher_offset + cipher_param->cipher_length)
1310 : (auth_param->auth_off + auth_param->auth_len);
1314 ICP_QAT_FW_COMN_PTR_TYPE_SET(qat_req->comn_hdr.comn_req_flags,
1315 QAT_COMN_PTR_TYPE_SGL);
1316 ret = qat_sgl_fill_array(op->sym->m_src, src_buf_start,
1317 &qat_op_cookie->qat_sgl_list_src,
1318 qat_req->comn_mid.src_length);
1320 PMD_DRV_LOG(ERR, "QAT PMD Cannot fill sgl array");
1324 if (likely(op->sym->m_dst == NULL))
1325 qat_req->comn_mid.dest_data_addr =
1326 qat_req->comn_mid.src_data_addr =
1327 qat_op_cookie->qat_sgl_src_phys_addr;
1329 ret = qat_sgl_fill_array(op->sym->m_dst,
1331 &qat_op_cookie->qat_sgl_list_dst,
1332 qat_req->comn_mid.dst_length);
1335 PMD_DRV_LOG(ERR, "QAT PMD Cannot "
1340 qat_req->comn_mid.src_data_addr =
1341 qat_op_cookie->qat_sgl_src_phys_addr;
1342 qat_req->comn_mid.dest_data_addr =
1343 qat_op_cookie->qat_sgl_dst_phys_addr;
1346 qat_req->comn_mid.src_data_addr = src_buf_start;
1347 qat_req->comn_mid.dest_data_addr = dst_buf_start;
1350 if (ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_128 ||
1351 ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_64) {
1352 if (ctx->cipher_iv.length == 12 ||
1353 ctx->auth_iv.length == 12) {
1355 * For GCM a 12 byte IV is allowed,
1356 * but we need to inform the f/w
1358 ICP_QAT_FW_LA_GCM_IV_LEN_FLAG_SET(
1359 qat_req->comn_hdr.serv_specif_flags,
1360 ICP_QAT_FW_LA_GCM_IV_LEN_12_OCTETS);
1364 qat_req->comn_mid.dst_length =
1365 qat_req->comn_mid.src_length =
1366 rte_pktmbuf_data_len(op->sym->m_src);
1367 auth_param->u1.aad_adr = 0;
1368 auth_param->auth_len = op->sym->auth.data.length;
1369 auth_param->auth_off = op->sym->auth.data.offset;
1370 auth_param->u2.aad_sz = 0;
1374 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX
1375 rte_hexdump(stdout, "qat_req:", qat_req,
1376 sizeof(struct icp_qat_fw_la_bulk_req));
1377 rte_hexdump(stdout, "src_data:",
1378 rte_pktmbuf_mtod(op->sym->m_src, uint8_t*),
1379 rte_pktmbuf_data_len(op->sym->m_src));
1381 uint8_t *cipher_iv_ptr = rte_crypto_op_ctod_offset(op,
1383 ctx->cipher_iv.offset);
1384 rte_hexdump(stdout, "cipher iv:", cipher_iv_ptr,
1385 ctx->cipher_iv.length);
1389 if (ctx->auth_iv.length) {
1390 uint8_t *auth_iv_ptr = rte_crypto_op_ctod_offset(op,
1392 ctx->auth_iv.offset);
1393 rte_hexdump(stdout, "auth iv:", auth_iv_ptr,
1394 ctx->auth_iv.length);
1396 rte_hexdump(stdout, "digest:", op->sym->auth.digest.data,
1397 ctx->digest_length);
1401 rte_hexdump(stdout, "digest:", op->sym->aead.digest.data,
1402 ctx->digest_length);
1403 rte_hexdump(stdout, "aad:", op->sym->aead.aad.data,
1410 static inline uint32_t adf_modulo(uint32_t data, uint32_t shift)
1412 uint32_t div = data >> shift;
1413 uint32_t mult = div << shift;
1418 int qat_dev_config(__rte_unused struct rte_cryptodev *dev,
1419 __rte_unused struct rte_cryptodev_config *config)
1421 PMD_INIT_FUNC_TRACE();
1425 int qat_dev_start(__rte_unused struct rte_cryptodev *dev)
1427 PMD_INIT_FUNC_TRACE();
1431 void qat_dev_stop(__rte_unused struct rte_cryptodev *dev)
1433 PMD_INIT_FUNC_TRACE();
1436 int qat_dev_close(struct rte_cryptodev *dev)
1440 PMD_INIT_FUNC_TRACE();
1442 for (i = 0; i < dev->data->nb_queue_pairs; i++) {
1443 ret = qat_crypto_sym_qp_release(dev, i);
1451 void qat_dev_info_get(struct rte_cryptodev *dev,
1452 struct rte_cryptodev_info *info)
1454 struct qat_pmd_private *internals = dev->data->dev_private;
1456 PMD_INIT_FUNC_TRACE();
1458 info->max_nb_queue_pairs =
1459 ADF_NUM_SYM_QPS_PER_BUNDLE *
1460 ADF_NUM_BUNDLES_PER_DEV;
1461 info->feature_flags = dev->feature_flags;
1462 info->capabilities = internals->qat_dev_capabilities;
1463 info->sym.max_nb_sessions = internals->max_nb_sessions;
1464 info->driver_id = cryptodev_qat_driver_id;
1465 info->pci_dev = RTE_DEV_TO_PCI(dev->device);
1469 void qat_crypto_sym_stats_get(struct rte_cryptodev *dev,
1470 struct rte_cryptodev_stats *stats)
1473 struct qat_qp **qp = (struct qat_qp **)(dev->data->queue_pairs);
1475 PMD_INIT_FUNC_TRACE();
1476 if (stats == NULL) {
1477 PMD_DRV_LOG(ERR, "invalid stats ptr NULL");
1480 for (i = 0; i < dev->data->nb_queue_pairs; i++) {
1481 if (qp[i] == NULL) {
1482 PMD_DRV_LOG(DEBUG, "Uninitialised queue pair");
1486 stats->enqueued_count += qp[i]->stats.enqueued_count;
1487 stats->dequeued_count += qp[i]->stats.dequeued_count;
1488 stats->enqueue_err_count += qp[i]->stats.enqueue_err_count;
1489 stats->dequeue_err_count += qp[i]->stats.dequeue_err_count;
1493 void qat_crypto_sym_stats_reset(struct rte_cryptodev *dev)
1496 struct qat_qp **qp = (struct qat_qp **)(dev->data->queue_pairs);
1498 PMD_INIT_FUNC_TRACE();
1499 for (i = 0; i < dev->data->nb_queue_pairs; i++)
1500 memset(&(qp[i]->stats), 0, sizeof(qp[i]->stats));
1501 PMD_DRV_LOG(DEBUG, "QAT crypto: stats cleared");