qat_sym.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2015-2018 Intel Corporation
   3  */
   4
   5 #include <rte_mempool.h>
   6 #include <rte_mbuf.h>
   7 #include <rte_hexdump.h>
   8 #include <rte_crypto_sym.h>
   9 #include <rte_bus_pci.h>
  10 #include <rte_byteorder.h>
  11
  12 #include <openssl/evp.h>
  13
  14 #include "qat_logs.h"
  15 #include "qat_sym_session.h"
  16 #include "qat_sym.h"
  17 #include "qat_qp.h"
  18 #include "adf_transport_access_macros.h"
  19 #include "qat_device.h"
  20
  21 #define BYTE_LENGTH    8
  22 /* bpi is only used for partial blocks of DES and AES
  23  * so AES block len can be assumed as max len for iv, src and dst
  24  */
  25 #define BPI_MAX_ENCR_IV_LEN ICP_QAT_HW_AES_BLK_SZ
  26
  27 /** Encrypt a single partial block
  28  *  Depends on openssl libcrypto
  29  *  Uses ECB+XOR to do CFB encryption, same result, more performant
  30  */
  31 static inline int
  32 bpi_cipher_encrypt(uint8_t *src, uint8_t *dst,
  33                 uint8_t *iv, int ivlen, int srclen,
  34                 void *bpi_ctx)
  35 {
  36         EVP_CIPHER_CTX *ctx = (EVP_CIPHER_CTX *)bpi_ctx;
  37         int encrypted_ivlen;
  38         uint8_t encrypted_iv[BPI_MAX_ENCR_IV_LEN];
  39         uint8_t *encr = encrypted_iv;
  40
  41         /* ECB method: encrypt the IV, then XOR this with plaintext */
  42         if (EVP_EncryptUpdate(ctx, encrypted_iv, &encrypted_ivlen, iv, ivlen)
  43                                                                 <= 0)
  44                 goto cipher_encrypt_err;
  45
  46         for (; srclen != 0; --srclen, ++dst, ++src, ++encr)
  47                 *dst = *src ^ *encr;
  48
  49         return 0;
  50
  51 cipher_encrypt_err:
  52         PMD_DRV_LOG(ERR, "libcrypto ECB cipher encrypt failed");
  53         return -EINVAL;
  54 }
  55
  56 /** Decrypt a single partial block
  57  *  Depends on openssl libcrypto
  58  *  Uses ECB+XOR to do CFB encryption, same result, more performant
  59  */
  60 static inline int
  61 bpi_cipher_decrypt(uint8_t *src, uint8_t *dst,
  62                 uint8_t *iv, int ivlen, int srclen,
  63                 void *bpi_ctx)
  64 {
  65         EVP_CIPHER_CTX *ctx = (EVP_CIPHER_CTX *)bpi_ctx;
  66         int encrypted_ivlen;
  67         uint8_t encrypted_iv[BPI_MAX_ENCR_IV_LEN];
  68         uint8_t *encr = encrypted_iv;
  69
  70         /* ECB method: encrypt (not decrypt!) the IV, then XOR with plaintext */
  71         if (EVP_EncryptUpdate(ctx, encrypted_iv, &encrypted_ivlen, iv, ivlen)
  72                                                                 <= 0)
  73                 goto cipher_decrypt_err;
  74
  75         for (; srclen != 0; --srclen, ++dst, ++src, ++encr)
  76                 *dst = *src ^ *encr;
  77
  78         return 0;
  79
  80 cipher_decrypt_err:
  81         PMD_DRV_LOG(ERR, "libcrypto ECB cipher decrypt for BPI IV failed");
  82         return -EINVAL;
  83 }
  84
  85 /** Creates a context in either AES or DES in ECB mode
  86  *  Depends on openssl libcrypto
  87  */
  88
  89 static inline uint32_t
  90 qat_bpicipher_preprocess(struct qat_sym_session *ctx,
  91                                 struct rte_crypto_op *op)
  92 {
  93         int block_len = qat_cipher_get_block_size(ctx->qat_cipher_alg);
  94         struct rte_crypto_sym_op *sym_op = op->sym;
  95         uint8_t last_block_len = block_len > 0 ?
  96                         sym_op->cipher.data.length % block_len : 0;
  97
  98         if (last_block_len &&
  99                         ctx->qat_dir == ICP_QAT_HW_CIPHER_DECRYPT) {
 100
 101                 /* Decrypt last block */
 102                 uint8_t *last_block, *dst, *iv;
 103                 uint32_t last_block_offset = sym_op->cipher.data.offset +
 104                                 sym_op->cipher.data.length - last_block_len;
 105                 last_block = (uint8_t *) rte_pktmbuf_mtod_offset(sym_op->m_src,
 106                                 uint8_t *, last_block_offset);
 107
 108                 if (unlikely(sym_op->m_dst != NULL))
 109                         /* out-of-place operation (OOP) */
 110                         dst = (uint8_t *) rte_pktmbuf_mtod_offset(sym_op->m_dst,
 111                                                 uint8_t *, last_block_offset);
 112                 else
 113                         dst = last_block;
 114
 115                 if (last_block_len < sym_op->cipher.data.length)
 116                         /* use previous block ciphertext as IV */
 117                         iv = last_block - block_len;
 118                 else
 119                         /* runt block, i.e. less than one full block */
 120                         iv = rte_crypto_op_ctod_offset(op, uint8_t *,
 121                                         ctx->cipher_iv.offset);
 122
 123 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX
 124                 rte_hexdump(stdout, "BPI: src before pre-process:", last_block,
 125                         last_block_len);
 126                 if (sym_op->m_dst != NULL)
 127                         rte_hexdump(stdout, "BPI: dst before pre-process:", dst,
 128                                 last_block_len);
 129 #endif
 130                 bpi_cipher_decrypt(last_block, dst, iv, block_len,
 131                                 last_block_len, ctx->bpi_ctx);
 132 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX
 133                 rte_hexdump(stdout, "BPI: src after pre-process:", last_block,
 134                         last_block_len);
 135                 if (sym_op->m_dst != NULL)
 136                         rte_hexdump(stdout, "BPI: dst after pre-process:", dst,
 137                                 last_block_len);
 138 #endif
 139         }
 140
 141         return sym_op->cipher.data.length - last_block_len;
 142 }
 143
 144 static inline uint32_t
 145 qat_bpicipher_postprocess(struct qat_sym_session *ctx,
 146                                 struct rte_crypto_op *op)
 147 {
 148         int block_len = qat_cipher_get_block_size(ctx->qat_cipher_alg);
 149         struct rte_crypto_sym_op *sym_op = op->sym;
 150         uint8_t last_block_len = block_len > 0 ?
 151                         sym_op->cipher.data.length % block_len : 0;
 152
 153         if (last_block_len > 0 &&
 154                         ctx->qat_dir == ICP_QAT_HW_CIPHER_ENCRYPT) {
 155
 156                 /* Encrypt last block */
 157                 uint8_t *last_block, *dst, *iv;
 158                 uint32_t last_block_offset;
 159
 160                 last_block_offset = sym_op->cipher.data.offset +
 161                                 sym_op->cipher.data.length - last_block_len;
 162                 last_block = (uint8_t *) rte_pktmbuf_mtod_offset(sym_op->m_src,
 163                                 uint8_t *, last_block_offset);
 164
 165                 if (unlikely(sym_op->m_dst != NULL))
 166                         /* out-of-place operation (OOP) */
 167                         dst = (uint8_t *) rte_pktmbuf_mtod_offset(sym_op->m_dst,
 168                                                 uint8_t *, last_block_offset);
 169                 else
 170                         dst = last_block;
 171
 172                 if (last_block_len < sym_op->cipher.data.length)
 173                         /* use previous block ciphertext as IV */
 174                         iv = dst - block_len;
 175                 else
 176                         /* runt block, i.e. less than one full block */
 177                         iv = rte_crypto_op_ctod_offset(op, uint8_t *,
 178                                         ctx->cipher_iv.offset);
 179
 180 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_RX
 181                 rte_hexdump(stdout, "BPI: src before post-process:", last_block,
 182                         last_block_len);
 183                 if (sym_op->m_dst != NULL)
 184                         rte_hexdump(stdout, "BPI: dst before post-process:",
 185                                         dst, last_block_len);
 186 #endif
 187                 bpi_cipher_encrypt(last_block, dst, iv, block_len,
 188                                 last_block_len, ctx->bpi_ctx);
 189 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_RX
 190                 rte_hexdump(stdout, "BPI: src after post-process:", last_block,
 191                         last_block_len);
 192                 if (sym_op->m_dst != NULL)
 193                         rte_hexdump(stdout, "BPI: dst after post-process:", dst,
 194                                 last_block_len);
 195 #endif
 196         }
 197         return sym_op->cipher.data.length - last_block_len;
 198 }
 199
 200 uint16_t
 201 qat_sym_pmd_enqueue_op_burst(void *qp, struct rte_crypto_op **ops,
 202                 uint16_t nb_ops)
 203 {
 204         return qat_enqueue_op_burst(qp, (void **)ops, nb_ops);
 205 }
 206
 207 int
 208 qat_sym_process_response(void **op, uint8_t *resp,
 209                 __rte_unused void *op_cookie,
 210                 __rte_unused enum qat_device_gen qat_dev_gen)
 211 {
 212
 213         struct icp_qat_fw_comn_resp *resp_msg =
 214                         (struct icp_qat_fw_comn_resp *)resp;
 215         struct rte_crypto_op *rx_op = (struct rte_crypto_op *)(uintptr_t)
 216                         (resp_msg->opaque_data);
 217
 218 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_RX
 219         rte_hexdump(stdout, "qat_response:", (uint8_t *)resp_msg,
 220                         sizeof(struct icp_qat_fw_comn_resp));
 221 #endif
 222
 223         if (ICP_QAT_FW_COMN_STATUS_FLAG_OK !=
 224                         ICP_QAT_FW_COMN_RESP_CRYPTO_STAT_GET(
 225                         resp_msg->comn_hdr.comn_status)) {
 226
 227                 rx_op->status = RTE_CRYPTO_OP_STATUS_AUTH_FAILED;
 228         } else {
 229                 struct qat_sym_session *sess = (struct qat_sym_session *)
 230                                                 get_session_private_data(
 231                                                 rx_op->sym->session,
 232                                                 cryptodev_qat_driver_id);
 233
 234                 if (sess->bpi_ctx)
 235                         qat_bpicipher_postprocess(sess, rx_op);
 236                 rx_op->status = RTE_CRYPTO_OP_STATUS_SUCCESS;
 237         }
 238         *op = (void *)rx_op;
 239
 240         return 0;
 241 }
 242
 243
 244 uint16_t
 245 qat_sym_pmd_dequeue_op_burst(void *qp, struct rte_crypto_op **ops,
 246                 uint16_t nb_ops)
 247 {
 248         return qat_dequeue_op_burst(qp, (void **)ops, nb_ops);
 249 }
 250
 251 static inline void
 252 set_cipher_iv(uint16_t iv_length, uint16_t iv_offset,
 253                 struct icp_qat_fw_la_cipher_req_params *cipher_param,
 254                 struct rte_crypto_op *op,
 255                 struct icp_qat_fw_la_bulk_req *qat_req)
 256 {
 257         /* copy IV into request if it fits */
 258         if (iv_length <= sizeof(cipher_param->u.cipher_IV_array)) {
 259                 rte_memcpy(cipher_param->u.cipher_IV_array,
 260                                 rte_crypto_op_ctod_offset(op, uint8_t *,
 261                                         iv_offset),
 262                                 iv_length);
 263         } else {
 264                 ICP_QAT_FW_LA_CIPH_IV_FLD_FLAG_SET(
 265                                 qat_req->comn_hdr.serv_specif_flags,
 266                                 ICP_QAT_FW_CIPH_IV_64BIT_PTR);
 267                 cipher_param->u.s.cipher_IV_ptr =
 268                                 rte_crypto_op_ctophys_offset(op,
 269                                         iv_offset);
 270         }
 271 }
 272
 273 /** Set IV for CCM is special case, 0th byte is set to q-1
 274  *  where q is padding of nonce in 16 byte block
 275  */
 276 static inline void
 277 set_cipher_iv_ccm(uint16_t iv_length, uint16_t iv_offset,
 278                 struct icp_qat_fw_la_cipher_req_params *cipher_param,
 279                 struct rte_crypto_op *op, uint8_t q, uint8_t aad_len_field_sz)
 280 {
 281         rte_memcpy(((uint8_t *)cipher_param->u.cipher_IV_array) +
 282                         ICP_QAT_HW_CCM_NONCE_OFFSET,
 283                         rte_crypto_op_ctod_offset(op, uint8_t *,
 284                                 iv_offset) + ICP_QAT_HW_CCM_NONCE_OFFSET,
 285                         iv_length);
 286         *(uint8_t *)&cipher_param->u.cipher_IV_array[0] =
 287                         q - ICP_QAT_HW_CCM_NONCE_OFFSET;
 288
 289         if (aad_len_field_sz)
 290                 rte_memcpy(&op->sym->aead.aad.data[ICP_QAT_HW_CCM_NONCE_OFFSET],
 291                         rte_crypto_op_ctod_offset(op, uint8_t *,
 292                                 iv_offset) + ICP_QAT_HW_CCM_NONCE_OFFSET,
 293                         iv_length);
 294 }
 295
 296
 297 int
 298 qat_sym_build_request(void *in_op, uint8_t *out_msg,
 299                 void *op_cookie, enum qat_device_gen qat_dev_gen)
 300 {
 301         int ret = 0;
 302         struct qat_sym_session *ctx;
 303         struct icp_qat_fw_la_cipher_req_params *cipher_param;
 304         struct icp_qat_fw_la_auth_req_params *auth_param;
 305         register struct icp_qat_fw_la_bulk_req *qat_req;
 306         uint8_t do_auth = 0, do_cipher = 0, do_aead = 0;
 307         uint32_t cipher_len = 0, cipher_ofs = 0;
 308         uint32_t auth_len = 0, auth_ofs = 0;
 309         uint32_t min_ofs = 0;
 310         uint64_t src_buf_start = 0, dst_buf_start = 0;
 311         uint8_t do_sgl = 0;
 312         struct rte_crypto_op *op = (struct rte_crypto_op *)in_op;
 313         struct qat_sym_op_cookie *cookie =
 314                                 (struct qat_sym_op_cookie *)op_cookie;
 315
 316 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX
 317         if (unlikely(op->type != RTE_CRYPTO_OP_TYPE_SYMMETRIC)) {
 318                 PMD_DRV_LOG(ERR, "QAT PMD only supports symmetric crypto "
 319                                 "operation requests, op (%p) is not a "
 320                                 "symmetric operation.", op);
 321                 return -EINVAL;
 322         }
 323 #endif
 324         if (unlikely(op->sess_type == RTE_CRYPTO_OP_SESSIONLESS)) {
 325                 PMD_DRV_LOG(ERR, "QAT PMD only supports session oriented"
 326                                 " requests, op (%p) is sessionless.", op);
 327                 return -EINVAL;
 328         }
 329
 330         ctx = (struct qat_sym_session *)get_session_private_data(
 331                         op->sym->session, cryptodev_qat_driver_id);
 332
 333         if (unlikely(ctx == NULL)) {
 334                 PMD_DRV_LOG(ERR, "Session was not created for this device");
 335                 return -EINVAL;
 336         }
 337
 338         if (unlikely(ctx->min_qat_dev_gen > qat_dev_gen)) {
 339                 PMD_DRV_LOG(ERR, "Session alg not supported on this device gen");
 340                 op->status = RTE_CRYPTO_OP_STATUS_INVALID_SESSION;
 341                 return -EINVAL;
 342         }
 343
 344         qat_req = (struct icp_qat_fw_la_bulk_req *)out_msg;
 345         rte_mov128((uint8_t *)qat_req, (const uint8_t *)&(ctx->fw_req));
 346         qat_req->comn_mid.opaque_data = (uint64_t)(uintptr_t)op;
 347         cipher_param = (void *)&qat_req->serv_specif_rqpars;
 348         auth_param = (void *)((uint8_t *)cipher_param + sizeof(*cipher_param));
 349
 350         if (ctx->qat_cmd == ICP_QAT_FW_LA_CMD_HASH_CIPHER ||
 351                         ctx->qat_cmd == ICP_QAT_FW_LA_CMD_CIPHER_HASH) {
 352                 /* AES-GCM or AES-CCM */
 353                 if (ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_128 ||
 354                         ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_64 ||
 355                         (ctx->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_AES128
 356                         && ctx->qat_mode == ICP_QAT_HW_CIPHER_CTR_MODE
 357                         && ctx->qat_hash_alg ==
 358                                         ICP_QAT_HW_AUTH_ALGO_AES_CBC_MAC)) {
 359                         do_aead = 1;
 360                 } else {
 361                         do_auth = 1;
 362                         do_cipher = 1;
 363                 }
 364         } else if (ctx->qat_cmd == ICP_QAT_FW_LA_CMD_AUTH) {
 365                 do_auth = 1;
 366                 do_cipher = 0;
 367         } else if (ctx->qat_cmd == ICP_QAT_FW_LA_CMD_CIPHER) {
 368                 do_auth = 0;
 369                 do_cipher = 1;
 370         }
 371
 372         if (do_cipher) {
 373
 374                 if (ctx->qat_cipher_alg ==
 375                                          ICP_QAT_HW_CIPHER_ALGO_SNOW_3G_UEA2 ||
 376                         ctx->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_KASUMI ||
 377                         ctx->qat_cipher_alg ==
 378                                 ICP_QAT_HW_CIPHER_ALGO_ZUC_3G_128_EEA3) {
 379
 380                         if (unlikely(
 381                                 (cipher_param->cipher_length % BYTE_LENGTH != 0)
 382                                  || (cipher_param->cipher_offset
 383                                                         % BYTE_LENGTH != 0))) {
 384                                 PMD_DRV_LOG(ERR,
 385                   "SNOW3G/KASUMI/ZUC in QAT PMD only supports byte aligned values");
 386                                 op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
 387                                 return -EINVAL;
 388                         }
 389                         cipher_len = op->sym->cipher.data.length >> 3;
 390                         cipher_ofs = op->sym->cipher.data.offset >> 3;
 391
 392                 } else if (ctx->bpi_ctx) {
 393                         /* DOCSIS - only send complete blocks to device
 394                          * Process any partial block using CFB mode.
 395                          * Even if 0 complete blocks, still send this to device
 396                          * to get into rx queue for post-process and dequeuing
 397                          */
 398                         cipher_len = qat_bpicipher_preprocess(ctx, op);
 399                         cipher_ofs = op->sym->cipher.data.offset;
 400                 } else {
 401                         cipher_len = op->sym->cipher.data.length;
 402                         cipher_ofs = op->sym->cipher.data.offset;
 403                 }
 404
 405                 set_cipher_iv(ctx->cipher_iv.length, ctx->cipher_iv.offset,
 406                                 cipher_param, op, qat_req);
 407                 min_ofs = cipher_ofs;
 408         }
 409
 410         if (do_auth) {
 411
 412                 if (ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2 ||
 413                         ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_KASUMI_F9 ||
 414                         ctx->qat_hash_alg ==
 415                                 ICP_QAT_HW_AUTH_ALGO_ZUC_3G_128_EIA3) {
 416                         if (unlikely((auth_param->auth_off % BYTE_LENGTH != 0)
 417                                 || (auth_param->auth_len % BYTE_LENGTH != 0))) {
 418                                 PMD_DRV_LOG(ERR,
 419                 "For SNOW3G/KASUMI/ZUC, QAT PMD only supports byte aligned values");
 420                                 op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
 421                                 return -EINVAL;
 422                         }
 423                         auth_ofs = op->sym->auth.data.offset >> 3;
 424                         auth_len = op->sym->auth.data.length >> 3;
 425
 426                         auth_param->u1.aad_adr =
 427                                         rte_crypto_op_ctophys_offset(op,
 428                                                         ctx->auth_iv.offset);
 429
 430                 } else if (ctx->qat_hash_alg ==
 431                                         ICP_QAT_HW_AUTH_ALGO_GALOIS_128 ||
 432                                 ctx->qat_hash_alg ==
 433                                         ICP_QAT_HW_AUTH_ALGO_GALOIS_64) {
 434                         /* AES-GMAC */
 435                         set_cipher_iv(ctx->auth_iv.length,
 436                                 ctx->auth_iv.offset,
 437                                 cipher_param, op, qat_req);
 438                         auth_ofs = op->sym->auth.data.offset;
 439                         auth_len = op->sym->auth.data.length;
 440
 441                         auth_param->u1.aad_adr = 0;
 442                         auth_param->u2.aad_sz = 0;
 443
 444                         /*
 445                          * If len(iv)==12B fw computes J0
 446                          */
 447                         if (ctx->auth_iv.length == 12) {
 448                                 ICP_QAT_FW_LA_GCM_IV_LEN_FLAG_SET(
 449                                         qat_req->comn_hdr.serv_specif_flags,
 450                                         ICP_QAT_FW_LA_GCM_IV_LEN_12_OCTETS);
 451
 452                         }
 453                 } else {
 454                         auth_ofs = op->sym->auth.data.offset;
 455                         auth_len = op->sym->auth.data.length;
 456
 457                 }
 458                 min_ofs = auth_ofs;
 459
 460                 if (likely(ctx->qat_hash_alg != ICP_QAT_HW_AUTH_ALGO_NULL))
 461                         auth_param->auth_res_addr =
 462                                         op->sym->auth.digest.phys_addr;
 463
 464         }
 465
 466         if (do_aead) {
 467                 /*
 468                  * This address may used for setting AAD physical pointer
 469                  * into IV offset from op
 470                  */
 471                 rte_iova_t aad_phys_addr_aead = op->sym->aead.aad.phys_addr;
 472                 if (ctx->qat_hash_alg ==
 473                                 ICP_QAT_HW_AUTH_ALGO_GALOIS_128 ||
 474                                 ctx->qat_hash_alg ==
 475                                         ICP_QAT_HW_AUTH_ALGO_GALOIS_64) {
 476                         /*
 477                          * If len(iv)==12B fw computes J0
 478                          */
 479                         if (ctx->cipher_iv.length == 12) {
 480                                 ICP_QAT_FW_LA_GCM_IV_LEN_FLAG_SET(
 481                                         qat_req->comn_hdr.serv_specif_flags,
 482                                         ICP_QAT_FW_LA_GCM_IV_LEN_12_OCTETS);
 483                         }
 484                         set_cipher_iv(ctx->cipher_iv.length,
 485                                         ctx->cipher_iv.offset,
 486                                         cipher_param, op, qat_req);
 487
 488                 } else if (ctx->qat_hash_alg ==
 489                                 ICP_QAT_HW_AUTH_ALGO_AES_CBC_MAC) {
 490
 491                         /* In case of AES-CCM this may point to user selected
 492                          * memory or iv offset in cypto_op
 493                          */
 494                         uint8_t *aad_data = op->sym->aead.aad.data;
 495                         /* This is true AAD length, it not includes 18 bytes of
 496                          * preceding data
 497                          */
 498                         uint8_t aad_ccm_real_len = 0;
 499                         uint8_t aad_len_field_sz = 0;
 500                         uint32_t msg_len_be =
 501                                         rte_bswap32(op->sym->aead.data.length);
 502
 503                         if (ctx->aad_len > ICP_QAT_HW_CCM_AAD_DATA_OFFSET) {
 504                                 aad_len_field_sz = ICP_QAT_HW_CCM_AAD_LEN_INFO;
 505                                 aad_ccm_real_len = ctx->aad_len -
 506                                         ICP_QAT_HW_CCM_AAD_B0_LEN -
 507                                         ICP_QAT_HW_CCM_AAD_LEN_INFO;
 508                         } else {
 509                                 /*
 510                                  * aad_len not greater than 18, so no actual aad
 511                                  *  data, then use IV after op for B0 block
 512                                  */
 513                                 aad_data = rte_crypto_op_ctod_offset(op,
 514                                                 uint8_t *,
 515                                                 ctx->cipher_iv.offset);
 516                                 aad_phys_addr_aead =
 517                                                 rte_crypto_op_ctophys_offset(op,
 518                                                         ctx->cipher_iv.offset);
 519                         }
 520
 521                         uint8_t q = ICP_QAT_HW_CCM_NQ_CONST -
 522                                                         ctx->cipher_iv.length;
 523
 524                         aad_data[0] = ICP_QAT_HW_CCM_BUILD_B0_FLAGS(
 525                                                         aad_len_field_sz,
 526                                                         ctx->digest_length, q);
 527
 528                         if (q > ICP_QAT_HW_CCM_MSG_LEN_MAX_FIELD_SIZE) {
 529                                 memcpy(aad_data + ctx->cipher_iv.length +
 530                                     ICP_QAT_HW_CCM_NONCE_OFFSET +
 531                                     (q - ICP_QAT_HW_CCM_MSG_LEN_MAX_FIELD_SIZE),
 532                                     (uint8_t *)&msg_len_be,
 533                                     ICP_QAT_HW_CCM_MSG_LEN_MAX_FIELD_SIZE);
 534                         } else {
 535                                 memcpy(aad_data + ctx->cipher_iv.length +
 536                                     ICP_QAT_HW_CCM_NONCE_OFFSET,
 537                                     (uint8_t *)&msg_len_be
 538                                     + (ICP_QAT_HW_CCM_MSG_LEN_MAX_FIELD_SIZE
 539                                     - q), q);
 540                         }
 541
 542                         if (aad_len_field_sz > 0) {
 543                                 *(uint16_t *)&aad_data[ICP_QAT_HW_CCM_AAD_B0_LEN]
 544                                                 = rte_bswap16(aad_ccm_real_len);
 545
 546                                 if ((aad_ccm_real_len + aad_len_field_sz)
 547                                                 % ICP_QAT_HW_CCM_AAD_B0_LEN) {
 548                                         uint8_t pad_len = 0;
 549                                         uint8_t pad_idx = 0;
 550
 551                                         pad_len = ICP_QAT_HW_CCM_AAD_B0_LEN -
 552                                         ((aad_ccm_real_len + aad_len_field_sz) %
 553                                                 ICP_QAT_HW_CCM_AAD_B0_LEN);
 554                                         pad_idx = ICP_QAT_HW_CCM_AAD_B0_LEN +
 555                                             aad_ccm_real_len + aad_len_field_sz;
 556                                         memset(&aad_data[pad_idx],
 557                                                         0, pad_len);
 558                                 }
 559
 560                         }
 561
 562                         set_cipher_iv_ccm(ctx->cipher_iv.length,
 563                                         ctx->cipher_iv.offset,
 564                                         cipher_param, op, q,
 565                                         aad_len_field_sz);
 566
 567                 }
 568
 569                 cipher_len = op->sym->aead.data.length;
 570                 cipher_ofs = op->sym->aead.data.offset;
 571                 auth_len = op->sym->aead.data.length;
 572                 auth_ofs = op->sym->aead.data.offset;
 573
 574                 auth_param->u1.aad_adr = aad_phys_addr_aead;
 575                 auth_param->auth_res_addr = op->sym->aead.digest.phys_addr;
 576                 min_ofs = op->sym->aead.data.offset;
 577         }
 578
 579         if (op->sym->m_src->next || (op->sym->m_dst && op->sym->m_dst->next))
 580                 do_sgl = 1;
 581
 582         /* adjust for chain case */
 583         if (do_cipher && do_auth)
 584                 min_ofs = cipher_ofs < auth_ofs ? cipher_ofs : auth_ofs;
 585
 586         if (unlikely(min_ofs >= rte_pktmbuf_data_len(op->sym->m_src) && do_sgl))
 587                 min_ofs = 0;
 588
 589         if (unlikely(op->sym->m_dst != NULL)) {
 590                 /* Out-of-place operation (OOP)
 591                  * Don't align DMA start. DMA the minimum data-set
 592                  * so as not to overwrite data in dest buffer
 593                  */
 594                 src_buf_start =
 595                         rte_pktmbuf_iova_offset(op->sym->m_src, min_ofs);
 596                 dst_buf_start =
 597                         rte_pktmbuf_iova_offset(op->sym->m_dst, min_ofs);
 598
 599         } else {
 600                 /* In-place operation
 601                  * Start DMA at nearest aligned address below min_ofs
 602                  */
 603                 src_buf_start =
 604                         rte_pktmbuf_iova_offset(op->sym->m_src, min_ofs)
 605                                                 & QAT_64_BTYE_ALIGN_MASK;
 606
 607                 if (unlikely((rte_pktmbuf_iova(op->sym->m_src) -
 608                                         rte_pktmbuf_headroom(op->sym->m_src))
 609                                                         > src_buf_start)) {
 610                         /* alignment has pushed addr ahead of start of mbuf
 611                          * so revert and take the performance hit
 612                          */
 613                         src_buf_start =
 614                                 rte_pktmbuf_iova_offset(op->sym->m_src,
 615                                                                 min_ofs);
 616                 }
 617                 dst_buf_start = src_buf_start;
 618         }
 619
 620         if (do_cipher || do_aead) {
 621                 cipher_param->cipher_offset =
 622                                 (uint32_t)rte_pktmbuf_iova_offset(
 623                                 op->sym->m_src, cipher_ofs) - src_buf_start;
 624                 cipher_param->cipher_length = cipher_len;
 625         } else {
 626                 cipher_param->cipher_offset = 0;
 627                 cipher_param->cipher_length = 0;
 628         }
 629
 630         if (do_auth || do_aead) {
 631                 auth_param->auth_off = (uint32_t)rte_pktmbuf_iova_offset(
 632                                 op->sym->m_src, auth_ofs) - src_buf_start;
 633                 auth_param->auth_len = auth_len;
 634         } else {
 635                 auth_param->auth_off = 0;
 636                 auth_param->auth_len = 0;
 637         }
 638
 639         qat_req->comn_mid.dst_length =
 640                 qat_req->comn_mid.src_length =
 641                 (cipher_param->cipher_offset + cipher_param->cipher_length)
 642                 > (auth_param->auth_off + auth_param->auth_len) ?
 643                 (cipher_param->cipher_offset + cipher_param->cipher_length)
 644                 : (auth_param->auth_off + auth_param->auth_len);
 645
 646         if (do_sgl) {
 647
 648                 ICP_QAT_FW_COMN_PTR_TYPE_SET(qat_req->comn_hdr.comn_req_flags,
 649                                 QAT_COMN_PTR_TYPE_SGL);
 650                 ret = qat_sgl_fill_array(op->sym->m_src, src_buf_start,
 651                                 &cookie->qat_sgl_src,
 652                                 qat_req->comn_mid.src_length);
 653                 if (ret) {
 654                         PMD_DRV_LOG(ERR, "QAT PMD Cannot fill sgl array");
 655                         return ret;
 656                 }
 657
 658                 if (likely(op->sym->m_dst == NULL))
 659                         qat_req->comn_mid.dest_data_addr =
 660                                 qat_req->comn_mid.src_data_addr =
 661                                 cookie->qat_sgl_src_phys_addr;
 662                 else {
 663                         ret = qat_sgl_fill_array(op->sym->m_dst,
 664                                         dst_buf_start,
 665                                         &cookie->qat_sgl_dst,
 666                                                 qat_req->comn_mid.dst_length);
 667
 668                         if (ret) {
 669                                 PMD_DRV_LOG(ERR, "QAT PMD Cannot "
 670                                                 "fill sgl array");
 671                                 return ret;
 672                         }
 673
 674                         qat_req->comn_mid.src_data_addr =
 675                                 cookie->qat_sgl_src_phys_addr;
 676                         qat_req->comn_mid.dest_data_addr =
 677                                         cookie->qat_sgl_dst_phys_addr;
 678                 }
 679         } else {
 680                 qat_req->comn_mid.src_data_addr = src_buf_start;
 681                 qat_req->comn_mid.dest_data_addr = dst_buf_start;
 682         }
 683
 684 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX
 685         rte_hexdump(stdout, "qat_req:", qat_req,
 686                         sizeof(struct icp_qat_fw_la_bulk_req));
 687         rte_hexdump(stdout, "src_data:",
 688                         rte_pktmbuf_mtod(op->sym->m_src, uint8_t*),
 689                         rte_pktmbuf_data_len(op->sym->m_src));
 690         if (do_cipher) {
 691                 uint8_t *cipher_iv_ptr = rte_crypto_op_ctod_offset(op,
 692                                                 uint8_t *,
 693                                                 ctx->cipher_iv.offset);
 694                 rte_hexdump(stdout, "cipher iv:", cipher_iv_ptr,
 695                                 ctx->cipher_iv.length);
 696         }
 697
 698         if (do_auth) {
 699                 if (ctx->auth_iv.length) {
 700                         uint8_t *auth_iv_ptr = rte_crypto_op_ctod_offset(op,
 701                                                         uint8_t *,
 702                                                         ctx->auth_iv.offset);
 703                         rte_hexdump(stdout, "auth iv:", auth_iv_ptr,
 704                                                 ctx->auth_iv.length);
 705                 }
 706                 rte_hexdump(stdout, "digest:", op->sym->auth.digest.data,
 707                                 ctx->digest_length);
 708         }
 709
 710         if (do_aead) {
 711                 rte_hexdump(stdout, "digest:", op->sym->aead.digest.data,
 712                                 ctx->digest_length);
 713                 rte_hexdump(stdout, "aad:", op->sym->aead.aad.data,
 714                                 ctx->aad_len);
 715         }
 716 #endif
 717         return 0;
 718 }
 719
 720
 721 void qat_sym_stats_get(struct rte_cryptodev *dev,
 722                 struct rte_cryptodev_stats *stats)
 723 {
 724         int i;
 725         struct qat_qp **qp = (struct qat_qp **)(dev->data->queue_pairs);
 726
 727         PMD_INIT_FUNC_TRACE();
 728         if (stats == NULL) {
 729                 PMD_DRV_LOG(ERR, "invalid stats ptr NULL");
 730                 return;
 731         }
 732         for (i = 0; i < dev->data->nb_queue_pairs; i++) {
 733                 if (qp[i] == NULL) {
 734                         PMD_DRV_LOG(DEBUG, "Uninitialised queue pair");
 735                         continue;
 736                 }
 737
 738                 stats->enqueued_count += qp[i]->stats.enqueued_count;
 739                 stats->dequeued_count += qp[i]->stats.dequeued_count;
 740                 stats->enqueue_err_count += qp[i]->stats.enqueue_err_count;
 741                 stats->dequeue_err_count += qp[i]->stats.dequeue_err_count;
 742         }
 743 }
 744
 745 void qat_sym_stats_reset(struct rte_cryptodev *dev)
 746 {
 747         int i;
 748         struct qat_qp **qp = (struct qat_qp **)(dev->data->queue_pairs);
 749
 750         PMD_INIT_FUNC_TRACE();
 751         for (i = 0; i < dev->data->nb_queue_pairs; i++)
 752                 memset(&(qp[i]->stats), 0, sizeof(qp[i]->stats));
 753         PMD_DRV_LOG(DEBUG, "QAT crypto: stats cleared");
 754 }
 755
 756 int qat_sym_qp_release(struct rte_cryptodev *dev, uint16_t queue_pair_id)
 757 {
 758         PMD_DRV_LOG(DEBUG, "Release sym qp %u on device %d",
 759                                 queue_pair_id, dev->data->dev_id);
 760
 761         return qat_qp_release((struct qat_qp **)
 762                         &(dev->data->queue_pairs[queue_pair_id]));
 763 }
 764
 765 int qat_sym_qp_setup(struct rte_cryptodev *dev, uint16_t qp_id,
 766         const struct rte_cryptodev_qp_conf *qp_conf,
 767         int socket_id, struct rte_mempool *session_pool __rte_unused)
 768 {
 769         struct qat_qp *qp;
 770         int ret = 0;
 771         uint32_t i;
 772         struct qat_qp_config qat_qp_conf;
 773
 774         struct qat_qp **qp_addr =
 775                         (struct qat_qp **)&(dev->data->queue_pairs[qp_id]);
 776         struct qat_pmd_private *qat_private = dev->data->dev_private;
 777         const struct qat_qp_hw_data *sym_hw_qps =
 778                         qp_gen_config[qat_private->qat_dev_gen]
 779                                       .qp_hw_data[QAT_SERVICE_SYMMETRIC];
 780         const struct qat_qp_hw_data *qp_hw_data = sym_hw_qps + qp_id;
 781
 782         /* If qp is already in use free ring memory and qp metadata. */
 783         if (*qp_addr != NULL) {
 784                 ret = qat_sym_qp_release(dev, qp_id);
 785                 if (ret < 0)
 786                         return ret;
 787         }
 788         if (qp_id >= qat_qps_per_service(sym_hw_qps, QAT_SERVICE_SYMMETRIC)) {
 789                 PMD_DRV_LOG(ERR, "qp_id %u invalid for this device", qp_id);
 790                 return -EINVAL;
 791         }
 792
 793         qat_qp_conf.hw = qp_hw_data;
 794         qat_qp_conf.build_request = qat_sym_build_request;
 795         qat_qp_conf.process_response = qat_sym_process_response;
 796         qat_qp_conf.cookie_size = sizeof(struct qat_sym_op_cookie);
 797         qat_qp_conf.nb_descriptors = qp_conf->nb_descriptors;
 798         qat_qp_conf.socket_id = socket_id;
 799         qat_qp_conf.service_str = "sym";
 800
 801         ret = qat_qp_setup(qat_private, qp_addr, qp_id, &qat_qp_conf);
 802         if (ret != 0)
 803                 return ret;
 804
 805         qp = (struct qat_qp *)*qp_addr;
 806
 807         for (i = 0; i < qp->nb_descriptors; i++) {
 808
 809                 struct qat_sym_op_cookie *sql_cookie =
 810                                 qp->op_cookies[i];
 811
 812                 sql_cookie->qat_sgl_src_phys_addr =
 813                                 rte_mempool_virt2iova(sql_cookie) +
 814                                 offsetof(struct qat_sym_op_cookie,
 815                                 qat_sgl_src);
 816
 817                 sql_cookie->qat_sgl_dst_phys_addr =
 818                                 rte_mempool_virt2iova(sql_cookie) +
 819                                 offsetof(struct qat_sym_op_cookie,
 820                                 qat_sgl_dst);
 821         }
 822
 823         return ret;
 824 }