1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2016 - 2018 Cavium Inc.
8 #ifndef _QEDE_ETHDEV_H_
9 #define _QEDE_ETHDEV_H_
11 #include <sys/queue.h>
13 #include <rte_ether.h>
14 #include <rte_ethdev_driver.h>
15 #include <rte_ethdev_pci.h>
20 #include "base/bcm_osal.h"
21 #include "base/ecore.h"
22 #include "base/ecore_dev_api.h"
23 #include "base/ecore_l2_api.h"
24 #include "base/ecore_vf_api.h"
25 #include "base/ecore_hsi_common.h"
26 #include "base/ecore_int_api.h"
27 #include "base/ecore_chain.h"
28 #include "base/ecore_status.h"
29 #include "base/ecore_hsi_eth.h"
30 #include "base/ecore_iov_api.h"
31 #include "base/ecore_cxt.h"
32 #include "base/nvm_cfg.h"
33 #include "base/ecore_sp_commands.h"
34 #include "base/ecore_l2.h"
35 #include "base/ecore_vf.h"
37 #include "qede_sriov.h"
38 #include "qede_logs.h"
40 #include "qede_rxtx.h"
42 #define qede_stringify1(x...) #x
43 #define qede_stringify(x...) qede_stringify1(x)
46 #define QEDE_PMD_DRV_VER_STR_SIZE NAME_SIZE /* 128 */
47 #define QEDE_PMD_VER_PREFIX "QEDE PMD"
48 #define QEDE_PMD_VERSION_MAJOR 2
49 #define QEDE_PMD_VERSION_MINOR 11
50 #define QEDE_PMD_VERSION_REVISION 3
51 #define QEDE_PMD_VERSION_PATCH 1
53 #define QEDE_PMD_DRV_VERSION qede_stringify(QEDE_PMD_VERSION_MAJOR) "." \
54 qede_stringify(QEDE_PMD_VERSION_MINOR) "." \
55 qede_stringify(QEDE_PMD_VERSION_REVISION) "." \
56 qede_stringify(QEDE_PMD_VERSION_PATCH)
58 #define QEDE_PMD_BASE_VERSION qede_stringify(ECORE_MAJOR_VERSION) "." \
59 qede_stringify(ECORE_MINOR_VERSION) "." \
60 qede_stringify(ECORE_REVISION_VERSION) "." \
61 qede_stringify(ECORE_ENGINEERING_VERSION)
63 #define QEDE_PMD_FW_VERSION qede_stringify(FW_MAJOR_VERSION) "." \
64 qede_stringify(FW_MINOR_VERSION) "." \
65 qede_stringify(FW_REVISION_VERSION) "." \
66 qede_stringify(FW_ENGINEERING_VERSION)
68 #define QEDE_RSS_INDIR_INITED (1 << 0)
69 #define QEDE_RSS_KEY_INITED (1 << 1)
70 #define QEDE_RSS_CAPS_INITED (1 << 2)
72 #define QEDE_MAX_RSS_CNT(edev) ((edev)->dev_info.num_queues)
73 #define QEDE_MAX_TSS_CNT(edev) ((edev)->dev_info.num_queues * \
74 (edev)->dev_info.num_tc)
76 #define QEDE_QUEUE_CNT(qdev) ((qdev)->num_queues)
77 #define QEDE_RSS_COUNT(dev) ((dev)->data->nb_rx_queues)
78 #define QEDE_TSS_COUNT(dev) ((dev)->data->nb_tx_queues)
80 #define QEDE_DUPLEX_FULL 1
81 #define QEDE_DUPLEX_HALF 2
82 #define QEDE_DUPLEX_UNKNOWN 0xff
84 #define QEDE_SUPPORTED_AUTONEG (1 << 6)
85 #define QEDE_SUPPORTED_PAUSE (1 << 13)
87 #define QEDE_INIT_QDEV(eth_dev) (eth_dev->data->dev_private)
89 #define QEDE_INIT_EDEV(adapter) (&((struct qede_dev *)adapter)->edev)
91 #define QEDE_INIT(eth_dev) { \
92 struct qede_dev *qdev = eth_dev->data->dev_private; \
93 struct ecore_dev *edev = &qdev->edev; \
96 /************* QLogic 10G/25G/40G/50G/100G vendor/devices ids *************/
97 #define PCI_VENDOR_ID_QLOGIC 0x1077
99 #define CHIP_NUM_57980E 0x1634
100 #define CHIP_NUM_57980S 0x1629
101 #define CHIP_NUM_VF 0x1630
102 #define CHIP_NUM_57980S_40 0x1634
103 #define CHIP_NUM_57980S_25 0x1656
104 #define CHIP_NUM_57980S_IOV 0x1664
105 #define CHIP_NUM_57980S_100 0x1644
106 #define CHIP_NUM_57980S_50 0x1654
107 #define CHIP_NUM_AH_50G 0x8070
108 #define CHIP_NUM_AH_10G 0x8071
109 #define CHIP_NUM_AH_40G 0x8072
110 #define CHIP_NUM_AH_25G 0x8073
111 #define CHIP_NUM_AH_IOV 0x8090
113 #define PCI_DEVICE_ID_QLOGIC_NX2_57980E CHIP_NUM_57980E
114 #define PCI_DEVICE_ID_QLOGIC_NX2_57980S CHIP_NUM_57980S
115 #define PCI_DEVICE_ID_QLOGIC_NX2_VF CHIP_NUM_VF
116 #define PCI_DEVICE_ID_QLOGIC_57980S_40 CHIP_NUM_57980S_40
117 #define PCI_DEVICE_ID_QLOGIC_57980S_25 CHIP_NUM_57980S_25
118 #define PCI_DEVICE_ID_QLOGIC_57980S_IOV CHIP_NUM_57980S_IOV
119 #define PCI_DEVICE_ID_QLOGIC_57980S_100 CHIP_NUM_57980S_100
120 #define PCI_DEVICE_ID_QLOGIC_57980S_50 CHIP_NUM_57980S_50
121 #define PCI_DEVICE_ID_QLOGIC_AH_50G CHIP_NUM_AH_50G
122 #define PCI_DEVICE_ID_QLOGIC_AH_10G CHIP_NUM_AH_10G
123 #define PCI_DEVICE_ID_QLOGIC_AH_40G CHIP_NUM_AH_40G
124 #define PCI_DEVICE_ID_QLOGIC_AH_25G CHIP_NUM_AH_25G
125 #define PCI_DEVICE_ID_QLOGIC_AH_IOV CHIP_NUM_AH_IOV
129 extern char qede_fw_file[];
131 /* Number of PF connections - 32 RX + 32 TX */
132 #define QEDE_PF_NUM_CONNS (64)
134 /* Maximum number of flowdir filters */
135 #define QEDE_RFS_MAX_FLTR (256)
137 #define QEDE_MAX_MCAST_FILTERS (64)
139 enum qed_filter_rx_mode_type {
140 QED_FILTER_RX_MODE_TYPE_REGULAR,
141 QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC,
142 QED_FILTER_RX_MODE_TYPE_PROMISC,
145 struct qede_vlan_entry {
146 SLIST_ENTRY(qede_vlan_entry) list;
150 struct qede_mcast_entry {
151 struct rte_ether_addr mac;
152 SLIST_ENTRY(qede_mcast_entry) list;
155 struct qede_ucast_entry {
156 struct rte_ether_addr mac;
159 SLIST_ENTRY(qede_ucast_entry) list;
162 #ifndef IPV6_ADDR_LEN
163 #define IPV6_ADDR_LEN (16)
166 struct qede_arfs_tuple {
169 uint8_t src_ipv6[IPV6_ADDR_LEN];
174 uint8_t dst_ipv6[IPV6_ADDR_LEN];
182 /* Describe filtering mode needed for this kind of filter */
183 enum ecore_filter_config_mode mode;
186 struct qede_arfs_entry {
187 uint32_t soft_id; /* unused for now */
188 uint16_t pkt_len; /* actual packet length to match */
189 uint16_t rx_queue; /* queue to be steered to */
190 bool is_drop; /* drop action */
191 const struct rte_memzone *mz; /* mz used to hold L2 frame */
192 struct qede_arfs_tuple tuple;
193 SLIST_ENTRY(qede_arfs_entry) list;
196 /* Opaque handle for rte flow managed by PMD */
198 struct qede_arfs_entry entry;
201 struct qede_arfs_info {
202 struct ecore_arfs_config_params arfs;
203 uint16_t filter_count;
204 SLIST_HEAD(arfs_list_head, qede_arfs_entry)arfs_list_head;
207 /* IANA assigned default UDP ports for encapsulation protocols */
208 #define QEDE_VXLAN_DEF_PORT (4789)
209 #define QEDE_GENEVE_DEF_PORT (6081)
211 struct qede_tunn_params {
213 uint16_t num_filters;
214 uint16_t filter_type;
218 #define QEDE_FW_DUMP_FILE_SIZE 128
221 * Structure to store private data for each port.
224 struct ecore_dev edev;
225 const struct qed_eth_ops *ops;
226 struct qed_dev_eth_info dev_info;
227 struct ecore_sb_info *sb_array;
228 struct qede_fastpath *fp_array;
229 struct qede_fastpath_cmt *fp_array_cmt;
232 bool enable_tx_switching;
234 struct rte_eth_rss_conf rss_conf;
235 uint16_t rss_ind_table[ECORE_RSS_IND_TABLE_SIZE];
239 uint8_t num_rx_queues;
240 uint8_t num_tx_queues;
241 SLIST_HEAD(vlan_list_head, qede_vlan_entry)vlan_list_head;
242 uint16_t configured_vlans;
243 bool accept_any_vlan;
244 struct rte_ether_addr primary_mac;
245 SLIST_HEAD(mc_list_head, qede_mcast_entry) mc_list_head;
246 uint16_t num_mc_addr;
247 SLIST_HEAD(uc_list_head, qede_ucast_entry) uc_list_head;
248 uint16_t num_uc_addr;
250 struct qede_tunn_params vxlan;
251 struct qede_tunn_params geneve;
252 struct qede_tunn_params ipgre;
253 struct qede_arfs_info arfs_info;
255 char drv_ver[QEDE_PMD_DRV_VER_STR_SIZE];
257 int vlan_offload_mask;
258 char dump_file[QEDE_FW_DUMP_FILE_SIZE];
262 static inline void qede_set_ucast_cmn_params(struct ecore_filter_ucast *ucast)
264 memset(ucast, 0, sizeof(struct ecore_filter_ucast));
265 ucast->is_rx_filter = true;
266 ucast->is_tx_filter = true;
267 /* ucast->assert_on_error = true; - For debug */
271 /* Non-static functions */
272 int qede_config_rss(struct rte_eth_dev *eth_dev);
274 int qede_rss_hash_update(struct rte_eth_dev *eth_dev,
275 struct rte_eth_rss_conf *rss_conf);
277 int qede_rss_reta_update(struct rte_eth_dev *eth_dev,
278 struct rte_eth_rss_reta_entry64 *reta_conf,
281 int qed_fill_eth_dev_info(struct ecore_dev *edev,
282 struct qed_dev_eth_info *info);
283 int qede_dev_set_link_state(struct rte_eth_dev *eth_dev, bool link_up);
285 int qede_link_update(struct rte_eth_dev *eth_dev,
286 __rte_unused int wait_to_complete);
288 int qede_dev_filter_ctrl(struct rte_eth_dev *dev, enum rte_filter_type type,
289 enum rte_filter_op op, void *arg);
291 int qede_ntuple_filter_conf(struct rte_eth_dev *eth_dev,
292 enum rte_filter_op filter_op, void *arg);
294 int qede_check_fdir_support(struct rte_eth_dev *eth_dev);
296 uint16_t qede_fdir_construct_pkt(struct rte_eth_dev *eth_dev,
297 struct rte_eth_fdir_filter *fdir,
299 struct ecore_arfs_config_params *params);
301 void qede_fdir_dealloc_resc(struct rte_eth_dev *eth_dev);
303 int qede_activate_vport(struct rte_eth_dev *eth_dev, bool flg);
305 int qede_update_mtu(struct rte_eth_dev *eth_dev, uint16_t mtu);
307 int qede_enable_tpa(struct rte_eth_dev *eth_dev, bool flg);
308 int qede_udp_dst_port_del(struct rte_eth_dev *eth_dev,
309 struct rte_eth_udp_tunnel *tunnel_udp);
310 int qede_udp_dst_port_add(struct rte_eth_dev *eth_dev,
311 struct rte_eth_udp_tunnel *tunnel_udp);
314 qede_mac_int_ops(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast,
316 void qede_config_accept_any_vlan(struct qede_dev *qdev, bool flg);
317 int qede_ucast_filter(struct rte_eth_dev *eth_dev,
318 struct ecore_filter_ucast *ucast,
321 #define REGDUMP_HEADER_SIZE sizeof(u32)
322 #define REGDUMP_HEADER_FEATURE_SHIFT 24
323 #define REGDUMP_HEADER_ENGINE_SHIFT 31
324 #define REGDUMP_HEADER_OMIT_ENGINE_SHIFT 30
326 enum debug_print_features {
332 PROTECTION_OVERRIDE = 5,
338 int qede_get_regs_len(struct qede_dev *qdev);
339 int qede_get_regs(struct rte_eth_dev *dev, struct rte_dev_reg_info *regs);
340 void qede_config_rx_mode(struct rte_eth_dev *eth_dev);
341 void qed_dbg_dump(struct rte_eth_dev *eth_dev);
342 #endif /* _QEDE_ETHDEV_H_ */