1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2009-2018 Solarflare Communications Inc.
12 __checkReturn efx_rc_t
15 __out efx_link_mode_t *link_modep)
17 efx_port_t *epp = &(enp->en_port);
18 siena_link_state_t sls;
21 if ((rc = siena_phy_get_link(enp, &sls)) != 0)
24 epp->ep_adv_cap_mask = sls.sls_adv_cap_mask;
25 epp->ep_fcntl = sls.sls_fcntl;
27 *link_modep = sls.sls_link_mode;
32 EFSYS_PROBE1(fail1, efx_rc_t, rc);
34 *link_modep = EFX_LINK_UNKNOWN;
39 __checkReturn efx_rc_t
42 __out boolean_t *mac_upp)
44 siena_link_state_t sls;
48 * Because Siena doesn't *require* polling, we can't rely on
49 * siena_mac_poll() being executed to populate epp->ep_mac_up.
51 if ((rc = siena_phy_get_link(enp, &sls)) != 0)
54 *mac_upp = sls.sls_mac_up;
59 EFSYS_PROBE1(fail1, efx_rc_t, rc);
64 __checkReturn efx_rc_t
65 siena_mac_reconfigure(
68 efx_port_t *epp = &(enp->en_port);
69 efx_oword_t multicast_hash[2];
71 EFX_MCDI_DECLARE_BUF(payload,
72 MAX(MC_CMD_SET_MAC_IN_LEN, MC_CMD_SET_MCAST_HASH_IN_LEN),
73 MAX(MC_CMD_SET_MAC_OUT_LEN, MC_CMD_SET_MCAST_HASH_OUT_LEN));
78 req.emr_cmd = MC_CMD_SET_MAC;
79 req.emr_in_buf = payload;
80 req.emr_in_length = MC_CMD_SET_MAC_IN_LEN;
81 req.emr_out_buf = payload;
82 req.emr_out_length = MC_CMD_SET_MAC_OUT_LEN;
84 MCDI_IN_SET_DWORD(req, SET_MAC_IN_MTU, epp->ep_mac_pdu);
85 MCDI_IN_SET_DWORD(req, SET_MAC_IN_DRAIN, epp->ep_mac_drain ? 1 : 0);
86 EFX_MAC_ADDR_COPY(MCDI_IN2(req, uint8_t, SET_MAC_IN_ADDR),
88 MCDI_IN_POPULATE_DWORD_2(req, SET_MAC_IN_REJECT,
89 SET_MAC_IN_REJECT_UNCST, !epp->ep_all_unicst,
90 SET_MAC_IN_REJECT_BRDCST, !epp->ep_brdcst);
92 if (epp->ep_fcntl_autoneg)
93 /* efx_fcntl_set() has already set the phy capabilities */
94 fcntl = MC_CMD_FCNTL_AUTO;
95 else if (epp->ep_fcntl & EFX_FCNTL_RESPOND)
96 fcntl = (epp->ep_fcntl & EFX_FCNTL_GENERATE)
98 : MC_CMD_FCNTL_RESPOND;
100 fcntl = MC_CMD_FCNTL_OFF;
102 MCDI_IN_SET_DWORD(req, SET_MAC_IN_FCNTL, fcntl);
104 efx_mcdi_execute(enp, &req);
106 if (req.emr_rc != 0) {
111 /* Push multicast hash */
113 if (epp->ep_all_mulcst) {
114 /* A hash matching all multicast is all 1s */
115 EFX_SET_OWORD(multicast_hash[0]);
116 EFX_SET_OWORD(multicast_hash[1]);
117 } else if (epp->ep_mulcst) {
118 /* Use the hash set by the multicast list */
119 multicast_hash[0] = epp->ep_multicst_hash[0];
120 multicast_hash[1] = epp->ep_multicst_hash[1];
122 /* A hash matching no traffic is simply 0 */
123 EFX_ZERO_OWORD(multicast_hash[0]);
124 EFX_ZERO_OWORD(multicast_hash[1]);
128 * Broadcast packets go through the multicast hash filter.
129 * The IEEE 802.3 CRC32 of the broadcast address is 0xbe2612ff
130 * so we always add bit 0xff to the mask (bit 0x7f in the
133 if (epp->ep_brdcst) {
135 * NOTE: due to constant folding, some of this evaluates
136 * to null expressions, giving E_EXPR_NULL_EFFECT during
137 * lint on Illumos. No good way to fix this without
138 * explicit coding the individual word/bit setting.
139 * So just suppress lint for this one line.
142 EFX_SET_OWORD_BIT(multicast_hash[1], 0x7f);
145 (void) memset(payload, 0, sizeof (payload));
146 req.emr_cmd = MC_CMD_SET_MCAST_HASH;
147 req.emr_in_buf = payload;
148 req.emr_in_length = MC_CMD_SET_MCAST_HASH_IN_LEN;
149 req.emr_out_buf = payload;
150 req.emr_out_length = MC_CMD_SET_MCAST_HASH_OUT_LEN;
152 memcpy(MCDI_IN2(req, uint8_t, SET_MCAST_HASH_IN_HASH0),
153 multicast_hash, sizeof (multicast_hash));
155 efx_mcdi_execute(enp, &req);
157 if (req.emr_rc != 0) {
167 EFSYS_PROBE1(fail1, efx_rc_t, rc);
172 #if EFSYS_OPT_LOOPBACK
174 __checkReturn efx_rc_t
175 siena_mac_loopback_set(
177 __in efx_link_mode_t link_mode,
178 __in efx_loopback_type_t loopback_type)
180 efx_port_t *epp = &(enp->en_port);
181 const efx_phy_ops_t *epop = epp->ep_epop;
182 efx_loopback_type_t old_loopback_type;
183 efx_link_mode_t old_loopback_link_mode;
186 /* The PHY object handles this on Siena */
187 old_loopback_type = epp->ep_loopback_type;
188 old_loopback_link_mode = epp->ep_loopback_link_mode;
189 epp->ep_loopback_type = loopback_type;
190 epp->ep_loopback_link_mode = link_mode;
192 if ((rc = epop->epo_reconfigure(enp)) != 0)
198 EFSYS_PROBE1(fail1, efx_rc_t, rc);
200 epp->ep_loopback_type = old_loopback_type;
201 epp->ep_loopback_link_mode = old_loopback_link_mode;
206 #endif /* EFSYS_OPT_LOOPBACK */
208 #if EFSYS_OPT_MAC_STATS
210 __checkReturn efx_rc_t
211 siena_mac_stats_get_mask(
213 __inout_bcount(mask_size) uint32_t *maskp,
214 __in size_t mask_size)
216 const struct efx_mac_stats_range siena_stats[] = {
217 { EFX_MAC_RX_OCTETS, EFX_MAC_RX_GE_15XX_PKTS },
218 /* EFX_MAC_RX_ERRORS is not supported */
219 { EFX_MAC_RX_FCS_ERRORS, EFX_MAC_TX_EX_DEF_PKTS },
223 _NOTE(ARGUNUSED(enp))
225 if ((rc = efx_mac_stats_mask_add_ranges(maskp, mask_size,
226 siena_stats, EFX_ARRAY_SIZE(siena_stats))) != 0)
232 EFSYS_PROBE1(fail1, efx_rc_t, rc);
237 #define SIENA_MAC_STAT_READ(_esmp, _field, _eqp) \
238 EFSYS_MEM_READQ((_esmp), (_field) * sizeof (efx_qword_t), _eqp)
240 __checkReturn efx_rc_t
241 siena_mac_stats_update(
243 __in efsys_mem_t *esmp,
244 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat,
245 __inout_opt uint32_t *generationp)
247 const efx_nic_cfg_t *encp = &enp->en_nic_cfg;
248 efx_qword_t generation_start;
249 efx_qword_t generation_end;
253 if (encp->enc_mac_stats_nstats < MC_CMD_MAC_NSTATS) {
254 /* MAC stats count too small */
258 if (EFSYS_MEM_SIZE(esmp) <
259 (encp->enc_mac_stats_nstats * sizeof (efx_qword_t))) {
260 /* DMA buffer too small */
265 /* Read END first so we don't race with the MC */
266 EFSYS_DMA_SYNC_FOR_KERNEL(esmp, 0, EFSYS_MEM_SIZE(esmp));
267 SIENA_MAC_STAT_READ(esmp, (encp->enc_mac_stats_nstats - 1),
269 EFSYS_MEM_READ_BARRIER();
272 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_PKTS, &value);
273 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_PKTS]), &value);
274 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_CONTROL_PKTS, &value);
275 EFSYS_STAT_SUBR_QWORD(&(stat[EFX_MAC_TX_PKTS]), &value);
277 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_PAUSE_PKTS, &value);
278 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_PAUSE_PKTS]), &value);
280 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_UNICAST_PKTS, &value);
281 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_UNICST_PKTS]), &value);
283 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_MULTICAST_PKTS, &value);
284 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_MULTICST_PKTS]), &value);
286 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_BROADCAST_PKTS, &value);
287 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_BRDCST_PKTS]), &value);
289 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_BYTES, &value);
290 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_OCTETS]), &value);
292 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_LT64_PKTS, &value);
293 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_LE_64_PKTS]), &value);
294 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_64_PKTS, &value);
295 EFSYS_STAT_INCR_QWORD(&(stat[EFX_MAC_TX_LE_64_PKTS]), &value);
297 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_65_TO_127_PKTS, &value);
298 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_65_TO_127_PKTS]), &value);
300 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_128_TO_255_PKTS, &value);
301 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_128_TO_255_PKTS]), &value);
303 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_256_TO_511_PKTS, &value);
304 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_256_TO_511_PKTS]), &value);
306 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_512_TO_1023_PKTS, &value);
307 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_512_TO_1023_PKTS]), &value);
309 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_1024_TO_15XX_PKTS, &value);
310 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_1024_TO_15XX_PKTS]), &value);
312 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_15XX_TO_JUMBO_PKTS, &value);
313 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_GE_15XX_PKTS]), &value);
314 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_GTJUMBO_PKTS, &value);
315 EFSYS_STAT_INCR_QWORD(&(stat[EFX_MAC_TX_GE_15XX_PKTS]), &value);
317 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_BAD_FCS_PKTS, &value);
318 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_ERRORS]), &value);
320 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_SINGLE_COLLISION_PKTS, &value);
321 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_SGL_COL_PKTS]), &value);
323 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_MULTIPLE_COLLISION_PKTS,
325 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_MULT_COL_PKTS]), &value);
327 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_EXCESSIVE_COLLISION_PKTS,
329 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_EX_COL_PKTS]), &value);
331 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_LATE_COLLISION_PKTS, &value);
332 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_LATE_COL_PKTS]), &value);
334 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_DEFERRED_PKTS, &value);
335 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_DEF_PKTS]), &value);
337 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_EXCESSIVE_DEFERRED_PKTS,
339 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_EX_DEF_PKTS]), &value);
342 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_BYTES, &value);
343 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_OCTETS]), &value);
345 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_PKTS, &value);
346 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_PKTS]), &value);
348 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_UNICAST_PKTS, &value);
349 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_UNICST_PKTS]), &value);
351 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_MULTICAST_PKTS, &value);
352 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_MULTICST_PKTS]), &value);
354 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_BROADCAST_PKTS, &value);
355 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_BRDCST_PKTS]), &value);
357 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_PAUSE_PKTS, &value);
358 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_PAUSE_PKTS]), &value);
360 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_UNDERSIZE_PKTS, &value);
361 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_LE_64_PKTS]), &value);
362 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_64_PKTS, &value);
363 EFSYS_STAT_INCR_QWORD(&(stat[EFX_MAC_RX_LE_64_PKTS]), &value);
365 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_65_TO_127_PKTS, &value);
366 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_65_TO_127_PKTS]), &value);
368 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_128_TO_255_PKTS, &value);
369 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_128_TO_255_PKTS]), &value);
371 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_256_TO_511_PKTS, &value);
372 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_256_TO_511_PKTS]), &value);
374 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_512_TO_1023_PKTS, &value);
375 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_512_TO_1023_PKTS]), &value);
377 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_1024_TO_15XX_PKTS, &value);
378 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_1024_TO_15XX_PKTS]), &value);
380 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_15XX_TO_JUMBO_PKTS, &value);
381 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_GE_15XX_PKTS]), &value);
382 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_GTJUMBO_PKTS, &value);
383 EFSYS_STAT_INCR_QWORD(&(stat[EFX_MAC_RX_GE_15XX_PKTS]), &value);
385 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_BAD_FCS_PKTS, &value);
386 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_FCS_ERRORS]), &value);
388 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_OVERFLOW_PKTS, &value);
389 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_DROP_EVENTS]), &value);
391 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_FALSE_CARRIER_PKTS, &value);
392 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_FALSE_CARRIER_ERRORS]), &value);
394 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_SYMBOL_ERROR_PKTS, &value);
395 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_SYMBOL_ERRORS]), &value);
397 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_ALIGN_ERROR_PKTS, &value);
398 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_ALIGN_ERRORS]), &value);
400 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_INTERNAL_ERROR_PKTS, &value);
401 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_INTERNAL_ERRORS]), &value);
403 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_JABBER_PKTS, &value);
404 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_JABBER_PKTS]), &value);
406 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_LANES01_CHAR_ERR, &value);
407 EFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE0_CHAR_ERR]),
408 &(value.eq_dword[0]));
409 EFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE1_CHAR_ERR]),
410 &(value.eq_dword[1]));
412 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_LANES23_CHAR_ERR, &value);
413 EFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE2_CHAR_ERR]),
414 &(value.eq_dword[0]));
415 EFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE3_CHAR_ERR]),
416 &(value.eq_dword[1]));
418 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_LANES01_DISP_ERR, &value);
419 EFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE0_DISP_ERR]),
420 &(value.eq_dword[0]));
421 EFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE1_DISP_ERR]),
422 &(value.eq_dword[1]));
424 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_LANES23_DISP_ERR, &value);
425 EFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE2_DISP_ERR]),
426 &(value.eq_dword[0]));
427 EFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE3_DISP_ERR]),
428 &(value.eq_dword[1]));
430 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_MATCH_FAULT, &value);
431 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_MATCH_FAULT]), &value);
433 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_NODESC_DROPS, &value);
434 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_NODESC_DROP_CNT]), &value);
436 EFSYS_DMA_SYNC_FOR_KERNEL(esmp, 0, EFSYS_MEM_SIZE(esmp));
437 EFSYS_MEM_READ_BARRIER();
438 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_GENERATION_START,
441 /* Check that we didn't read the stats in the middle of a DMA */
442 /* Not a good enough check ? */
443 if (memcmp(&generation_start, &generation_end,
444 sizeof (generation_start)))
448 *generationp = EFX_QWORD_FIELD(generation_start, EFX_DWORD_0);
455 EFSYS_PROBE1(fail1, efx_rc_t, rc);
460 #endif /* EFSYS_OPT_MAC_STATS */
462 __checkReturn efx_rc_t
470 #endif /* EFSYS_OPT_SIENA */