1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2009-2018 Solarflare Communications Inc.
13 #if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM
15 static __checkReturn efx_rc_t
16 siena_nic_get_partn_mask(
18 __out unsigned int *maskp)
21 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_NVRAM_TYPES_IN_LEN,
22 MC_CMD_NVRAM_TYPES_OUT_LEN);
25 req.emr_cmd = MC_CMD_NVRAM_TYPES;
26 req.emr_in_buf = payload;
27 req.emr_in_length = MC_CMD_NVRAM_TYPES_IN_LEN;
28 req.emr_out_buf = payload;
29 req.emr_out_length = MC_CMD_NVRAM_TYPES_OUT_LEN;
31 efx_mcdi_execute(enp, &req);
33 if (req.emr_rc != 0) {
38 if (req.emr_out_length_used < MC_CMD_NVRAM_TYPES_OUT_LEN) {
43 *maskp = MCDI_OUT_DWORD(req, NVRAM_TYPES_OUT_TYPES);
50 EFSYS_PROBE1(fail1, efx_rc_t, rc);
55 #endif /* EFSYS_OPT_VPD || EFSYS_OPT_NVRAM */
57 static __checkReturn efx_rc_t
61 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
63 efx_dword_t capabilities;
65 uint32_t nevq, nrxq, ntxq;
68 /* Siena has a fixed 8Kbyte VI window size */
69 EFX_STATIC_ASSERT(1U << EFX_VI_WINDOW_SHIFT_8K == 8192);
70 encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_8K;
72 /* External port identifier using one-based port numbering */
73 encp->enc_external_port = (uint8_t)enp->en_mcdi.em_emip.emi_port;
75 /* Board configuration */
76 if ((rc = efx_mcdi_get_board_cfg(enp, &board_type,
77 &capabilities, mac_addr)) != 0)
80 EFX_MAC_ADDR_COPY(encp->enc_mac_addr, mac_addr);
82 encp->enc_board_type = board_type;
85 * There is no possibility to determine the number of PFs on Siena
86 * by issuing MCDI request, and it is not an easy task to find the
87 * value based on the board type, so 'enc_hw_pf_count' is set to 1
89 encp->enc_hw_pf_count = 1;
91 /* Additional capabilities */
92 encp->enc_clk_mult = 1;
93 if (EFX_DWORD_FIELD(capabilities, MC_CMD_CAPABILITIES_TURBO)) {
94 enp->en_features |= EFX_FEATURE_TURBO;
96 if (EFX_DWORD_FIELD(capabilities,
97 MC_CMD_CAPABILITIES_TURBO_ACTIVE)) {
98 encp->enc_clk_mult = 2;
102 encp->enc_evq_timer_quantum_ns =
103 EFX_EVQ_SIENA_TIMER_QUANTUM_NS / encp->enc_clk_mult;
104 encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns <<
105 FRF_CZ_TC_TIMER_VAL_WIDTH) / 1000;
107 encp->enc_ev_desc_size = SIENA_EVQ_DESC_SIZE;
108 encp->enc_rx_desc_size = SIENA_RXQ_DESC_SIZE;
109 encp->enc_tx_desc_size = SIENA_TXQ_DESC_SIZE;
111 /* When hash header insertion is enabled, Siena inserts 16 bytes */
112 encp->enc_rx_prefix_size = 16;
114 /* Alignment for receive packet DMA buffers */
115 encp->enc_rx_buf_align_start = 1;
116 encp->enc_rx_buf_align_end = 1;
118 /* Alignment for WPTR updates */
119 encp->enc_rx_push_align = 1;
121 #if EFSYS_OPT_RX_SCALE
122 /* There is one RSS context per function */
123 encp->enc_rx_scale_max_exclusive_contexts = 1;
125 encp->enc_rx_scale_hash_alg_mask |= (1U << EFX_RX_HASHALG_LFSR);
126 encp->enc_rx_scale_hash_alg_mask |= (1U << EFX_RX_HASHALG_TOEPLITZ);
129 * It is always possible to use port numbers
130 * as the input data for hash computation.
132 encp->enc_rx_scale_l4_hash_supported = B_TRUE;
134 /* There is no support for additional RSS modes */
135 encp->enc_rx_scale_additional_modes_supported = B_FALSE;
136 #endif /* EFSYS_OPT_RX_SCALE */
138 encp->enc_tx_dma_desc_size_max = EFX_MASK32(FSF_AZ_TX_KER_BYTE_COUNT);
139 /* Fragments must not span 4k boundaries. */
140 encp->enc_tx_dma_desc_boundary = 4096;
142 /* Resource limits */
143 rc = efx_mcdi_get_resource_limits(enp, &nevq, &nrxq, &ntxq);
149 nrxq = EFX_RXQ_LIMIT_TARGET;
150 ntxq = EFX_TXQ_LIMIT_TARGET;
152 encp->enc_evq_limit = nevq;
153 encp->enc_rxq_limit = MIN(EFX_RXQ_LIMIT_TARGET, nrxq);
154 encp->enc_txq_limit = MIN(EFX_TXQ_LIMIT_TARGET, ntxq);
156 encp->enc_evq_max_nevs = SIENA_EVQ_MAXNEVS;
157 encp->enc_evq_min_nevs = SIENA_EVQ_MINNEVS;
159 encp->enc_rxq_max_ndescs = EF10_RXQ_MAXNDESCS;
160 encp->enc_rxq_min_ndescs = EF10_RXQ_MINNDESCS;
162 encp->enc_txq_max_ndescs = SIENA_TXQ_MAXNDESCS;
163 encp->enc_txq_min_ndescs = SIENA_TXQ_MINNDESCS;
165 encp->enc_buftbl_limit = SIENA_SRAM_ROWS -
166 (encp->enc_txq_limit * EFX_TXQ_DC_NDESCS(EFX_TXQ_DC_SIZE)) -
167 (encp->enc_rxq_limit * EFX_RXQ_DC_NDESCS(EFX_RXQ_DC_SIZE));
169 encp->enc_hw_tx_insert_vlan_enabled = B_FALSE;
170 encp->enc_fw_assisted_tso_enabled = B_FALSE;
171 encp->enc_fw_assisted_tso_v2_enabled = B_FALSE;
172 encp->enc_fw_assisted_tso_v2_n_contexts = 0;
173 encp->enc_allow_set_mac_with_installed_filters = B_TRUE;
174 encp->enc_rx_packed_stream_supported = B_FALSE;
175 encp->enc_rx_var_packed_stream_supported = B_FALSE;
176 encp->enc_rx_es_super_buffer_supported = B_FALSE;
177 encp->enc_fw_subvariant_no_tx_csum_supported = B_FALSE;
179 /* Siena supports two 10G ports, and 8 lanes of PCIe Gen2 */
180 encp->enc_required_pcie_bandwidth_mbps = 2 * 10000;
181 encp->enc_max_pcie_link_gen = EFX_PCIE_LINK_SPEED_GEN2;
183 encp->enc_nvram_update_verify_result_supported = B_FALSE;
185 encp->enc_mac_stats_nstats = MC_CMD_MAC_NSTATS;
187 encp->enc_filter_action_flag_supported = B_FALSE;
188 encp->enc_filter_action_mark_supported = B_FALSE;
189 encp->enc_filter_action_mark_max = 0;
196 EFSYS_PROBE1(fail1, efx_rc_t, rc);
201 static __checkReturn efx_rc_t
205 #if EFSYS_OPT_PHY_STATS
206 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
207 #endif /* EFSYS_OPT_PHY_STATS */
210 /* Fill out fields in enp->en_port and enp->en_nic_cfg from MCDI */
211 if ((rc = efx_mcdi_get_phy_cfg(enp)) != 0)
214 #if EFSYS_OPT_PHY_STATS
215 /* Convert the MCDI statistic mask into the EFX_PHY_STAT mask */
216 siena_phy_decode_stats(enp, encp->enc_mcdi_phy_stat_mask,
217 NULL, &encp->enc_phy_stat_mask, NULL);
218 #endif /* EFSYS_OPT_PHY_STATS */
223 EFSYS_PROBE1(fail1, efx_rc_t, rc);
228 #define SIENA_BIU_MAGIC0 0x01234567
229 #define SIENA_BIU_MAGIC1 0xfedcba98
231 static __checkReturn efx_rc_t
239 * Write magic values to scratch registers 0 and 1, then
240 * verify that the values were written correctly. Interleave
241 * the accesses to ensure that the BIU is not just reading
242 * back the cached value that was last written.
244 EFX_POPULATE_OWORD_1(oword, FRF_AZ_DRIVER_DW0, SIENA_BIU_MAGIC0);
245 EFX_BAR_TBL_WRITEO(enp, FR_AZ_DRIVER_REG, 0, &oword, B_TRUE);
247 EFX_POPULATE_OWORD_1(oword, FRF_AZ_DRIVER_DW0, SIENA_BIU_MAGIC1);
248 EFX_BAR_TBL_WRITEO(enp, FR_AZ_DRIVER_REG, 1, &oword, B_TRUE);
250 EFX_BAR_TBL_READO(enp, FR_AZ_DRIVER_REG, 0, &oword, B_TRUE);
251 if (EFX_OWORD_FIELD(oword, FRF_AZ_DRIVER_DW0) != SIENA_BIU_MAGIC0) {
256 EFX_BAR_TBL_READO(enp, FR_AZ_DRIVER_REG, 1, &oword, B_TRUE);
257 if (EFX_OWORD_FIELD(oword, FRF_AZ_DRIVER_DW0) != SIENA_BIU_MAGIC1) {
263 * Perform the same test, with the values swapped. This
264 * ensures that subsequent tests don't start with the correct
265 * values already written into the scratch registers.
267 EFX_POPULATE_OWORD_1(oword, FRF_AZ_DRIVER_DW0, SIENA_BIU_MAGIC1);
268 EFX_BAR_TBL_WRITEO(enp, FR_AZ_DRIVER_REG, 0, &oword, B_TRUE);
270 EFX_POPULATE_OWORD_1(oword, FRF_AZ_DRIVER_DW0, SIENA_BIU_MAGIC0);
271 EFX_BAR_TBL_WRITEO(enp, FR_AZ_DRIVER_REG, 1, &oword, B_TRUE);
273 EFX_BAR_TBL_READO(enp, FR_AZ_DRIVER_REG, 0, &oword, B_TRUE);
274 if (EFX_OWORD_FIELD(oword, FRF_AZ_DRIVER_DW0) != SIENA_BIU_MAGIC1) {
279 EFX_BAR_TBL_READO(enp, FR_AZ_DRIVER_REG, 1, &oword, B_TRUE);
280 if (EFX_OWORD_FIELD(oword, FRF_AZ_DRIVER_DW0) != SIENA_BIU_MAGIC0) {
294 EFSYS_PROBE1(fail1, efx_rc_t, rc);
299 __checkReturn efx_rc_t
303 efx_port_t *epp = &(enp->en_port);
304 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
305 siena_link_state_t sls;
310 EFSYS_ASSERT3U(enp->en_family, ==, EFX_FAMILY_SIENA);
313 if ((rc = siena_nic_biu_test(enp)) != 0)
316 /* Clear the region register */
317 EFX_POPULATE_OWORD_4(oword,
318 FRF_AZ_ADR_REGION0, 0,
319 FRF_AZ_ADR_REGION1, (1 << 16),
320 FRF_AZ_ADR_REGION2, (2 << 16),
321 FRF_AZ_ADR_REGION3, (3 << 16));
322 EFX_BAR_WRITEO(enp, FR_AZ_ADR_REGION_REG, &oword);
324 /* Read clear any assertion state */
325 if ((rc = efx_mcdi_read_assertion(enp)) != 0)
328 /* Exit the assertion handler */
329 if ((rc = efx_mcdi_exit_assertion_handler(enp)) != 0)
332 /* Wrestle control from the BMC */
333 if ((rc = efx_mcdi_drv_attach(enp, B_TRUE)) != 0)
336 if ((rc = siena_board_cfg(enp)) != 0)
339 if ((rc = siena_phy_cfg(enp)) != 0)
342 /* Obtain the default PHY advertised capabilities */
343 if ((rc = siena_nic_reset(enp)) != 0)
345 if ((rc = siena_phy_get_link(enp, &sls)) != 0)
347 epp->ep_default_adv_cap_mask = sls.sls_adv_cap_mask;
348 epp->ep_adv_cap_mask = sls.sls_adv_cap_mask;
350 #if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM
351 if ((rc = siena_nic_get_partn_mask(enp, &mask)) != 0)
353 enp->en_u.siena.enu_partn_mask = mask;
356 #if EFSYS_OPT_MAC_STATS
357 /* Wipe the MAC statistics */
358 if ((rc = efx_mcdi_mac_stats_clear(enp)) != 0)
362 #if EFSYS_OPT_LOOPBACK
363 if ((rc = efx_mcdi_get_loopback_modes(enp)) != 0)
367 #if EFSYS_OPT_MON_STATS
368 if ((rc = mcdi_mon_cfg_build(enp)) != 0)
372 encp->enc_features = enp->en_features;
376 #if EFSYS_OPT_MON_STATS
380 #if EFSYS_OPT_LOOPBACK
384 #if EFSYS_OPT_MAC_STATS
388 #if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM
407 EFSYS_PROBE1(fail1, efx_rc_t, rc);
412 __checkReturn efx_rc_t
419 EFSYS_ASSERT3U(enp->en_family, ==, EFX_FAMILY_SIENA);
421 /* siena_nic_reset() is called to recover from BADASSERT failures. */
422 if ((rc = efx_mcdi_read_assertion(enp)) != 0)
424 if ((rc = efx_mcdi_exit_assertion_handler(enp)) != 0)
428 * Bug24908: ENTITY_RESET_IN_LEN is non zero but zero may be supplied
429 * for backwards compatibility with PORT_RESET_IN_LEN.
431 EFX_STATIC_ASSERT(MC_CMD_ENTITY_RESET_OUT_LEN == 0);
433 req.emr_cmd = MC_CMD_ENTITY_RESET;
434 req.emr_in_buf = NULL;
435 req.emr_in_length = 0;
436 req.emr_out_buf = NULL;
437 req.emr_out_length = 0;
439 efx_mcdi_execute(enp, &req);
441 if (req.emr_rc != 0) {
453 EFSYS_PROBE1(fail1, efx_rc_t, rc);
465 * RX_INGR_EN is always enabled on Siena, because we rely on
466 * the RX parser to be resiliant to missing SOP/EOP.
468 EFX_BAR_READO(enp, FR_AZ_RX_CFG_REG, &oword);
469 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_INGR_EN, 1);
470 EFX_BAR_WRITEO(enp, FR_AZ_RX_CFG_REG, &oword);
472 /* Disable parsing of additional 802.1Q in Q packets */
473 EFX_BAR_READO(enp, FR_AZ_RX_FILTER_CTL_REG, &oword);
474 EFX_SET_OWORD_FIELD(oword, FRF_CZ_RX_FILTER_ALL_VLAN_ETHERTYPES, 0);
475 EFX_BAR_WRITEO(enp, FR_AZ_RX_FILTER_CTL_REG, &oword);
484 EFX_POPULATE_OWORD_1(oword, FRF_CZ_USREV_DIS, 1);
485 EFX_BAR_WRITEO(enp, FR_CZ_USR_EV_CFG, &oword);
488 __checkReturn efx_rc_t
494 EFSYS_ASSERT3U(enp->en_family, ==, EFX_FAMILY_SIENA);
496 /* Enable reporting of some events (e.g. link change) */
497 if ((rc = efx_mcdi_log_ctrl(enp)) != 0)
500 siena_sram_init(enp);
502 /* Configure Siena's RX block */
503 siena_nic_rx_cfg(enp);
505 /* Disable USR_EVents for now */
506 siena_nic_usrev_dis(enp);
508 /* bug17057: Ensure set_link is called */
509 if ((rc = siena_phy_reconfigure(enp)) != 0)
512 enp->en_nic_cfg.enc_mcdi_max_payload_length = MCDI_CTL_SDU_LEN_MAX_V1;
519 EFSYS_PROBE1(fail1, efx_rc_t, rc);
528 _NOTE(ARGUNUSED(enp))
535 #if EFSYS_OPT_MON_STATS
536 mcdi_mon_cfg_free(enp);
537 #endif /* EFSYS_OPT_MON_STATS */
538 (void) efx_mcdi_drv_attach(enp, B_FALSE);
543 static siena_register_set_t __siena_registers[] = {
544 { FR_AZ_ADR_REGION_REG_OFST, 0, 1 },
545 { FR_CZ_USR_EV_CFG_OFST, 0, 1 },
546 { FR_AZ_RX_CFG_REG_OFST, 0, 1 },
547 { FR_AZ_TX_CFG_REG_OFST, 0, 1 },
548 { FR_AZ_TX_RESERVED_REG_OFST, 0, 1 },
549 { FR_AZ_SRM_TX_DC_CFG_REG_OFST, 0, 1 },
550 { FR_AZ_RX_DC_CFG_REG_OFST, 0, 1 },
551 { FR_AZ_RX_DC_PF_WM_REG_OFST, 0, 1 },
552 { FR_AZ_DP_CTRL_REG_OFST, 0, 1 },
553 { FR_BZ_RX_RSS_TKEY_REG_OFST, 0, 1},
554 { FR_CZ_RX_RSS_IPV6_REG1_OFST, 0, 1},
555 { FR_CZ_RX_RSS_IPV6_REG2_OFST, 0, 1},
556 { FR_CZ_RX_RSS_IPV6_REG3_OFST, 0, 1}
559 static const uint32_t __siena_register_masks[] = {
560 0x0003FFFF, 0x0003FFFF, 0x0003FFFF, 0x0003FFFF,
561 0x000103FF, 0x00000000, 0x00000000, 0x00000000,
562 0xFFFFFFFE, 0xFFFFFFFF, 0x0003FFFF, 0x00000000,
563 0x7FFF0037, 0xFFFF8000, 0xFFFFFFFF, 0x03FFFFFF,
564 0xFFFEFE80, 0x1FFFFFFF, 0x020000FE, 0x007FFFFF,
565 0x001FFFFF, 0x00000000, 0x00000000, 0x00000000,
566 0x00000003, 0x00000000, 0x00000000, 0x00000000,
567 0x000003FF, 0x00000000, 0x00000000, 0x00000000,
568 0x00000FFF, 0x00000000, 0x00000000, 0x00000000,
569 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
570 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
571 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
572 0xFFFFFFFF, 0xFFFFFFFF, 0x00000007, 0x00000000
575 static siena_register_set_t __siena_tables[] = {
576 { FR_AZ_RX_FILTER_TBL0_OFST, FR_AZ_RX_FILTER_TBL0_STEP,
577 FR_AZ_RX_FILTER_TBL0_ROWS },
578 { FR_CZ_RX_MAC_FILTER_TBL0_OFST, FR_CZ_RX_MAC_FILTER_TBL0_STEP,
579 FR_CZ_RX_MAC_FILTER_TBL0_ROWS },
580 { FR_AZ_RX_DESC_PTR_TBL_OFST,
581 FR_AZ_RX_DESC_PTR_TBL_STEP, FR_CZ_RX_DESC_PTR_TBL_ROWS },
582 { FR_AZ_TX_DESC_PTR_TBL_OFST,
583 FR_AZ_TX_DESC_PTR_TBL_STEP, FR_CZ_TX_DESC_PTR_TBL_ROWS },
584 { FR_AZ_TIMER_TBL_OFST, FR_AZ_TIMER_TBL_STEP, FR_CZ_TIMER_TBL_ROWS },
585 { FR_CZ_TX_FILTER_TBL0_OFST,
586 FR_CZ_TX_FILTER_TBL0_STEP, FR_CZ_TX_FILTER_TBL0_ROWS },
587 { FR_CZ_TX_MAC_FILTER_TBL0_OFST,
588 FR_CZ_TX_MAC_FILTER_TBL0_STEP, FR_CZ_TX_MAC_FILTER_TBL0_ROWS }
591 static const uint32_t __siena_table_masks[] = {
592 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x000003FF,
593 0xFFFF0FFF, 0xFFFFFFFF, 0x00000E7F, 0x00000000,
594 0xFFFFFFFE, 0x0FFFFFFF, 0x01800000, 0x00000000,
595 0xFFFFFFFE, 0x0FFFFFFF, 0x0C000000, 0x00000000,
596 0x3FFFFFFF, 0x00000000, 0x00000000, 0x00000000,
597 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x000013FF,
598 0xFFFF07FF, 0xFFFFFFFF, 0x0000007F, 0x00000000,
601 __checkReturn efx_rc_t
602 siena_nic_test_registers(
604 __in siena_register_set_t *rsp,
608 efx_oword_t original;
614 /* This function is only suitable for registers */
615 EFSYS_ASSERT(rsp->rows == 1);
617 /* bit sweep on and off */
618 EFSYS_BAR_READO(enp->en_esbp, rsp->address, &original,
620 for (bit = 0; bit < 128; bit++) {
621 /* Is this bit in the mask? */
622 if (~(rsp->mask.eo_u32[bit >> 5]) & (1 << bit))
625 /* Test this bit can be set in isolation */
627 EFX_AND_OWORD(reg, rsp->mask);
628 EFX_SET_OWORD_BIT(reg, bit);
630 EFSYS_BAR_WRITEO(enp->en_esbp, rsp->address, ®,
632 EFSYS_BAR_READO(enp->en_esbp, rsp->address, &buf,
635 EFX_AND_OWORD(buf, rsp->mask);
636 if (memcmp(®, &buf, sizeof (reg))) {
641 /* Test this bit can be cleared in isolation */
642 EFX_OR_OWORD(reg, rsp->mask);
643 EFX_CLEAR_OWORD_BIT(reg, bit);
645 EFSYS_BAR_WRITEO(enp->en_esbp, rsp->address, ®,
647 EFSYS_BAR_READO(enp->en_esbp, rsp->address, &buf,
650 EFX_AND_OWORD(buf, rsp->mask);
651 if (memcmp(®, &buf, sizeof (reg))) {
657 /* Restore the old value */
658 EFSYS_BAR_WRITEO(enp->en_esbp, rsp->address, &original,
670 EFSYS_PROBE1(fail1, efx_rc_t, rc);
672 /* Restore the old value */
673 EFSYS_BAR_WRITEO(enp->en_esbp, rsp->address, &original, B_TRUE);
678 __checkReturn efx_rc_t
679 siena_nic_test_tables(
681 __in siena_register_set_t *rsp,
682 __in efx_pattern_type_t pattern,
685 efx_sram_pattern_fn_t func;
687 unsigned int address;
692 EFSYS_ASSERT(pattern < EFX_PATTERN_NTYPES);
693 func = __efx_sram_pattern_fns[pattern];
697 address = rsp->address;
698 for (index = 0; index < rsp->rows; ++index) {
699 func(2 * index + 0, B_FALSE, ®.eo_qword[0]);
700 func(2 * index + 1, B_FALSE, ®.eo_qword[1]);
701 EFX_AND_OWORD(reg, rsp->mask);
702 EFSYS_BAR_WRITEO(enp->en_esbp, address, ®, B_TRUE);
704 address += rsp->step;
708 address = rsp->address;
709 for (index = 0; index < rsp->rows; ++index) {
710 func(2 * index + 0, B_FALSE, ®.eo_qword[0]);
711 func(2 * index + 1, B_FALSE, ®.eo_qword[1]);
712 EFX_AND_OWORD(reg, rsp->mask);
713 EFSYS_BAR_READO(enp->en_esbp, address, &buf, B_TRUE);
714 if (memcmp(®, &buf, sizeof (reg))) {
719 address += rsp->step;
729 EFSYS_PROBE1(fail1, efx_rc_t, rc);
735 __checkReturn efx_rc_t
736 siena_nic_register_test(
739 siena_register_set_t *rsp;
740 const uint32_t *dwordp;
745 /* Fill out the register mask entries */
746 EFX_STATIC_ASSERT(EFX_ARRAY_SIZE(__siena_register_masks)
747 == EFX_ARRAY_SIZE(__siena_registers) * 4);
749 nitems = EFX_ARRAY_SIZE(__siena_registers);
750 dwordp = __siena_register_masks;
751 for (count = 0; count < nitems; ++count) {
752 rsp = __siena_registers + count;
753 rsp->mask.eo_u32[0] = *dwordp++;
754 rsp->mask.eo_u32[1] = *dwordp++;
755 rsp->mask.eo_u32[2] = *dwordp++;
756 rsp->mask.eo_u32[3] = *dwordp++;
759 /* Fill out the register table entries */
760 EFX_STATIC_ASSERT(EFX_ARRAY_SIZE(__siena_table_masks)
761 == EFX_ARRAY_SIZE(__siena_tables) * 4);
763 nitems = EFX_ARRAY_SIZE(__siena_tables);
764 dwordp = __siena_table_masks;
765 for (count = 0; count < nitems; ++count) {
766 rsp = __siena_tables + count;
767 rsp->mask.eo_u32[0] = *dwordp++;
768 rsp->mask.eo_u32[1] = *dwordp++;
769 rsp->mask.eo_u32[2] = *dwordp++;
770 rsp->mask.eo_u32[3] = *dwordp++;
773 if ((rc = siena_nic_test_registers(enp, __siena_registers,
774 EFX_ARRAY_SIZE(__siena_registers))) != 0)
777 if ((rc = siena_nic_test_tables(enp, __siena_tables,
778 EFX_PATTERN_BYTE_ALTERNATE,
779 EFX_ARRAY_SIZE(__siena_tables))) != 0)
782 if ((rc = siena_nic_test_tables(enp, __siena_tables,
783 EFX_PATTERN_BYTE_CHANGING,
784 EFX_ARRAY_SIZE(__siena_tables))) != 0)
787 if ((rc = siena_nic_test_tables(enp, __siena_tables,
788 EFX_PATTERN_BIT_SWEEP, EFX_ARRAY_SIZE(__siena_tables))) != 0)
800 EFSYS_PROBE1(fail1, efx_rc_t, rc);
805 #endif /* EFSYS_OPT_DIAG */
807 #endif /* EFSYS_OPT_SIENA */