1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Chelsio Communications.
6 #ifndef _T4FW_INTERFACE_H_
7 #define _T4FW_INTERFACE_H_
9 /******************************************************************************
10 * R E T U R N V A L U E S
11 ********************************/
14 FW_SUCCESS = 0, /* completed successfully */
15 FW_EPERM = 1, /* operation not permitted */
16 FW_ENOENT = 2, /* no such file or directory */
17 FW_EIO = 5, /* input/output error; hw bad */
18 FW_ENOEXEC = 8, /* exec format error; inv microcode */
19 FW_EAGAIN = 11, /* try again */
20 FW_ENOMEM = 12, /* out of memory */
21 FW_EFAULT = 14, /* bad address; fw bad */
22 FW_EBUSY = 16, /* resource busy */
23 FW_EEXIST = 17, /* file exists */
24 FW_ENODEV = 19, /* no such device */
25 FW_EINVAL = 22, /* invalid argument */
26 FW_ENOSPC = 28, /* no space left on device */
27 FW_ENOSYS = 38, /* functionality not implemented */
28 FW_ENODATA = 61, /* no data available */
29 FW_EPROTO = 71, /* protocol error */
30 FW_EADDRINUSE = 98, /* address already in use */
31 FW_EADDRNOTAVAIL = 99, /* cannot assigned requested address */
32 FW_ENETDOWN = 100, /* network is down */
33 FW_ENETUNREACH = 101, /* network is unreachable */
34 FW_ENOBUFS = 105, /* no buffer space available */
35 FW_ETIMEDOUT = 110, /* timeout */
36 FW_EINPROGRESS = 115, /* fw internal */
39 /******************************************************************************
40 * M E M O R Y T Y P E s
41 ******************************/
44 FW_MEMTYPE_EDC0 = 0x0,
45 FW_MEMTYPE_EDC1 = 0x1,
46 FW_MEMTYPE_EXTMEM = 0x2,
47 FW_MEMTYPE_FLASH = 0x4,
48 FW_MEMTYPE_INTERNAL = 0x5,
49 FW_MEMTYPE_EXTMEM1 = 0x6,
52 /******************************************************************************
53 * W O R K R E Q U E S T s
54 ********************************/
60 FW_ETH_TX_PKT_WR = 0x08,
61 FW_ETH_TX_PKTS_WR = 0x09,
62 FW_ETH_TX_PKT_VM_WR = 0x11,
63 FW_ETH_TX_PKTS_VM_WR = 0x12,
65 FW_ETH_TX_PKTS2_WR = 0x78,
69 * Generic work request header flit0
76 /* work request opcode (hi)
79 #define M_FW_WR_OP 0xff
80 #define V_FW_WR_OP(x) ((x) << S_FW_WR_OP)
81 #define G_FW_WR_OP(x) (((x) >> S_FW_WR_OP) & M_FW_WR_OP)
83 /* atomic flag (hi) - firmware encapsulates CPLs in CPL_BARRIER
85 #define S_FW_WR_ATOMIC 23
86 #define V_FW_WR_ATOMIC(x) ((x) << S_FW_WR_ATOMIC)
88 /* work request immediate data length (hi)
90 #define S_FW_WR_IMMDLEN 0
91 #define M_FW_WR_IMMDLEN 0xff
92 #define V_FW_WR_IMMDLEN(x) ((x) << S_FW_WR_IMMDLEN)
93 #define G_FW_WR_IMMDLEN(x) \
94 (((x) >> S_FW_WR_IMMDLEN) & M_FW_WR_IMMDLEN)
96 /* egress queue status update to egress queue status entry (lo)
98 #define S_FW_WR_EQUEQ 30
99 #define M_FW_WR_EQUEQ 0x1
100 #define V_FW_WR_EQUEQ(x) ((x) << S_FW_WR_EQUEQ)
101 #define G_FW_WR_EQUEQ(x) (((x) >> S_FW_WR_EQUEQ) & M_FW_WR_EQUEQ)
102 #define F_FW_WR_EQUEQ V_FW_WR_EQUEQ(1U)
104 /* flow context identifier (lo)
106 #define S_FW_WR_FLOWID 8
107 #define V_FW_WR_FLOWID(x) ((x) << S_FW_WR_FLOWID)
109 /* length in units of 16-bytes (lo)
111 #define S_FW_WR_LEN16 0
112 #define M_FW_WR_LEN16 0xff
113 #define V_FW_WR_LEN16(x) ((x) << S_FW_WR_LEN16)
114 #define G_FW_WR_LEN16(x) (((x) >> S_FW_WR_LEN16) & M_FW_WR_LEN16)
116 struct fw_eth_tx_pkt_wr {
118 __be32 equiq_to_len16;
122 #define S_FW_ETH_TX_PKT_WR_IMMDLEN 0
123 #define M_FW_ETH_TX_PKT_WR_IMMDLEN 0x1ff
124 #define V_FW_ETH_TX_PKT_WR_IMMDLEN(x) ((x) << S_FW_ETH_TX_PKT_WR_IMMDLEN)
125 #define G_FW_ETH_TX_PKT_WR_IMMDLEN(x) \
126 (((x) >> S_FW_ETH_TX_PKT_WR_IMMDLEN) & M_FW_ETH_TX_PKT_WR_IMMDLEN)
128 struct fw_eth_tx_pkts_wr {
130 __be32 equiq_to_len16;
137 struct fw_eth_tx_pkt_vm_wr {
139 __be32 equiq_to_len16;
147 struct fw_eth_tx_pkts_vm_wr {
149 __be32 equiq_to_len16;
160 /* filter wr reply code in cookie in CPL_SET_TCB_RPL */
161 enum fw_filter_wr_cookie {
162 FW_FILTER_WR_SUCCESS,
163 FW_FILTER_WR_FLT_ADDED,
164 FW_FILTER_WR_FLT_DELETED,
165 FW_FILTER_WR_SMT_TBL_FULL,
169 struct fw_filter2_wr {
174 __be32 del_filter_to_l2tix;
177 __u8 frag_to_ovlan_vldm;
179 __be16 rx_chan_rx_rpl_iq;
180 __be32 maci_to_matchtypem;
200 __u8 filter_type_swapmac;
201 __u8 natmode_to_ulp_type;
214 #define S_FW_FILTER_WR_TID 12
215 #define V_FW_FILTER_WR_TID(x) ((x) << S_FW_FILTER_WR_TID)
217 #define S_FW_FILTER_WR_RQTYPE 11
218 #define V_FW_FILTER_WR_RQTYPE(x) ((x) << S_FW_FILTER_WR_RQTYPE)
220 #define S_FW_FILTER_WR_NOREPLY 10
221 #define V_FW_FILTER_WR_NOREPLY(x) ((x) << S_FW_FILTER_WR_NOREPLY)
223 #define S_FW_FILTER_WR_IQ 0
224 #define V_FW_FILTER_WR_IQ(x) ((x) << S_FW_FILTER_WR_IQ)
226 #define S_FW_FILTER_WR_DEL_FILTER 31
227 #define V_FW_FILTER_WR_DEL_FILTER(x) ((x) << S_FW_FILTER_WR_DEL_FILTER)
228 #define F_FW_FILTER_WR_DEL_FILTER V_FW_FILTER_WR_DEL_FILTER(1U)
230 #define S_FW_FILTER_WR_RPTTID 25
231 #define V_FW_FILTER_WR_RPTTID(x) ((x) << S_FW_FILTER_WR_RPTTID)
233 #define S_FW_FILTER_WR_DROP 24
234 #define V_FW_FILTER_WR_DROP(x) ((x) << S_FW_FILTER_WR_DROP)
236 #define S_FW_FILTER_WR_DIRSTEER 23
237 #define V_FW_FILTER_WR_DIRSTEER(x) ((x) << S_FW_FILTER_WR_DIRSTEER)
239 #define S_FW_FILTER_WR_MASKHASH 22
240 #define V_FW_FILTER_WR_MASKHASH(x) ((x) << S_FW_FILTER_WR_MASKHASH)
242 #define S_FW_FILTER_WR_DIRSTEERHASH 21
243 #define V_FW_FILTER_WR_DIRSTEERHASH(x) ((x) << S_FW_FILTER_WR_DIRSTEERHASH)
245 #define S_FW_FILTER_WR_LPBK 20
246 #define V_FW_FILTER_WR_LPBK(x) ((x) << S_FW_FILTER_WR_LPBK)
248 #define S_FW_FILTER_WR_DMAC 19
249 #define V_FW_FILTER_WR_DMAC(x) ((x) << S_FW_FILTER_WR_DMAC)
251 #define S_FW_FILTER_WR_SMAC 18
252 #define V_FW_FILTER_WR_SMAC(x) ((x) << S_FW_FILTER_WR_SMAC)
254 #define S_FW_FILTER_WR_INSVLAN 17
255 #define V_FW_FILTER_WR_INSVLAN(x) ((x) << S_FW_FILTER_WR_INSVLAN)
257 #define S_FW_FILTER_WR_RMVLAN 16
258 #define V_FW_FILTER_WR_RMVLAN(x) ((x) << S_FW_FILTER_WR_RMVLAN)
260 #define S_FW_FILTER_WR_HITCNTS 15
261 #define V_FW_FILTER_WR_HITCNTS(x) ((x) << S_FW_FILTER_WR_HITCNTS)
263 #define S_FW_FILTER_WR_TXCHAN 13
264 #define V_FW_FILTER_WR_TXCHAN(x) ((x) << S_FW_FILTER_WR_TXCHAN)
266 #define S_FW_FILTER_WR_PRIO 12
267 #define V_FW_FILTER_WR_PRIO(x) ((x) << S_FW_FILTER_WR_PRIO)
269 #define S_FW_FILTER_WR_L2TIX 0
270 #define V_FW_FILTER_WR_L2TIX(x) ((x) << S_FW_FILTER_WR_L2TIX)
272 #define S_FW_FILTER_WR_FRAG 7
273 #define V_FW_FILTER_WR_FRAG(x) ((x) << S_FW_FILTER_WR_FRAG)
275 #define S_FW_FILTER_WR_FRAGM 6
276 #define V_FW_FILTER_WR_FRAGM(x) ((x) << S_FW_FILTER_WR_FRAGM)
278 #define S_FW_FILTER_WR_IVLAN_VLD 5
279 #define V_FW_FILTER_WR_IVLAN_VLD(x) ((x) << S_FW_FILTER_WR_IVLAN_VLD)
281 #define S_FW_FILTER_WR_OVLAN_VLD 4
282 #define V_FW_FILTER_WR_OVLAN_VLD(x) ((x) << S_FW_FILTER_WR_OVLAN_VLD)
284 #define S_FW_FILTER_WR_IVLAN_VLDM 3
285 #define V_FW_FILTER_WR_IVLAN_VLDM(x) ((x) << S_FW_FILTER_WR_IVLAN_VLDM)
287 #define S_FW_FILTER_WR_OVLAN_VLDM 2
288 #define V_FW_FILTER_WR_OVLAN_VLDM(x) ((x) << S_FW_FILTER_WR_OVLAN_VLDM)
290 #define S_FW_FILTER_WR_RX_CHAN 15
291 #define V_FW_FILTER_WR_RX_CHAN(x) ((x) << S_FW_FILTER_WR_RX_CHAN)
293 #define S_FW_FILTER_WR_RX_RPL_IQ 0
294 #define V_FW_FILTER_WR_RX_RPL_IQ(x) ((x) << S_FW_FILTER_WR_RX_RPL_IQ)
296 #define S_FW_FILTER_WR_MACI 23
297 #define V_FW_FILTER_WR_MACI(x) ((x) << S_FW_FILTER_WR_MACI)
299 #define S_FW_FILTER_WR_MACIM 14
300 #define V_FW_FILTER_WR_MACIM(x) ((x) << S_FW_FILTER_WR_MACIM)
302 #define S_FW_FILTER_WR_FCOE 13
303 #define V_FW_FILTER_WR_FCOE(x) ((x) << S_FW_FILTER_WR_FCOE)
305 #define S_FW_FILTER_WR_FCOEM 12
306 #define V_FW_FILTER_WR_FCOEM(x) ((x) << S_FW_FILTER_WR_FCOEM)
308 #define S_FW_FILTER_WR_PORT 9
309 #define V_FW_FILTER_WR_PORT(x) ((x) << S_FW_FILTER_WR_PORT)
311 #define S_FW_FILTER_WR_PORTM 6
312 #define V_FW_FILTER_WR_PORTM(x) ((x) << S_FW_FILTER_WR_PORTM)
314 #define S_FW_FILTER_WR_MATCHTYPE 3
315 #define V_FW_FILTER_WR_MATCHTYPE(x) ((x) << S_FW_FILTER_WR_MATCHTYPE)
317 #define S_FW_FILTER_WR_MATCHTYPEM 0
318 #define V_FW_FILTER_WR_MATCHTYPEM(x) ((x) << S_FW_FILTER_WR_MATCHTYPEM)
320 #define S_FW_FILTER2_WR_SWAPMAC 0
321 #define V_FW_FILTER2_WR_SWAPMAC(x) ((x) << S_FW_FILTER2_WR_SWAPMAC)
323 #define S_FW_FILTER2_WR_NATMODE 5
324 #define V_FW_FILTER2_WR_NATMODE(x) ((x) << S_FW_FILTER2_WR_NATMODE)
326 #define S_FW_FILTER2_WR_ULP_TYPE 0
327 #define V_FW_FILTER2_WR_ULP_TYPE(x) ((x) << S_FW_FILTER2_WR_ULP_TYPE)
329 /******************************************************************************
331 *********************/
334 * The maximum length of time, in miliseconds, that we expect any firmware
335 * command to take to execute and return a reply to the host. The RESET
336 * and INITIALIZE commands can take a fair amount of time to execute but
337 * most execute in far less time than this maximum. This constant is used
338 * by host software to determine how long to wait for a firmware command
339 * reply before declaring the firmware as dead/unreachable ...
341 #define FW_CMD_MAX_TIMEOUT 10000
344 * If a host driver does a HELLO and discovers that there's already a MASTER
345 * selected, we may have to wait for that MASTER to finish issuing RESET,
346 * configuration and INITIALIZE commands. Also, there's a possibility that
347 * our own HELLO may get lost if it happens right as the MASTER is issuign a
348 * RESET command, so we need to be willing to make a few retries of our HELLO.
350 #define FW_CMD_HELLO_TIMEOUT (3 * FW_CMD_MAX_TIMEOUT)
351 #define FW_CMD_HELLO_RETRIES 3
353 enum fw_cmd_opcodes {
358 FW_INITIALIZE_CMD = 0x06,
359 FW_CAPS_CONFIG_CMD = 0x07,
360 FW_PARAMS_CMD = 0x08,
363 FW_EQ_ETH_CMD = 0x12,
364 FW_EQ_CTRL_CMD = 0x13,
366 FW_VI_MAC_CMD = 0x15,
367 FW_VI_RXMODE_CMD = 0x16,
368 FW_VI_ENABLE_CMD = 0x17,
369 FW_VI_STATS_CMD = 0x1a,
371 FW_RSS_IND_TBL_CMD = 0x20,
372 FW_RSS_GLB_CONFIG_CMD = 0x22,
373 FW_RSS_VI_CONFIG_CMD = 0x23,
379 FW_CMD_CAP_PORT = 0x04,
383 * Generic command header flit0
390 #define S_FW_CMD_OP 24
391 #define M_FW_CMD_OP 0xff
392 #define V_FW_CMD_OP(x) ((x) << S_FW_CMD_OP)
393 #define G_FW_CMD_OP(x) (((x) >> S_FW_CMD_OP) & M_FW_CMD_OP)
395 #define S_FW_CMD_REQUEST 23
396 #define M_FW_CMD_REQUEST 0x1
397 #define V_FW_CMD_REQUEST(x) ((x) << S_FW_CMD_REQUEST)
398 #define G_FW_CMD_REQUEST(x) (((x) >> S_FW_CMD_REQUEST) & M_FW_CMD_REQUEST)
399 #define F_FW_CMD_REQUEST V_FW_CMD_REQUEST(1U)
401 #define S_FW_CMD_READ 22
402 #define M_FW_CMD_READ 0x1
403 #define V_FW_CMD_READ(x) ((x) << S_FW_CMD_READ)
404 #define G_FW_CMD_READ(x) (((x) >> S_FW_CMD_READ) & M_FW_CMD_READ)
405 #define F_FW_CMD_READ V_FW_CMD_READ(1U)
407 #define S_FW_CMD_WRITE 21
408 #define M_FW_CMD_WRITE 0x1
409 #define V_FW_CMD_WRITE(x) ((x) << S_FW_CMD_WRITE)
410 #define G_FW_CMD_WRITE(x) (((x) >> S_FW_CMD_WRITE) & M_FW_CMD_WRITE)
411 #define F_FW_CMD_WRITE V_FW_CMD_WRITE(1U)
413 #define S_FW_CMD_EXEC 20
414 #define M_FW_CMD_EXEC 0x1
415 #define V_FW_CMD_EXEC(x) ((x) << S_FW_CMD_EXEC)
416 #define G_FW_CMD_EXEC(x) (((x) >> S_FW_CMD_EXEC) & M_FW_CMD_EXEC)
417 #define F_FW_CMD_EXEC V_FW_CMD_EXEC(1U)
419 #define S_FW_CMD_RETVAL 8
420 #define M_FW_CMD_RETVAL 0xff
421 #define V_FW_CMD_RETVAL(x) ((x) << S_FW_CMD_RETVAL)
422 #define G_FW_CMD_RETVAL(x) (((x) >> S_FW_CMD_RETVAL) & M_FW_CMD_RETVAL)
424 #define S_FW_CMD_LEN16 0
425 #define M_FW_CMD_LEN16 0xff
426 #define V_FW_CMD_LEN16(x) ((x) << S_FW_CMD_LEN16)
427 #define G_FW_CMD_LEN16(x) (((x) >> S_FW_CMD_LEN16) & M_FW_CMD_LEN16)
429 #define FW_LEN16(fw_struct) V_FW_CMD_LEN16(sizeof(fw_struct) / 16)
433 enum fw_ldst_addrspc {
434 FW_LDST_ADDRSPC_TP_PIO = 0x0010,
438 __be32 op_to_addrspace;
439 __be32 cycles_to_len16;
441 struct fw_ldst_addrval {
445 struct fw_ldst_idctxt {
447 __be32 msg_ctxtflush;
457 struct fw_ldst_mdio {
473 struct fw_ldst_func {
481 struct fw_ldst_pcie {
491 struct fw_ldst_i2c_deprecated {
515 #define S_FW_LDST_CMD_ADDRSPACE 0
516 #define M_FW_LDST_CMD_ADDRSPACE 0xff
517 #define V_FW_LDST_CMD_ADDRSPACE(x) ((x) << S_FW_LDST_CMD_ADDRSPACE)
519 struct fw_reset_cmd {
526 #define S_FW_RESET_CMD_HALT 31
527 #define M_FW_RESET_CMD_HALT 0x1
528 #define V_FW_RESET_CMD_HALT(x) ((x) << S_FW_RESET_CMD_HALT)
529 #define G_FW_RESET_CMD_HALT(x) \
530 (((x) >> S_FW_RESET_CMD_HALT) & M_FW_RESET_CMD_HALT)
531 #define F_FW_RESET_CMD_HALT V_FW_RESET_CMD_HALT(1U)
534 FW_HELLO_CMD_STAGE_OS = 0,
537 struct fw_hello_cmd {
540 __be32 err_to_clearinit;
544 #define S_FW_HELLO_CMD_ERR 31
545 #define M_FW_HELLO_CMD_ERR 0x1
546 #define V_FW_HELLO_CMD_ERR(x) ((x) << S_FW_HELLO_CMD_ERR)
547 #define G_FW_HELLO_CMD_ERR(x) \
548 (((x) >> S_FW_HELLO_CMD_ERR) & M_FW_HELLO_CMD_ERR)
549 #define F_FW_HELLO_CMD_ERR V_FW_HELLO_CMD_ERR(1U)
551 #define S_FW_HELLO_CMD_INIT 30
552 #define M_FW_HELLO_CMD_INIT 0x1
553 #define V_FW_HELLO_CMD_INIT(x) ((x) << S_FW_HELLO_CMD_INIT)
554 #define G_FW_HELLO_CMD_INIT(x) \
555 (((x) >> S_FW_HELLO_CMD_INIT) & M_FW_HELLO_CMD_INIT)
556 #define F_FW_HELLO_CMD_INIT V_FW_HELLO_CMD_INIT(1U)
558 #define S_FW_HELLO_CMD_MASTERDIS 29
559 #define M_FW_HELLO_CMD_MASTERDIS 0x1
560 #define V_FW_HELLO_CMD_MASTERDIS(x) ((x) << S_FW_HELLO_CMD_MASTERDIS)
561 #define G_FW_HELLO_CMD_MASTERDIS(x) \
562 (((x) >> S_FW_HELLO_CMD_MASTERDIS) & M_FW_HELLO_CMD_MASTERDIS)
563 #define F_FW_HELLO_CMD_MASTERDIS V_FW_HELLO_CMD_MASTERDIS(1U)
565 #define S_FW_HELLO_CMD_MASTERFORCE 28
566 #define M_FW_HELLO_CMD_MASTERFORCE 0x1
567 #define V_FW_HELLO_CMD_MASTERFORCE(x) ((x) << S_FW_HELLO_CMD_MASTERFORCE)
568 #define G_FW_HELLO_CMD_MASTERFORCE(x) \
569 (((x) >> S_FW_HELLO_CMD_MASTERFORCE) & M_FW_HELLO_CMD_MASTERFORCE)
570 #define F_FW_HELLO_CMD_MASTERFORCE V_FW_HELLO_CMD_MASTERFORCE(1U)
572 #define S_FW_HELLO_CMD_MBMASTER 24
573 #define M_FW_HELLO_CMD_MBMASTER 0xf
574 #define V_FW_HELLO_CMD_MBMASTER(x) ((x) << S_FW_HELLO_CMD_MBMASTER)
575 #define G_FW_HELLO_CMD_MBMASTER(x) \
576 (((x) >> S_FW_HELLO_CMD_MBMASTER) & M_FW_HELLO_CMD_MBMASTER)
578 #define S_FW_HELLO_CMD_MBASYNCNOT 20
579 #define M_FW_HELLO_CMD_MBASYNCNOT 0x7
580 #define V_FW_HELLO_CMD_MBASYNCNOT(x) ((x) << S_FW_HELLO_CMD_MBASYNCNOT)
581 #define G_FW_HELLO_CMD_MBASYNCNOT(x) \
582 (((x) >> S_FW_HELLO_CMD_MBASYNCNOT) & M_FW_HELLO_CMD_MBASYNCNOT)
584 #define S_FW_HELLO_CMD_STAGE 17
585 #define M_FW_HELLO_CMD_STAGE 0x7
586 #define V_FW_HELLO_CMD_STAGE(x) ((x) << S_FW_HELLO_CMD_STAGE)
587 #define G_FW_HELLO_CMD_STAGE(x) \
588 (((x) >> S_FW_HELLO_CMD_STAGE) & M_FW_HELLO_CMD_STAGE)
590 #define S_FW_HELLO_CMD_CLEARINIT 16
591 #define M_FW_HELLO_CMD_CLEARINIT 0x1
592 #define V_FW_HELLO_CMD_CLEARINIT(x) ((x) << S_FW_HELLO_CMD_CLEARINIT)
593 #define G_FW_HELLO_CMD_CLEARINIT(x) \
594 (((x) >> S_FW_HELLO_CMD_CLEARINIT) & M_FW_HELLO_CMD_CLEARINIT)
595 #define F_FW_HELLO_CMD_CLEARINIT V_FW_HELLO_CMD_CLEARINIT(1U)
603 struct fw_initialize_cmd {
609 enum fw_caps_config_nic {
610 FW_CAPS_CONFIG_NIC_HASHFILTER = 0x00000020,
611 FW_CAPS_CONFIG_NIC_ETHOFLD = 0x00000040,
615 FW_MEMTYPE_CF_FLASH = FW_MEMTYPE_FLASH,
618 struct fw_caps_config_cmd {
620 __be32 cfvalid_to_len16;
638 #define S_FW_CAPS_CONFIG_CMD_CFVALID 27
639 #define M_FW_CAPS_CONFIG_CMD_CFVALID 0x1
640 #define V_FW_CAPS_CONFIG_CMD_CFVALID(x) ((x) << S_FW_CAPS_CONFIG_CMD_CFVALID)
641 #define G_FW_CAPS_CONFIG_CMD_CFVALID(x) \
642 (((x) >> S_FW_CAPS_CONFIG_CMD_CFVALID) & M_FW_CAPS_CONFIG_CMD_CFVALID)
643 #define F_FW_CAPS_CONFIG_CMD_CFVALID V_FW_CAPS_CONFIG_CMD_CFVALID(1U)
645 #define S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF 24
646 #define M_FW_CAPS_CONFIG_CMD_MEMTYPE_CF 0x7
647 #define V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x) \
648 ((x) << S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF)
649 #define G_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x) \
650 (((x) >> S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF) & \
651 M_FW_CAPS_CONFIG_CMD_MEMTYPE_CF)
653 #define S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF 16
654 #define M_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF 0xff
655 #define V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x) \
656 ((x) << S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF)
657 #define G_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x) \
658 (((x) >> S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF) & \
659 M_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF)
662 * params command mnemonics
664 enum fw_params_mnem {
665 FW_PARAMS_MNEM_DEV = 1, /* device params */
666 FW_PARAMS_MNEM_PFVF = 2, /* function params */
667 FW_PARAMS_MNEM_REG = 3, /* limited register access */
668 FW_PARAMS_MNEM_DMAQ = 4, /* dma queue params */
675 #define S_FW_PARAMS_PARAM_FILTER_MODE 16
676 #define M_FW_PARAMS_PARAM_FILTER_MODE 0xffff
677 #define V_FW_PARAMS_PARAM_FILTER_MODE(x) \
678 ((x) << S_FW_PARAMS_PARAM_FILTER_MODE)
679 #define G_FW_PARAMS_PARAM_FILTER_MODE(x) \
680 (((x) >> S_FW_PARAMS_PARAM_FILTER_MODE) & \
681 M_FW_PARAMS_PARAM_FILTER_MODE)
683 #define S_FW_PARAMS_PARAM_FILTER_MASK 0
684 #define M_FW_PARAMS_PARAM_FILTER_MASK 0xffff
685 #define V_FW_PARAMS_PARAM_FILTER_MASK(x) \
686 ((x) << S_FW_PARAMS_PARAM_FILTER_MASK)
687 #define G_FW_PARAMS_PARAM_FILTER_MASK(x) \
688 (((x) >> S_FW_PARAMS_PARAM_FILTER_MASK) & \
689 M_FW_PARAMS_PARAM_FILTER_MASK)
691 enum fw_params_param_dev {
692 FW_PARAMS_PARAM_DEV_CCLK = 0x00, /* chip core clock in khz */
693 FW_PARAMS_PARAM_DEV_PORTVEC = 0x01, /* the port vector */
694 FW_PARAMS_PARAM_DEV_NTID = 0x02, /* reads the number of TIDs
695 * allocated by the device's
698 FW_PARAMS_PARAM_DEV_FWREV = 0x0B, /* fw version */
699 FW_PARAMS_PARAM_DEV_TPREV = 0x0C, /* tp version */
700 FW_PARAMS_PARAM_DEV_CF = 0x0D,
701 FW_PARAMS_PARAM_DEV_ULPTX_MEMWRITE_DSGL = 0x17,
702 FW_PARAMS_PARAM_DEV_FILTER2_WR = 0x1D,
703 FW_PARAMS_PARAM_DEV_OPAQUE_VIID_SMT_EXTN = 0x27,
704 FW_PARAMS_PARAM_DEV_HASHFILTER_WITH_OFLD = 0x28,
705 FW_PARAMS_PARAM_DEV_FILTER = 0x2E,
706 FW_PARAMS_PARAM_DEV_VI_ENABLE_INGRESS_AFTER_LINKUP = 0x32,
707 FW_PARAMS_PARAM_PFVF_RAWF_START = 0x36,
708 FW_PARAMS_PARAM_PFVF_RAWF_END = 0x37,
712 * physical and virtual function parameters
714 enum fw_params_param_pfvf {
715 FW_PARAMS_PARAM_PFVF_CLIP_START = 0x03,
716 FW_PARAMS_PARAM_PFVF_CLIP_END = 0x04,
717 FW_PARAMS_PARAM_PFVF_FILTER_START = 0x05,
718 FW_PARAMS_PARAM_PFVF_FILTER_END = 0x06,
719 FW_PARAMS_PARAM_PFVF_L2T_START = 0x13,
720 FW_PARAMS_PARAM_PFVF_L2T_END = 0x14,
721 FW_PARAMS_PARAM_PFVF_CPLFW4MSG_ENCAP = 0x31,
722 FW_PARAMS_PARAM_PFVF_PORT_CAPS32 = 0x3A,
723 FW_PARAMS_PARAM_PFVF_MAX_PKTS_PER_ETH_TX_PKTS_WR = 0x3D,
724 FW_PARAMS_PARAM_PFVF_GET_SMT_START = 0x3E,
725 FW_PARAMS_PARAM_PFVF_GET_SMT_SIZE = 0x3F,
729 * dma queue parameters
731 enum fw_params_param_dmaq {
732 FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH = 0x01,
733 FW_PARAMS_PARAM_DMAQ_CONM_CTXT = 0x20,
736 enum fw_params_param_dev_filter {
737 FW_PARAM_DEV_FILTER_VNIC_MODE = 0x00,
738 FW_PARAM_DEV_FILTER_MODE_MASK = 0x01,
741 #define S_FW_PARAMS_MNEM 24
742 #define M_FW_PARAMS_MNEM 0xff
743 #define V_FW_PARAMS_MNEM(x) ((x) << S_FW_PARAMS_MNEM)
744 #define G_FW_PARAMS_MNEM(x) \
745 (((x) >> S_FW_PARAMS_MNEM) & M_FW_PARAMS_MNEM)
747 #define S_FW_PARAMS_PARAM_X 16
748 #define M_FW_PARAMS_PARAM_X 0xff
749 #define V_FW_PARAMS_PARAM_X(x) ((x) << S_FW_PARAMS_PARAM_X)
750 #define G_FW_PARAMS_PARAM_X(x) \
751 (((x) >> S_FW_PARAMS_PARAM_X) & M_FW_PARAMS_PARAM_X)
753 #define S_FW_PARAMS_PARAM_Y 8
754 #define M_FW_PARAMS_PARAM_Y 0xff
755 #define V_FW_PARAMS_PARAM_Y(x) ((x) << S_FW_PARAMS_PARAM_Y)
756 #define G_FW_PARAMS_PARAM_Y(x) \
757 (((x) >> S_FW_PARAMS_PARAM_Y) & M_FW_PARAMS_PARAM_Y)
759 #define S_FW_PARAMS_PARAM_Z 0
760 #define M_FW_PARAMS_PARAM_Z 0xff
761 #define V_FW_PARAMS_PARAM_Z(x) ((x) << S_FW_PARAMS_PARAM_Z)
762 #define G_FW_PARAMS_PARAM_Z(x) \
763 (((x) >> S_FW_PARAMS_PARAM_Z) & M_FW_PARAMS_PARAM_Z)
765 #define S_FW_PARAMS_PARAM_YZ 0
766 #define M_FW_PARAMS_PARAM_YZ 0xffff
767 #define V_FW_PARAMS_PARAM_YZ(x) ((x) << S_FW_PARAMS_PARAM_YZ)
768 #define G_FW_PARAMS_PARAM_YZ(x) \
769 (((x) >> S_FW_PARAMS_PARAM_YZ) & M_FW_PARAMS_PARAM_YZ)
771 #define S_FW_PARAMS_PARAM_XYZ 0
772 #define M_FW_PARAMS_PARAM_XYZ 0xffffff
773 #define V_FW_PARAMS_PARAM_XYZ(x) ((x) << S_FW_PARAMS_PARAM_XYZ)
775 struct fw_params_cmd {
778 struct fw_params_param {
784 #define S_FW_PARAMS_CMD_PFN 8
785 #define M_FW_PARAMS_CMD_PFN 0x7
786 #define V_FW_PARAMS_CMD_PFN(x) ((x) << S_FW_PARAMS_CMD_PFN)
787 #define G_FW_PARAMS_CMD_PFN(x) \
788 (((x) >> S_FW_PARAMS_CMD_PFN) & M_FW_PARAMS_CMD_PFN)
790 #define S_FW_PARAMS_CMD_VFN 0
791 #define M_FW_PARAMS_CMD_VFN 0xff
792 #define V_FW_PARAMS_CMD_VFN(x) ((x) << S_FW_PARAMS_CMD_VFN)
793 #define G_FW_PARAMS_CMD_VFN(x) \
794 (((x) >> S_FW_PARAMS_CMD_VFN) & M_FW_PARAMS_CMD_VFN)
801 __be32 tc_to_nexactf;
802 __be32 r_caps_to_nethctrl;
808 #define S_FW_PFVF_CMD_PFN 8
809 #define V_FW_PFVF_CMD_PFN(x) ((x) << S_FW_PFVF_CMD_PFN)
811 #define S_FW_PFVF_CMD_VFN 0
812 #define V_FW_PFVF_CMD_VFN(x) ((x) << S_FW_PFVF_CMD_VFN)
814 #define S_FW_PFVF_CMD_NIQFLINT 20
815 #define M_FW_PFVF_CMD_NIQFLINT 0xfff
816 #define G_FW_PFVF_CMD_NIQFLINT(x) \
817 (((x) >> S_FW_PFVF_CMD_NIQFLINT) & M_FW_PFVF_CMD_NIQFLINT)
819 #define S_FW_PFVF_CMD_NIQ 0
820 #define M_FW_PFVF_CMD_NIQ 0xfffff
821 #define G_FW_PFVF_CMD_NIQ(x) \
822 (((x) >> S_FW_PFVF_CMD_NIQ) & M_FW_PFVF_CMD_NIQ)
824 #define S_FW_PFVF_CMD_PMASK 20
825 #define M_FW_PFVF_CMD_PMASK 0xf
826 #define G_FW_PFVF_CMD_PMASK(x) \
827 (((x) >> S_FW_PFVF_CMD_PMASK) & M_FW_PFVF_CMD_PMASK)
829 #define S_FW_PFVF_CMD_NEQ 0
830 #define M_FW_PFVF_CMD_NEQ 0xfffff
831 #define G_FW_PFVF_CMD_NEQ(x) \
832 (((x) >> S_FW_PFVF_CMD_NEQ) & M_FW_PFVF_CMD_NEQ)
834 #define S_FW_PFVF_CMD_TC 24
835 #define M_FW_PFVF_CMD_TC 0xff
836 #define G_FW_PFVF_CMD_TC(x) \
837 (((x) >> S_FW_PFVF_CMD_TC) & M_FW_PFVF_CMD_TC)
839 #define S_FW_PFVF_CMD_NVI 16
840 #define M_FW_PFVF_CMD_NVI 0xff
841 #define G_FW_PFVF_CMD_NVI(x) \
842 (((x) >> S_FW_PFVF_CMD_NVI) & M_FW_PFVF_CMD_NVI)
844 #define S_FW_PFVF_CMD_NEXACTF 0
845 #define M_FW_PFVF_CMD_NEXACTF 0xffff
846 #define G_FW_PFVF_CMD_NEXACTF(x) \
847 (((x) >> S_FW_PFVF_CMD_NEXACTF) & M_FW_PFVF_CMD_NEXACTF)
849 #define S_FW_PFVF_CMD_R_CAPS 24
850 #define M_FW_PFVF_CMD_R_CAPS 0xff
851 #define G_FW_PFVF_CMD_R_CAPS(x) \
852 (((x) >> S_FW_PFVF_CMD_R_CAPS) & M_FW_PFVF_CMD_R_CAPS)
854 #define S_FW_PFVF_CMD_WX_CAPS 16
855 #define M_FW_PFVF_CMD_WX_CAPS 0xff
856 #define G_FW_PFVF_CMD_WX_CAPS(x) \
857 (((x) >> S_FW_PFVF_CMD_WX_CAPS) & M_FW_PFVF_CMD_WX_CAPS)
859 #define S_FW_PFVF_CMD_NETHCTRL 0
860 #define M_FW_PFVF_CMD_NETHCTRL 0xffff
861 #define G_FW_PFVF_CMD_NETHCTRL(x) \
862 (((x) >> S_FW_PFVF_CMD_NETHCTRL) & M_FW_PFVF_CMD_NETHCTRL)
865 * ingress queue type; the first 1K ingress queues can have associated 0,
866 * 1 or 2 free lists and an interrupt, all other ingress queues lack these
870 FW_IQ_TYPE_FL_INT_CAP,
874 FW_IQ_IQTYPE_NIC = 1,
880 __be32 alloc_to_len16;
885 __be32 type_to_iqandstindex;
886 __be16 iqdroprss_to_iqesize;
889 __be32 iqns_to_fl0congen;
890 __be16 fl0dcaen_to_fl0cidxfthresh;
893 __be32 fl1cngchmap_to_fl1congen;
894 __be16 fl1dcaen_to_fl1cidxfthresh;
899 #define S_FW_IQ_CMD_PFN 8
900 #define M_FW_IQ_CMD_PFN 0x7
901 #define V_FW_IQ_CMD_PFN(x) ((x) << S_FW_IQ_CMD_PFN)
902 #define G_FW_IQ_CMD_PFN(x) (((x) >> S_FW_IQ_CMD_PFN) & M_FW_IQ_CMD_PFN)
904 #define S_FW_IQ_CMD_VFN 0
905 #define M_FW_IQ_CMD_VFN 0xff
906 #define V_FW_IQ_CMD_VFN(x) ((x) << S_FW_IQ_CMD_VFN)
907 #define G_FW_IQ_CMD_VFN(x) (((x) >> S_FW_IQ_CMD_VFN) & M_FW_IQ_CMD_VFN)
909 #define S_FW_IQ_CMD_ALLOC 31
910 #define M_FW_IQ_CMD_ALLOC 0x1
911 #define V_FW_IQ_CMD_ALLOC(x) ((x) << S_FW_IQ_CMD_ALLOC)
912 #define G_FW_IQ_CMD_ALLOC(x) \
913 (((x) >> S_FW_IQ_CMD_ALLOC) & M_FW_IQ_CMD_ALLOC)
914 #define F_FW_IQ_CMD_ALLOC V_FW_IQ_CMD_ALLOC(1U)
916 #define S_FW_IQ_CMD_FREE 30
917 #define M_FW_IQ_CMD_FREE 0x1
918 #define V_FW_IQ_CMD_FREE(x) ((x) << S_FW_IQ_CMD_FREE)
919 #define G_FW_IQ_CMD_FREE(x) (((x) >> S_FW_IQ_CMD_FREE) & M_FW_IQ_CMD_FREE)
920 #define F_FW_IQ_CMD_FREE V_FW_IQ_CMD_FREE(1U)
922 #define S_FW_IQ_CMD_IQSTART 28
923 #define M_FW_IQ_CMD_IQSTART 0x1
924 #define V_FW_IQ_CMD_IQSTART(x) ((x) << S_FW_IQ_CMD_IQSTART)
925 #define G_FW_IQ_CMD_IQSTART(x) \
926 (((x) >> S_FW_IQ_CMD_IQSTART) & M_FW_IQ_CMD_IQSTART)
927 #define F_FW_IQ_CMD_IQSTART V_FW_IQ_CMD_IQSTART(1U)
929 #define S_FW_IQ_CMD_IQSTOP 27
930 #define M_FW_IQ_CMD_IQSTOP 0x1
931 #define V_FW_IQ_CMD_IQSTOP(x) ((x) << S_FW_IQ_CMD_IQSTOP)
932 #define G_FW_IQ_CMD_IQSTOP(x) \
933 (((x) >> S_FW_IQ_CMD_IQSTOP) & M_FW_IQ_CMD_IQSTOP)
934 #define F_FW_IQ_CMD_IQSTOP V_FW_IQ_CMD_IQSTOP(1U)
936 #define S_FW_IQ_CMD_TYPE 29
937 #define M_FW_IQ_CMD_TYPE 0x7
938 #define V_FW_IQ_CMD_TYPE(x) ((x) << S_FW_IQ_CMD_TYPE)
939 #define G_FW_IQ_CMD_TYPE(x) (((x) >> S_FW_IQ_CMD_TYPE) & M_FW_IQ_CMD_TYPE)
941 #define S_FW_IQ_CMD_IQASYNCH 28
942 #define M_FW_IQ_CMD_IQASYNCH 0x1
943 #define V_FW_IQ_CMD_IQASYNCH(x) ((x) << S_FW_IQ_CMD_IQASYNCH)
944 #define G_FW_IQ_CMD_IQASYNCH(x) \
945 (((x) >> S_FW_IQ_CMD_IQASYNCH) & M_FW_IQ_CMD_IQASYNCH)
946 #define F_FW_IQ_CMD_IQASYNCH V_FW_IQ_CMD_IQASYNCH(1U)
948 #define S_FW_IQ_CMD_VIID 16
949 #define M_FW_IQ_CMD_VIID 0xfff
950 #define V_FW_IQ_CMD_VIID(x) ((x) << S_FW_IQ_CMD_VIID)
951 #define G_FW_IQ_CMD_VIID(x) (((x) >> S_FW_IQ_CMD_VIID) & M_FW_IQ_CMD_VIID)
953 #define S_FW_IQ_CMD_IQANDST 15
954 #define M_FW_IQ_CMD_IQANDST 0x1
955 #define V_FW_IQ_CMD_IQANDST(x) ((x) << S_FW_IQ_CMD_IQANDST)
956 #define G_FW_IQ_CMD_IQANDST(x) \
957 (((x) >> S_FW_IQ_CMD_IQANDST) & M_FW_IQ_CMD_IQANDST)
958 #define F_FW_IQ_CMD_IQANDST V_FW_IQ_CMD_IQANDST(1U)
960 #define S_FW_IQ_CMD_IQANUD 12
961 #define M_FW_IQ_CMD_IQANUD 0x3
962 #define V_FW_IQ_CMD_IQANUD(x) ((x) << S_FW_IQ_CMD_IQANUD)
963 #define G_FW_IQ_CMD_IQANUD(x) \
964 (((x) >> S_FW_IQ_CMD_IQANUD) & M_FW_IQ_CMD_IQANUD)
966 #define S_FW_IQ_CMD_IQANDSTINDEX 0
967 #define M_FW_IQ_CMD_IQANDSTINDEX 0xfff
968 #define V_FW_IQ_CMD_IQANDSTINDEX(x) ((x) << S_FW_IQ_CMD_IQANDSTINDEX)
969 #define G_FW_IQ_CMD_IQANDSTINDEX(x) \
970 (((x) >> S_FW_IQ_CMD_IQANDSTINDEX) & M_FW_IQ_CMD_IQANDSTINDEX)
972 #define S_FW_IQ_CMD_IQGTSMODE 14
973 #define M_FW_IQ_CMD_IQGTSMODE 0x1
974 #define V_FW_IQ_CMD_IQGTSMODE(x) ((x) << S_FW_IQ_CMD_IQGTSMODE)
975 #define G_FW_IQ_CMD_IQGTSMODE(x) \
976 (((x) >> S_FW_IQ_CMD_IQGTSMODE) & M_FW_IQ_CMD_IQGTSMODE)
977 #define F_FW_IQ_CMD_IQGTSMODE V_FW_IQ_CMD_IQGTSMODE(1U)
979 #define S_FW_IQ_CMD_IQPCIECH 12
980 #define M_FW_IQ_CMD_IQPCIECH 0x3
981 #define V_FW_IQ_CMD_IQPCIECH(x) ((x) << S_FW_IQ_CMD_IQPCIECH)
982 #define G_FW_IQ_CMD_IQPCIECH(x) \
983 (((x) >> S_FW_IQ_CMD_IQPCIECH) & M_FW_IQ_CMD_IQPCIECH)
985 #define S_FW_IQ_CMD_IQINTCNTTHRESH 4
986 #define M_FW_IQ_CMD_IQINTCNTTHRESH 0x3
987 #define V_FW_IQ_CMD_IQINTCNTTHRESH(x) ((x) << S_FW_IQ_CMD_IQINTCNTTHRESH)
988 #define G_FW_IQ_CMD_IQINTCNTTHRESH(x) \
989 (((x) >> S_FW_IQ_CMD_IQINTCNTTHRESH) & M_FW_IQ_CMD_IQINTCNTTHRESH)
991 #define S_FW_IQ_CMD_IQESIZE 0
992 #define M_FW_IQ_CMD_IQESIZE 0x3
993 #define V_FW_IQ_CMD_IQESIZE(x) ((x) << S_FW_IQ_CMD_IQESIZE)
994 #define G_FW_IQ_CMD_IQESIZE(x) \
995 (((x) >> S_FW_IQ_CMD_IQESIZE) & M_FW_IQ_CMD_IQESIZE)
997 #define S_FW_IQ_CMD_IQRO 30
998 #define M_FW_IQ_CMD_IQRO 0x1
999 #define V_FW_IQ_CMD_IQRO(x) ((x) << S_FW_IQ_CMD_IQRO)
1000 #define G_FW_IQ_CMD_IQRO(x) \
1001 (((x) >> S_FW_IQ_CMD_IQRO) & M_FW_IQ_CMD_IQRO)
1002 #define F_FW_IQ_CMD_IQRO V_FW_IQ_CMD_IQRO(1U)
1004 #define S_FW_IQ_CMD_IQFLINTCONGEN 27
1005 #define M_FW_IQ_CMD_IQFLINTCONGEN 0x1
1006 #define V_FW_IQ_CMD_IQFLINTCONGEN(x) ((x) << S_FW_IQ_CMD_IQFLINTCONGEN)
1007 #define G_FW_IQ_CMD_IQFLINTCONGEN(x) \
1008 (((x) >> S_FW_IQ_CMD_IQFLINTCONGEN) & M_FW_IQ_CMD_IQFLINTCONGEN)
1009 #define F_FW_IQ_CMD_IQFLINTCONGEN V_FW_IQ_CMD_IQFLINTCONGEN(1U)
1011 #define S_FW_IQ_CMD_IQTYPE 24
1012 #define V_FW_IQ_CMD_IQTYPE(x) ((x) << S_FW_IQ_CMD_IQTYPE)
1014 #define S_FW_IQ_CMD_FL0CNGCHMAP 20
1015 #define M_FW_IQ_CMD_FL0CNGCHMAP 0xf
1016 #define V_FW_IQ_CMD_FL0CNGCHMAP(x) ((x) << S_FW_IQ_CMD_FL0CNGCHMAP)
1017 #define G_FW_IQ_CMD_FL0CNGCHMAP(x) \
1018 (((x) >> S_FW_IQ_CMD_FL0CNGCHMAP) & M_FW_IQ_CMD_FL0CNGCHMAP)
1020 #define S_FW_IQ_CMD_FL0DATARO 12
1021 #define M_FW_IQ_CMD_FL0DATARO 0x1
1022 #define V_FW_IQ_CMD_FL0DATARO(x) ((x) << S_FW_IQ_CMD_FL0DATARO)
1023 #define G_FW_IQ_CMD_FL0DATARO(x) \
1024 (((x) >> S_FW_IQ_CMD_FL0DATARO) & M_FW_IQ_CMD_FL0DATARO)
1025 #define F_FW_IQ_CMD_FL0DATARO V_FW_IQ_CMD_FL0DATARO(1U)
1027 #define S_FW_IQ_CMD_FL0CONGCIF 11
1028 #define M_FW_IQ_CMD_FL0CONGCIF 0x1
1029 #define V_FW_IQ_CMD_FL0CONGCIF(x) ((x) << S_FW_IQ_CMD_FL0CONGCIF)
1030 #define G_FW_IQ_CMD_FL0CONGCIF(x) \
1031 (((x) >> S_FW_IQ_CMD_FL0CONGCIF) & M_FW_IQ_CMD_FL0CONGCIF)
1032 #define F_FW_IQ_CMD_FL0CONGCIF V_FW_IQ_CMD_FL0CONGCIF(1U)
1034 #define S_FW_IQ_CMD_FL0FETCHRO 6
1035 #define M_FW_IQ_CMD_FL0FETCHRO 0x1
1036 #define V_FW_IQ_CMD_FL0FETCHRO(x) ((x) << S_FW_IQ_CMD_FL0FETCHRO)
1037 #define G_FW_IQ_CMD_FL0FETCHRO(x) \
1038 (((x) >> S_FW_IQ_CMD_FL0FETCHRO) & M_FW_IQ_CMD_FL0FETCHRO)
1039 #define F_FW_IQ_CMD_FL0FETCHRO V_FW_IQ_CMD_FL0FETCHRO(1U)
1041 #define S_FW_IQ_CMD_FL0HOSTFCMODE 4
1042 #define M_FW_IQ_CMD_FL0HOSTFCMODE 0x3
1043 #define V_FW_IQ_CMD_FL0HOSTFCMODE(x) ((x) << S_FW_IQ_CMD_FL0HOSTFCMODE)
1044 #define G_FW_IQ_CMD_FL0HOSTFCMODE(x) \
1045 (((x) >> S_FW_IQ_CMD_FL0HOSTFCMODE) & M_FW_IQ_CMD_FL0HOSTFCMODE)
1047 #define S_FW_IQ_CMD_FL0PADEN 2
1048 #define M_FW_IQ_CMD_FL0PADEN 0x1
1049 #define V_FW_IQ_CMD_FL0PADEN(x) ((x) << S_FW_IQ_CMD_FL0PADEN)
1050 #define G_FW_IQ_CMD_FL0PADEN(x) \
1051 (((x) >> S_FW_IQ_CMD_FL0PADEN) & M_FW_IQ_CMD_FL0PADEN)
1052 #define F_FW_IQ_CMD_FL0PADEN V_FW_IQ_CMD_FL0PADEN(1U)
1054 #define S_FW_IQ_CMD_FL0PACKEN 1
1055 #define M_FW_IQ_CMD_FL0PACKEN 0x1
1056 #define V_FW_IQ_CMD_FL0PACKEN(x) ((x) << S_FW_IQ_CMD_FL0PACKEN)
1057 #define G_FW_IQ_CMD_FL0PACKEN(x) \
1058 (((x) >> S_FW_IQ_CMD_FL0PACKEN) & M_FW_IQ_CMD_FL0PACKEN)
1059 #define F_FW_IQ_CMD_FL0PACKEN V_FW_IQ_CMD_FL0PACKEN(1U)
1061 #define S_FW_IQ_CMD_FL0CONGEN 0
1062 #define M_FW_IQ_CMD_FL0CONGEN 0x1
1063 #define V_FW_IQ_CMD_FL0CONGEN(x) ((x) << S_FW_IQ_CMD_FL0CONGEN)
1064 #define G_FW_IQ_CMD_FL0CONGEN(x) \
1065 (((x) >> S_FW_IQ_CMD_FL0CONGEN) & M_FW_IQ_CMD_FL0CONGEN)
1066 #define F_FW_IQ_CMD_FL0CONGEN V_FW_IQ_CMD_FL0CONGEN(1U)
1068 #define S_FW_IQ_CMD_FL0FBMIN 7
1069 #define M_FW_IQ_CMD_FL0FBMIN 0x7
1070 #define V_FW_IQ_CMD_FL0FBMIN(x) ((x) << S_FW_IQ_CMD_FL0FBMIN)
1071 #define G_FW_IQ_CMD_FL0FBMIN(x) \
1072 (((x) >> S_FW_IQ_CMD_FL0FBMIN) & M_FW_IQ_CMD_FL0FBMIN)
1074 #define S_FW_IQ_CMD_FL0FBMAX 4
1075 #define M_FW_IQ_CMD_FL0FBMAX 0x7
1076 #define V_FW_IQ_CMD_FL0FBMAX(x) ((x) << S_FW_IQ_CMD_FL0FBMAX)
1077 #define G_FW_IQ_CMD_FL0FBMAX(x) \
1078 (((x) >> S_FW_IQ_CMD_FL0FBMAX) & M_FW_IQ_CMD_FL0FBMAX)
1080 struct fw_eq_eth_cmd {
1082 __be32 alloc_to_len16;
1084 __be32 physeqid_pkd;
1085 __be32 fetchszm_to_iqid;
1086 __be32 dcaen_to_eqsize;
1088 __be32 autoequiqe_to_viid;
1093 #define S_FW_EQ_ETH_CMD_PFN 8
1094 #define M_FW_EQ_ETH_CMD_PFN 0x7
1095 #define V_FW_EQ_ETH_CMD_PFN(x) ((x) << S_FW_EQ_ETH_CMD_PFN)
1096 #define G_FW_EQ_ETH_CMD_PFN(x) \
1097 (((x) >> S_FW_EQ_ETH_CMD_PFN) & M_FW_EQ_ETH_CMD_PFN)
1099 #define S_FW_EQ_ETH_CMD_VFN 0
1100 #define M_FW_EQ_ETH_CMD_VFN 0xff
1101 #define V_FW_EQ_ETH_CMD_VFN(x) ((x) << S_FW_EQ_ETH_CMD_VFN)
1102 #define G_FW_EQ_ETH_CMD_VFN(x) \
1103 (((x) >> S_FW_EQ_ETH_CMD_VFN) & M_FW_EQ_ETH_CMD_VFN)
1105 #define S_FW_EQ_ETH_CMD_ALLOC 31
1106 #define M_FW_EQ_ETH_CMD_ALLOC 0x1
1107 #define V_FW_EQ_ETH_CMD_ALLOC(x) ((x) << S_FW_EQ_ETH_CMD_ALLOC)
1108 #define G_FW_EQ_ETH_CMD_ALLOC(x) \
1109 (((x) >> S_FW_EQ_ETH_CMD_ALLOC) & M_FW_EQ_ETH_CMD_ALLOC)
1110 #define F_FW_EQ_ETH_CMD_ALLOC V_FW_EQ_ETH_CMD_ALLOC(1U)
1112 #define S_FW_EQ_ETH_CMD_FREE 30
1113 #define M_FW_EQ_ETH_CMD_FREE 0x1
1114 #define V_FW_EQ_ETH_CMD_FREE(x) ((x) << S_FW_EQ_ETH_CMD_FREE)
1115 #define G_FW_EQ_ETH_CMD_FREE(x) \
1116 (((x) >> S_FW_EQ_ETH_CMD_FREE) & M_FW_EQ_ETH_CMD_FREE)
1117 #define F_FW_EQ_ETH_CMD_FREE V_FW_EQ_ETH_CMD_FREE(1U)
1119 #define S_FW_EQ_ETH_CMD_EQSTART 28
1120 #define M_FW_EQ_ETH_CMD_EQSTART 0x1
1121 #define V_FW_EQ_ETH_CMD_EQSTART(x) ((x) << S_FW_EQ_ETH_CMD_EQSTART)
1122 #define G_FW_EQ_ETH_CMD_EQSTART(x) \
1123 (((x) >> S_FW_EQ_ETH_CMD_EQSTART) & M_FW_EQ_ETH_CMD_EQSTART)
1124 #define F_FW_EQ_ETH_CMD_EQSTART V_FW_EQ_ETH_CMD_EQSTART(1U)
1126 #define S_FW_EQ_ETH_CMD_EQID 0
1127 #define M_FW_EQ_ETH_CMD_EQID 0xfffff
1128 #define V_FW_EQ_ETH_CMD_EQID(x) ((x) << S_FW_EQ_ETH_CMD_EQID)
1129 #define G_FW_EQ_ETH_CMD_EQID(x) \
1130 (((x) >> S_FW_EQ_ETH_CMD_EQID) & M_FW_EQ_ETH_CMD_EQID)
1132 #define S_FW_EQ_ETH_CMD_PHYSEQID 0
1133 #define M_FW_EQ_ETH_CMD_PHYSEQID 0xfffff
1134 #define G_FW_EQ_ETH_CMD_PHYSEQID(x) \
1135 (((x) >> S_FW_EQ_ETH_CMD_PHYSEQID) & M_FW_EQ_ETH_CMD_PHYSEQID)
1137 #define S_FW_EQ_ETH_CMD_FETCHRO 22
1138 #define M_FW_EQ_ETH_CMD_FETCHRO 0x1
1139 #define V_FW_EQ_ETH_CMD_FETCHRO(x) ((x) << S_FW_EQ_ETH_CMD_FETCHRO)
1140 #define G_FW_EQ_ETH_CMD_FETCHRO(x) \
1141 (((x) >> S_FW_EQ_ETH_CMD_FETCHRO) & M_FW_EQ_ETH_CMD_FETCHRO)
1142 #define F_FW_EQ_ETH_CMD_FETCHRO V_FW_EQ_ETH_CMD_FETCHRO(1U)
1144 #define S_FW_EQ_ETH_CMD_HOSTFCMODE 20
1145 #define M_FW_EQ_ETH_CMD_HOSTFCMODE 0x3
1146 #define V_FW_EQ_ETH_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_ETH_CMD_HOSTFCMODE)
1147 #define G_FW_EQ_ETH_CMD_HOSTFCMODE(x) \
1148 (((x) >> S_FW_EQ_ETH_CMD_HOSTFCMODE) & M_FW_EQ_ETH_CMD_HOSTFCMODE)
1150 #define S_FW_EQ_ETH_CMD_PCIECHN 16
1151 #define M_FW_EQ_ETH_CMD_PCIECHN 0x3
1152 #define V_FW_EQ_ETH_CMD_PCIECHN(x) ((x) << S_FW_EQ_ETH_CMD_PCIECHN)
1153 #define G_FW_EQ_ETH_CMD_PCIECHN(x) \
1154 (((x) >> S_FW_EQ_ETH_CMD_PCIECHN) & M_FW_EQ_ETH_CMD_PCIECHN)
1156 #define S_FW_EQ_ETH_CMD_IQID 0
1157 #define M_FW_EQ_ETH_CMD_IQID 0xffff
1158 #define V_FW_EQ_ETH_CMD_IQID(x) ((x) << S_FW_EQ_ETH_CMD_IQID)
1159 #define G_FW_EQ_ETH_CMD_IQID(x) \
1160 (((x) >> S_FW_EQ_ETH_CMD_IQID) & M_FW_EQ_ETH_CMD_IQID)
1162 #define S_FW_EQ_ETH_CMD_FBMIN 23
1163 #define M_FW_EQ_ETH_CMD_FBMIN 0x7
1164 #define V_FW_EQ_ETH_CMD_FBMIN(x) ((x) << S_FW_EQ_ETH_CMD_FBMIN)
1165 #define G_FW_EQ_ETH_CMD_FBMIN(x) \
1166 (((x) >> S_FW_EQ_ETH_CMD_FBMIN) & M_FW_EQ_ETH_CMD_FBMIN)
1168 #define S_FW_EQ_ETH_CMD_FBMAX 20
1169 #define M_FW_EQ_ETH_CMD_FBMAX 0x7
1170 #define V_FW_EQ_ETH_CMD_FBMAX(x) ((x) << S_FW_EQ_ETH_CMD_FBMAX)
1171 #define G_FW_EQ_ETH_CMD_FBMAX(x) \
1172 (((x) >> S_FW_EQ_ETH_CMD_FBMAX) & M_FW_EQ_ETH_CMD_FBMAX)
1174 #define S_FW_EQ_ETH_CMD_CIDXFTHRESH 16
1175 #define M_FW_EQ_ETH_CMD_CIDXFTHRESH 0x7
1176 #define V_FW_EQ_ETH_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_ETH_CMD_CIDXFTHRESH)
1177 #define G_FW_EQ_ETH_CMD_CIDXFTHRESH(x) \
1178 (((x) >> S_FW_EQ_ETH_CMD_CIDXFTHRESH) & M_FW_EQ_ETH_CMD_CIDXFTHRESH)
1180 #define S_FW_EQ_ETH_CMD_EQSIZE 0
1181 #define M_FW_EQ_ETH_CMD_EQSIZE 0xffff
1182 #define V_FW_EQ_ETH_CMD_EQSIZE(x) ((x) << S_FW_EQ_ETH_CMD_EQSIZE)
1183 #define G_FW_EQ_ETH_CMD_EQSIZE(x) \
1184 (((x) >> S_FW_EQ_ETH_CMD_EQSIZE) & M_FW_EQ_ETH_CMD_EQSIZE)
1186 #define S_FW_EQ_ETH_CMD_AUTOEQUEQE 30
1187 #define M_FW_EQ_ETH_CMD_AUTOEQUEQE 0x1
1188 #define V_FW_EQ_ETH_CMD_AUTOEQUEQE(x) ((x) << S_FW_EQ_ETH_CMD_AUTOEQUEQE)
1189 #define G_FW_EQ_ETH_CMD_AUTOEQUEQE(x) \
1190 (((x) >> S_FW_EQ_ETH_CMD_AUTOEQUEQE) & M_FW_EQ_ETH_CMD_AUTOEQUEQE)
1191 #define F_FW_EQ_ETH_CMD_AUTOEQUEQE V_FW_EQ_ETH_CMD_AUTOEQUEQE(1U)
1193 #define S_FW_EQ_ETH_CMD_VIID 16
1194 #define M_FW_EQ_ETH_CMD_VIID 0xfff
1195 #define V_FW_EQ_ETH_CMD_VIID(x) ((x) << S_FW_EQ_ETH_CMD_VIID)
1196 #define G_FW_EQ_ETH_CMD_VIID(x) \
1197 (((x) >> S_FW_EQ_ETH_CMD_VIID) & M_FW_EQ_ETH_CMD_VIID)
1199 struct fw_eq_ctrl_cmd {
1201 __be32 alloc_to_len16;
1202 __be32 cmpliqid_eqid;
1203 __be32 physeqid_pkd;
1204 __be32 fetchszm_to_iqid;
1205 __be32 dcaen_to_eqsize;
1209 #define S_FW_EQ_CTRL_CMD_PFN 8
1210 #define V_FW_EQ_CTRL_CMD_PFN(x) ((x) << S_FW_EQ_CTRL_CMD_PFN)
1212 #define S_FW_EQ_CTRL_CMD_VFN 0
1213 #define V_FW_EQ_CTRL_CMD_VFN(x) ((x) << S_FW_EQ_CTRL_CMD_VFN)
1215 #define S_FW_EQ_CTRL_CMD_ALLOC 31
1216 #define V_FW_EQ_CTRL_CMD_ALLOC(x) ((x) << S_FW_EQ_CTRL_CMD_ALLOC)
1217 #define F_FW_EQ_CTRL_CMD_ALLOC V_FW_EQ_CTRL_CMD_ALLOC(1U)
1219 #define S_FW_EQ_CTRL_CMD_FREE 30
1220 #define V_FW_EQ_CTRL_CMD_FREE(x) ((x) << S_FW_EQ_CTRL_CMD_FREE)
1221 #define F_FW_EQ_CTRL_CMD_FREE V_FW_EQ_CTRL_CMD_FREE(1U)
1223 #define S_FW_EQ_CTRL_CMD_EQSTART 28
1224 #define V_FW_EQ_CTRL_CMD_EQSTART(x) ((x) << S_FW_EQ_CTRL_CMD_EQSTART)
1225 #define F_FW_EQ_CTRL_CMD_EQSTART V_FW_EQ_CTRL_CMD_EQSTART(1U)
1227 #define S_FW_EQ_CTRL_CMD_CMPLIQID 20
1228 #define V_FW_EQ_CTRL_CMD_CMPLIQID(x) ((x) << S_FW_EQ_CTRL_CMD_CMPLIQID)
1230 #define S_FW_EQ_CTRL_CMD_EQID 0
1231 #define M_FW_EQ_CTRL_CMD_EQID 0xfffff
1232 #define V_FW_EQ_CTRL_CMD_EQID(x) ((x) << S_FW_EQ_CTRL_CMD_EQID)
1233 #define G_FW_EQ_CTRL_CMD_EQID(x) \
1234 (((x) >> S_FW_EQ_CTRL_CMD_EQID) & M_FW_EQ_CTRL_CMD_EQID)
1236 #define S_FW_EQ_CTRL_CMD_PHYSEQID 0
1237 #define M_FW_EQ_CTRL_CMD_PHYSEQID 0xfffff
1238 #define V_FW_EQ_CTRL_CMD_PHYSEQID(x) ((x) << S_FW_EQ_CTRL_CMD_PHYSEQID)
1239 #define G_FW_EQ_CTRL_CMD_PHYSEQID(x) \
1240 (((x) >> S_FW_EQ_CTRL_CMD_PHYSEQID) & M_FW_EQ_CTRL_CMD_PHYSEQID)
1242 #define S_FW_EQ_CTRL_CMD_FETCHRO 22
1243 #define V_FW_EQ_CTRL_CMD_FETCHRO(x) ((x) << S_FW_EQ_CTRL_CMD_FETCHRO)
1244 #define F_FW_EQ_CTRL_CMD_FETCHRO V_FW_EQ_CTRL_CMD_FETCHRO(1U)
1246 #define S_FW_EQ_CTRL_CMD_HOSTFCMODE 20
1247 #define M_FW_EQ_CTRL_CMD_HOSTFCMODE 0x3
1248 #define V_FW_EQ_CTRL_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_CTRL_CMD_HOSTFCMODE)
1250 #define S_FW_EQ_CTRL_CMD_PCIECHN 16
1251 #define V_FW_EQ_CTRL_CMD_PCIECHN(x) ((x) << S_FW_EQ_CTRL_CMD_PCIECHN)
1253 #define S_FW_EQ_CTRL_CMD_IQID 0
1254 #define V_FW_EQ_CTRL_CMD_IQID(x) ((x) << S_FW_EQ_CTRL_CMD_IQID)
1256 #define S_FW_EQ_CTRL_CMD_FBMIN 23
1257 #define V_FW_EQ_CTRL_CMD_FBMIN(x) ((x) << S_FW_EQ_CTRL_CMD_FBMIN)
1259 #define S_FW_EQ_CTRL_CMD_FBMAX 20
1260 #define V_FW_EQ_CTRL_CMD_FBMAX(x) ((x) << S_FW_EQ_CTRL_CMD_FBMAX)
1262 #define S_FW_EQ_CTRL_CMD_CIDXFTHRESH 16
1263 #define V_FW_EQ_CTRL_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_CTRL_CMD_CIDXFTHRESH)
1265 #define S_FW_EQ_CTRL_CMD_EQSIZE 0
1266 #define V_FW_EQ_CTRL_CMD_EQSIZE(x) ((x) << S_FW_EQ_CTRL_CMD_EQSIZE)
1272 /* Macros for VIID parsing:
1273 * VIID - [10:8] PFN, [7] VI Valid, [6:0] VI number
1276 #define S_FW_VIID_VIVLD 7
1277 #define M_FW_VIID_VIVLD 0x1
1278 #define G_FW_VIID_VIVLD(x) (((x) >> S_FW_VIID_VIVLD) & M_FW_VIID_VIVLD)
1280 #define S_FW_VIID_VIN 0
1281 #define M_FW_VIID_VIN 0x7F
1282 #define G_FW_VIID_VIN(x) (((x) >> S_FW_VIID_VIN) & M_FW_VIID_VIN)
1286 __be32 alloc_to_len16;
1287 __be16 type_to_viid;
1292 __be16 norss_rsssize;
1302 #define S_FW_VI_CMD_PFN 8
1303 #define M_FW_VI_CMD_PFN 0x7
1304 #define V_FW_VI_CMD_PFN(x) ((x) << S_FW_VI_CMD_PFN)
1305 #define G_FW_VI_CMD_PFN(x) (((x) >> S_FW_VI_CMD_PFN) & M_FW_VI_CMD_PFN)
1307 #define S_FW_VI_CMD_VFN 0
1308 #define M_FW_VI_CMD_VFN 0xff
1309 #define V_FW_VI_CMD_VFN(x) ((x) << S_FW_VI_CMD_VFN)
1310 #define G_FW_VI_CMD_VFN(x) (((x) >> S_FW_VI_CMD_VFN) & M_FW_VI_CMD_VFN)
1312 #define S_FW_VI_CMD_ALLOC 31
1313 #define M_FW_VI_CMD_ALLOC 0x1
1314 #define V_FW_VI_CMD_ALLOC(x) ((x) << S_FW_VI_CMD_ALLOC)
1315 #define G_FW_VI_CMD_ALLOC(x) \
1316 (((x) >> S_FW_VI_CMD_ALLOC) & M_FW_VI_CMD_ALLOC)
1317 #define F_FW_VI_CMD_ALLOC V_FW_VI_CMD_ALLOC(1U)
1319 #define S_FW_VI_CMD_FREE 30
1320 #define M_FW_VI_CMD_FREE 0x1
1321 #define V_FW_VI_CMD_FREE(x) ((x) << S_FW_VI_CMD_FREE)
1322 #define G_FW_VI_CMD_FREE(x) (((x) >> S_FW_VI_CMD_FREE) & M_FW_VI_CMD_FREE)
1323 #define F_FW_VI_CMD_FREE V_FW_VI_CMD_FREE(1U)
1325 #define S_FW_VI_CMD_VFVLD 24
1326 #define M_FW_VI_CMD_VFVLD 0x1
1327 #define G_FW_VI_CMD_VFVLD(x) \
1328 (((x) >> S_FW_VI_CMD_VFVLD) & M_FW_VI_CMD_VFVLD)
1330 #define S_FW_VI_CMD_VIN 16
1331 #define M_FW_VI_CMD_VIN 0xff
1332 #define G_FW_VI_CMD_VIN(x) \
1333 (((x) >> S_FW_VI_CMD_VIN) & M_FW_VI_CMD_VIN)
1335 #define S_FW_VI_CMD_TYPE 15
1336 #define M_FW_VI_CMD_TYPE 0x1
1337 #define V_FW_VI_CMD_TYPE(x) ((x) << S_FW_VI_CMD_TYPE)
1338 #define G_FW_VI_CMD_TYPE(x) (((x) >> S_FW_VI_CMD_TYPE) & M_FW_VI_CMD_TYPE)
1339 #define F_FW_VI_CMD_TYPE V_FW_VI_CMD_TYPE(1U)
1341 #define S_FW_VI_CMD_FUNC 12
1342 #define M_FW_VI_CMD_FUNC 0x7
1343 #define V_FW_VI_CMD_FUNC(x) ((x) << S_FW_VI_CMD_FUNC)
1344 #define G_FW_VI_CMD_FUNC(x) (((x) >> S_FW_VI_CMD_FUNC) & M_FW_VI_CMD_FUNC)
1346 #define S_FW_VI_CMD_VIID 0
1347 #define M_FW_VI_CMD_VIID 0xfff
1348 #define V_FW_VI_CMD_VIID(x) ((x) << S_FW_VI_CMD_VIID)
1349 #define G_FW_VI_CMD_VIID(x) (((x) >> S_FW_VI_CMD_VIID) & M_FW_VI_CMD_VIID)
1351 #define S_FW_VI_CMD_PORTID 4
1352 #define M_FW_VI_CMD_PORTID 0xf
1353 #define V_FW_VI_CMD_PORTID(x) ((x) << S_FW_VI_CMD_PORTID)
1354 #define G_FW_VI_CMD_PORTID(x) \
1355 (((x) >> S_FW_VI_CMD_PORTID) & M_FW_VI_CMD_PORTID)
1357 #define S_FW_VI_CMD_RSSSIZE 0
1358 #define M_FW_VI_CMD_RSSSIZE 0x7ff
1359 #define V_FW_VI_CMD_RSSSIZE(x) ((x) << S_FW_VI_CMD_RSSSIZE)
1360 #define G_FW_VI_CMD_RSSSIZE(x) \
1361 (((x) >> S_FW_VI_CMD_RSSSIZE) & M_FW_VI_CMD_RSSSIZE)
1363 /* Special VI_MAC command index ids */
1364 #define FW_VI_MAC_ADD_MAC 0x3FF
1365 #define FW_VI_MAC_ADD_PERSIST_MAC 0x3FE
1366 #define FW_VI_MAC_ID_BASED_FREE 0x3FC
1368 enum fw_vi_mac_smac {
1369 FW_VI_MAC_MPS_TCAM_ENTRY = 0x0,
1370 FW_VI_MAC_SMT_AND_MPSTCAM = 0x3
1373 enum fw_vi_mac_entry_types {
1374 FW_VI_MAC_TYPE_RAW = 0x2,
1377 struct fw_vi_mac_cmd {
1379 __be32 freemacs_to_len16;
1381 struct fw_vi_mac_exact {
1382 __be16 valid_to_idx;
1385 struct fw_vi_mac_hash {
1388 struct fw_vi_mac_raw {
1398 #define S_FW_VI_MAC_CMD_VIID 0
1399 #define M_FW_VI_MAC_CMD_VIID 0xfff
1400 #define V_FW_VI_MAC_CMD_VIID(x) ((x) << S_FW_VI_MAC_CMD_VIID)
1401 #define G_FW_VI_MAC_CMD_VIID(x) \
1402 (((x) >> S_FW_VI_MAC_CMD_VIID) & M_FW_VI_MAC_CMD_VIID)
1404 #define S_FW_VI_MAC_CMD_FREEMACS 31
1405 #define V_FW_VI_MAC_CMD_FREEMACS(x) ((x) << S_FW_VI_MAC_CMD_FREEMACS)
1407 #define S_FW_VI_MAC_CMD_ENTRY_TYPE 23
1408 #define V_FW_VI_MAC_CMD_ENTRY_TYPE(x) ((x) << S_FW_VI_MAC_CMD_ENTRY_TYPE)
1410 #define S_FW_VI_MAC_CMD_VALID 15
1411 #define M_FW_VI_MAC_CMD_VALID 0x1
1412 #define V_FW_VI_MAC_CMD_VALID(x) ((x) << S_FW_VI_MAC_CMD_VALID)
1413 #define G_FW_VI_MAC_CMD_VALID(x) \
1414 (((x) >> S_FW_VI_MAC_CMD_VALID) & M_FW_VI_MAC_CMD_VALID)
1415 #define F_FW_VI_MAC_CMD_VALID V_FW_VI_MAC_CMD_VALID(1U)
1417 #define S_FW_VI_MAC_CMD_SMAC_RESULT 10
1418 #define M_FW_VI_MAC_CMD_SMAC_RESULT 0x3
1419 #define V_FW_VI_MAC_CMD_SMAC_RESULT(x) ((x) << S_FW_VI_MAC_CMD_SMAC_RESULT)
1420 #define G_FW_VI_MAC_CMD_SMAC_RESULT(x) \
1421 (((x) >> S_FW_VI_MAC_CMD_SMAC_RESULT) & M_FW_VI_MAC_CMD_SMAC_RESULT)
1423 #define S_FW_VI_MAC_CMD_IDX 0
1424 #define M_FW_VI_MAC_CMD_IDX 0x3ff
1425 #define V_FW_VI_MAC_CMD_IDX(x) ((x) << S_FW_VI_MAC_CMD_IDX)
1426 #define G_FW_VI_MAC_CMD_IDX(x) \
1427 (((x) >> S_FW_VI_MAC_CMD_IDX) & M_FW_VI_MAC_CMD_IDX)
1429 #define S_FW_VI_MAC_CMD_RAW_IDX 16
1430 #define M_FW_VI_MAC_CMD_RAW_IDX 0xffff
1431 #define V_FW_VI_MAC_CMD_RAW_IDX(x) ((x) << S_FW_VI_MAC_CMD_RAW_IDX)
1432 #define G_FW_VI_MAC_CMD_RAW_IDX(x) \
1433 (((x) >> S_FW_VI_MAC_CMD_RAW_IDX) & M_FW_VI_MAC_CMD_RAW_IDX)
1435 struct fw_vi_rxmode_cmd {
1437 __be32 retval_len16;
1438 __be32 mtu_to_vlanexen;
1442 #define S_FW_VI_RXMODE_CMD_VIID 0
1443 #define M_FW_VI_RXMODE_CMD_VIID 0xfff
1444 #define V_FW_VI_RXMODE_CMD_VIID(x) ((x) << S_FW_VI_RXMODE_CMD_VIID)
1445 #define G_FW_VI_RXMODE_CMD_VIID(x) \
1446 (((x) >> S_FW_VI_RXMODE_CMD_VIID) & M_FW_VI_RXMODE_CMD_VIID)
1448 #define S_FW_VI_RXMODE_CMD_MTU 16
1449 #define M_FW_VI_RXMODE_CMD_MTU 0xffff
1450 #define V_FW_VI_RXMODE_CMD_MTU(x) ((x) << S_FW_VI_RXMODE_CMD_MTU)
1451 #define G_FW_VI_RXMODE_CMD_MTU(x) \
1452 (((x) >> S_FW_VI_RXMODE_CMD_MTU) & M_FW_VI_RXMODE_CMD_MTU)
1454 #define S_FW_VI_RXMODE_CMD_PROMISCEN 14
1455 #define M_FW_VI_RXMODE_CMD_PROMISCEN 0x3
1456 #define V_FW_VI_RXMODE_CMD_PROMISCEN(x) ((x) << S_FW_VI_RXMODE_CMD_PROMISCEN)
1457 #define G_FW_VI_RXMODE_CMD_PROMISCEN(x) \
1458 (((x) >> S_FW_VI_RXMODE_CMD_PROMISCEN) & M_FW_VI_RXMODE_CMD_PROMISCEN)
1460 #define S_FW_VI_RXMODE_CMD_ALLMULTIEN 12
1461 #define M_FW_VI_RXMODE_CMD_ALLMULTIEN 0x3
1462 #define V_FW_VI_RXMODE_CMD_ALLMULTIEN(x) \
1463 ((x) << S_FW_VI_RXMODE_CMD_ALLMULTIEN)
1464 #define G_FW_VI_RXMODE_CMD_ALLMULTIEN(x) \
1465 (((x) >> S_FW_VI_RXMODE_CMD_ALLMULTIEN) & M_FW_VI_RXMODE_CMD_ALLMULTIEN)
1467 #define S_FW_VI_RXMODE_CMD_BROADCASTEN 10
1468 #define M_FW_VI_RXMODE_CMD_BROADCASTEN 0x3
1469 #define V_FW_VI_RXMODE_CMD_BROADCASTEN(x) \
1470 ((x) << S_FW_VI_RXMODE_CMD_BROADCASTEN)
1471 #define G_FW_VI_RXMODE_CMD_BROADCASTEN(x) \
1472 (((x) >> S_FW_VI_RXMODE_CMD_BROADCASTEN) & \
1473 M_FW_VI_RXMODE_CMD_BROADCASTEN)
1475 #define S_FW_VI_RXMODE_CMD_VLANEXEN 8
1476 #define M_FW_VI_RXMODE_CMD_VLANEXEN 0x3
1477 #define V_FW_VI_RXMODE_CMD_VLANEXEN(x) ((x) << S_FW_VI_RXMODE_CMD_VLANEXEN)
1478 #define G_FW_VI_RXMODE_CMD_VLANEXEN(x) \
1479 (((x) >> S_FW_VI_RXMODE_CMD_VLANEXEN) & M_FW_VI_RXMODE_CMD_VLANEXEN)
1481 struct fw_vi_enable_cmd {
1483 __be32 ien_to_len16;
1489 #define S_FW_VI_ENABLE_CMD_VIID 0
1490 #define M_FW_VI_ENABLE_CMD_VIID 0xfff
1491 #define V_FW_VI_ENABLE_CMD_VIID(x) ((x) << S_FW_VI_ENABLE_CMD_VIID)
1492 #define G_FW_VI_ENABLE_CMD_VIID(x) \
1493 (((x) >> S_FW_VI_ENABLE_CMD_VIID) & M_FW_VI_ENABLE_CMD_VIID)
1495 #define S_FW_VI_ENABLE_CMD_IEN 31
1496 #define M_FW_VI_ENABLE_CMD_IEN 0x1
1497 #define V_FW_VI_ENABLE_CMD_IEN(x) ((x) << S_FW_VI_ENABLE_CMD_IEN)
1498 #define G_FW_VI_ENABLE_CMD_IEN(x) \
1499 (((x) >> S_FW_VI_ENABLE_CMD_IEN) & M_FW_VI_ENABLE_CMD_IEN)
1500 #define F_FW_VI_ENABLE_CMD_IEN V_FW_VI_ENABLE_CMD_IEN(1U)
1502 #define S_FW_VI_ENABLE_CMD_EEN 30
1503 #define M_FW_VI_ENABLE_CMD_EEN 0x1
1504 #define V_FW_VI_ENABLE_CMD_EEN(x) ((x) << S_FW_VI_ENABLE_CMD_EEN)
1505 #define G_FW_VI_ENABLE_CMD_EEN(x) \
1506 (((x) >> S_FW_VI_ENABLE_CMD_EEN) & M_FW_VI_ENABLE_CMD_EEN)
1507 #define F_FW_VI_ENABLE_CMD_EEN V_FW_VI_ENABLE_CMD_EEN(1U)
1509 #define S_FW_VI_ENABLE_CMD_DCB_INFO 28
1510 #define M_FW_VI_ENABLE_CMD_DCB_INFO 0x1
1511 #define V_FW_VI_ENABLE_CMD_DCB_INFO(x) ((x) << S_FW_VI_ENABLE_CMD_DCB_INFO)
1512 #define G_FW_VI_ENABLE_CMD_DCB_INFO(x) \
1513 (((x) >> S_FW_VI_ENABLE_CMD_DCB_INFO) & M_FW_VI_ENABLE_CMD_DCB_INFO)
1514 #define F_FW_VI_ENABLE_CMD_DCB_INFO V_FW_VI_ENABLE_CMD_DCB_INFO(1U)
1516 /* VI VF stats offset definitions */
1517 #define VI_VF_NUM_STATS 16
1519 /* VI PF stats offset definitions */
1520 #define VI_PF_NUM_STATS 17
1521 enum fw_vi_stats_pf_index {
1522 FW_VI_PF_STAT_TX_BCAST_BYTES_IX,
1523 FW_VI_PF_STAT_TX_BCAST_FRAMES_IX,
1524 FW_VI_PF_STAT_TX_MCAST_BYTES_IX,
1525 FW_VI_PF_STAT_TX_MCAST_FRAMES_IX,
1526 FW_VI_PF_STAT_TX_UCAST_BYTES_IX,
1527 FW_VI_PF_STAT_TX_UCAST_FRAMES_IX,
1528 FW_VI_PF_STAT_TX_OFLD_BYTES_IX,
1529 FW_VI_PF_STAT_TX_OFLD_FRAMES_IX,
1530 FW_VI_PF_STAT_RX_BYTES_IX,
1531 FW_VI_PF_STAT_RX_FRAMES_IX,
1532 FW_VI_PF_STAT_RX_BCAST_BYTES_IX,
1533 FW_VI_PF_STAT_RX_BCAST_FRAMES_IX,
1534 FW_VI_PF_STAT_RX_MCAST_BYTES_IX,
1535 FW_VI_PF_STAT_RX_MCAST_FRAMES_IX,
1536 FW_VI_PF_STAT_RX_UCAST_BYTES_IX,
1537 FW_VI_PF_STAT_RX_UCAST_FRAMES_IX,
1538 FW_VI_PF_STAT_RX_ERR_FRAMES_IX
1541 struct fw_vi_stats_cmd {
1543 __be32 retval_len16;
1545 struct fw_vi_stats_ctl {
1556 struct fw_vi_stats_pf {
1557 __be64 tx_bcast_bytes;
1558 __be64 tx_bcast_frames;
1559 __be64 tx_mcast_bytes;
1560 __be64 tx_mcast_frames;
1561 __be64 tx_ucast_bytes;
1562 __be64 tx_ucast_frames;
1563 __be64 tx_offload_bytes;
1564 __be64 tx_offload_frames;
1566 __be64 rx_pf_frames;
1567 __be64 rx_bcast_bytes;
1568 __be64 rx_bcast_frames;
1569 __be64 rx_mcast_bytes;
1570 __be64 rx_mcast_frames;
1571 __be64 rx_ucast_bytes;
1572 __be64 rx_ucast_frames;
1573 __be64 rx_err_frames;
1575 struct fw_vi_stats_vf {
1576 __be64 tx_bcast_bytes;
1577 __be64 tx_bcast_frames;
1578 __be64 tx_mcast_bytes;
1579 __be64 tx_mcast_frames;
1580 __be64 tx_ucast_bytes;
1581 __be64 tx_ucast_frames;
1582 __be64 tx_drop_frames;
1583 __be64 tx_offload_bytes;
1584 __be64 tx_offload_frames;
1585 __be64 rx_bcast_bytes;
1586 __be64 rx_bcast_frames;
1587 __be64 rx_mcast_bytes;
1588 __be64 rx_mcast_frames;
1589 __be64 rx_ucast_bytes;
1590 __be64 rx_ucast_frames;
1591 __be64 rx_err_frames;
1596 #define S_FW_VI_STATS_CMD_VIID 0
1597 #define V_FW_VI_STATS_CMD_VIID(x) ((x) << S_FW_VI_STATS_CMD_VIID)
1599 #define S_FW_VI_STATS_CMD_NSTATS 12
1600 #define V_FW_VI_STATS_CMD_NSTATS(x) ((x) << S_FW_VI_STATS_CMD_NSTATS)
1602 #define S_FW_VI_STATS_CMD_IX 0
1603 #define V_FW_VI_STATS_CMD_IX(x) ((x) << S_FW_VI_STATS_CMD_IX)
1605 /* new 32-bit port capabilities bitmap (fw_port_cap32_t) */
1606 #define FW_PORT_CAP32_SPEED_100M 0x00000001UL
1607 #define FW_PORT_CAP32_SPEED_1G 0x00000002UL
1608 #define FW_PORT_CAP32_SPEED_10G 0x00000004UL
1609 #define FW_PORT_CAP32_SPEED_25G 0x00000008UL
1610 #define FW_PORT_CAP32_SPEED_40G 0x00000010UL
1611 #define FW_PORT_CAP32_SPEED_50G 0x00000020UL
1612 #define FW_PORT_CAP32_SPEED_100G 0x00000040UL
1613 #define FW_PORT_CAP32_FC_RX 0x00010000UL
1614 #define FW_PORT_CAP32_FC_TX 0x00020000UL
1615 #define FW_PORT_CAP32_802_3_PAUSE 0x00040000UL
1616 #define FW_PORT_CAP32_802_3_ASM_DIR 0x00080000UL
1617 #define FW_PORT_CAP32_ANEG 0x00100000UL
1618 #define FW_PORT_CAP32_MDIX 0x00200000UL
1619 #define FW_PORT_CAP32_MDIAUTO 0x00400000UL
1620 #define FW_PORT_CAP32_FEC_RS 0x00800000UL
1621 #define FW_PORT_CAP32_FEC_BASER_RS 0x01000000UL
1622 #define FW_PORT_CAP32_FEC_NO_FEC 0x02000000UL
1623 #define FW_PORT_CAP32_FORCE_PAUSE 0x10000000UL
1624 #define FW_PORT_CAP32_FORCE_FEC 0x20000000UL
1626 #define S_FW_PORT_CAP32_SPEED 0
1627 #define M_FW_PORT_CAP32_SPEED 0xfff
1628 #define V_FW_PORT_CAP32_SPEED(x) ((x) << S_FW_PORT_CAP32_SPEED)
1629 #define G_FW_PORT_CAP32_SPEED(x) \
1630 (((x) >> S_FW_PORT_CAP32_SPEED) & M_FW_PORT_CAP32_SPEED)
1632 #define S_FW_PORT_CAP32_FC 16
1633 #define M_FW_PORT_CAP32_FC 0x3
1634 #define V_FW_PORT_CAP32_FC(x) ((x) << S_FW_PORT_CAP32_FC)
1636 #define S_FW_PORT_CAP32_802_3 18
1637 #define M_FW_PORT_CAP32_802_3 0x3
1638 #define V_FW_PORT_CAP32_802_3(x) ((x) << S_FW_PORT_CAP32_802_3)
1640 enum fw_port_mdi32 {
1641 FW_PORT_CAP32_MDI_AUTO = 1,
1644 #define S_FW_PORT_CAP32_MDI 21
1645 #define M_FW_PORT_CAP32_MDI 3
1646 #define V_FW_PORT_CAP32_MDI(x) ((x) << S_FW_PORT_CAP32_MDI)
1647 #define G_FW_PORT_CAP32_MDI(x) \
1648 (((x) >> S_FW_PORT_CAP32_MDI) & M_FW_PORT_CAP32_MDI)
1650 #define S_FW_PORT_CAP32_FEC 23
1651 #define M_FW_PORT_CAP32_FEC 0x1f
1652 #define V_FW_PORT_CAP32_FEC(x) ((x) << S_FW_PORT_CAP32_FEC)
1654 enum fw_port_action {
1655 FW_PORT_ACTION_L1_CFG32 = 0x0009,
1656 FW_PORT_ACTION_GET_PORT_INFO32 = 0x000a,
1659 struct fw_port_cmd {
1660 __be32 op_to_portid;
1661 __be32 action_to_len16;
1663 struct fw_port_l1cfg {
1667 struct fw_port_l2cfg {
1669 __u8 ovlan3_to_ivlan0;
1671 __be16 txipg_force_pinfo;
1682 struct fw_port_info {
1683 __be32 lstatus_to_modtype;
1694 struct fw_port_diags {
1700 struct fw_port_dcb_pgid {
1707 struct fw_port_dcb_pgrate {
1711 __u8 num_tcs_supported;
1715 struct fw_port_dcb_priorate {
1719 __u8 strict_priorate[8];
1721 struct fw_port_dcb_pfc {
1728 struct fw_port_app_priority {
1737 struct fw_port_dcb_control {
1740 __be16 dcb_version_to_app_state;
1745 struct fw_port_l1cfg32 {
1749 struct fw_port_info32 {
1750 __be32 lstatus32_to_cbllen32;
1751 __be32 auxlinfo32_mtu32;
1760 #define S_FW_PORT_CMD_PORTID 0
1761 #define M_FW_PORT_CMD_PORTID 0xf
1762 #define V_FW_PORT_CMD_PORTID(x) ((x) << S_FW_PORT_CMD_PORTID)
1763 #define G_FW_PORT_CMD_PORTID(x) \
1764 (((x) >> S_FW_PORT_CMD_PORTID) & M_FW_PORT_CMD_PORTID)
1766 #define S_FW_PORT_CMD_ACTION 16
1767 #define M_FW_PORT_CMD_ACTION 0xffff
1768 #define V_FW_PORT_CMD_ACTION(x) ((x) << S_FW_PORT_CMD_ACTION)
1769 #define G_FW_PORT_CMD_ACTION(x) \
1770 (((x) >> S_FW_PORT_CMD_ACTION) & M_FW_PORT_CMD_ACTION)
1772 #define S_FW_PORT_CMD_LSTATUS 31
1773 #define M_FW_PORT_CMD_LSTATUS 0x1
1774 #define V_FW_PORT_CMD_LSTATUS(x) ((x) << S_FW_PORT_CMD_LSTATUS)
1775 #define G_FW_PORT_CMD_LSTATUS(x) \
1776 (((x) >> S_FW_PORT_CMD_LSTATUS) & M_FW_PORT_CMD_LSTATUS)
1777 #define F_FW_PORT_CMD_LSTATUS V_FW_PORT_CMD_LSTATUS(1U)
1779 #define S_FW_PORT_CMD_LSPEED 24
1780 #define M_FW_PORT_CMD_LSPEED 0x3f
1781 #define V_FW_PORT_CMD_LSPEED(x) ((x) << S_FW_PORT_CMD_LSPEED)
1782 #define G_FW_PORT_CMD_LSPEED(x) \
1783 (((x) >> S_FW_PORT_CMD_LSPEED) & M_FW_PORT_CMD_LSPEED)
1785 #define S_FW_PORT_CMD_TXPAUSE 23
1786 #define M_FW_PORT_CMD_TXPAUSE 0x1
1787 #define V_FW_PORT_CMD_TXPAUSE(x) ((x) << S_FW_PORT_CMD_TXPAUSE)
1788 #define G_FW_PORT_CMD_TXPAUSE(x) \
1789 (((x) >> S_FW_PORT_CMD_TXPAUSE) & M_FW_PORT_CMD_TXPAUSE)
1790 #define F_FW_PORT_CMD_TXPAUSE V_FW_PORT_CMD_TXPAUSE(1U)
1792 #define S_FW_PORT_CMD_RXPAUSE 22
1793 #define M_FW_PORT_CMD_RXPAUSE 0x1
1794 #define V_FW_PORT_CMD_RXPAUSE(x) ((x) << S_FW_PORT_CMD_RXPAUSE)
1795 #define G_FW_PORT_CMD_RXPAUSE(x) \
1796 (((x) >> S_FW_PORT_CMD_RXPAUSE) & M_FW_PORT_CMD_RXPAUSE)
1797 #define F_FW_PORT_CMD_RXPAUSE V_FW_PORT_CMD_RXPAUSE(1U)
1799 #define S_FW_PORT_CMD_PTYPE 8
1800 #define M_FW_PORT_CMD_PTYPE 0x1f
1801 #define V_FW_PORT_CMD_PTYPE(x) ((x) << S_FW_PORT_CMD_PTYPE)
1802 #define G_FW_PORT_CMD_PTYPE(x) \
1803 (((x) >> S_FW_PORT_CMD_PTYPE) & M_FW_PORT_CMD_PTYPE)
1805 #define S_FW_PORT_CMD_LSTATUS32 31
1806 #define M_FW_PORT_CMD_LSTATUS32 0x1
1807 #define V_FW_PORT_CMD_LSTATUS32(x) ((x) << S_FW_PORT_CMD_LSTATUS32)
1808 #define F_FW_PORT_CMD_LSTATUS32 V_FW_PORT_CMD_LSTATUS32(1U)
1810 #define S_FW_PORT_CMD_LINKDNRC32 28
1811 #define M_FW_PORT_CMD_LINKDNRC32 0x7
1812 #define G_FW_PORT_CMD_LINKDNRC32(x) \
1813 (((x) >> S_FW_PORT_CMD_LINKDNRC32) & M_FW_PORT_CMD_LINKDNRC32)
1815 #define S_FW_PORT_CMD_MDIOCAP32 26
1816 #define M_FW_PORT_CMD_MDIOCAP32 0x1
1817 #define V_FW_PORT_CMD_MDIOCAP32(x) ((x) << S_FW_PORT_CMD_MDIOCAP32)
1818 #define F_FW_PORT_CMD_MDIOCAP32 V_FW_PORT_CMD_MDIOCAP32(1U)
1820 #define S_FW_PORT_CMD_MDIOADDR32 21
1821 #define M_FW_PORT_CMD_MDIOADDR32 0x1f
1822 #define G_FW_PORT_CMD_MDIOADDR32(x) \
1823 (((x) >> S_FW_PORT_CMD_MDIOADDR32) & M_FW_PORT_CMD_MDIOADDR32)
1825 #define S_FW_PORT_CMD_PORTTYPE32 13
1826 #define M_FW_PORT_CMD_PORTTYPE32 0xff
1827 #define G_FW_PORT_CMD_PORTTYPE32(x) \
1828 (((x) >> S_FW_PORT_CMD_PORTTYPE32) & M_FW_PORT_CMD_PORTTYPE32)
1830 #define S_FW_PORT_CMD_MODTYPE32 8
1831 #define M_FW_PORT_CMD_MODTYPE32 0x1f
1832 #define G_FW_PORT_CMD_MODTYPE32(x) \
1833 (((x) >> S_FW_PORT_CMD_MODTYPE32) & M_FW_PORT_CMD_MODTYPE32)
1836 * These are configured into the VPD and hence tools that generate
1837 * VPD may use this enumeration.
1838 * extPHY #lanes T4_I2C extI2C BP_Eq BP_ANEG Speed
1841 * Update the Common Code t4_hw.c:t4_get_port_type_description()
1842 * with any new Firmware Port Technology Types!
1845 FW_PORT_TYPE_FIBER_XFI = 0, /* Y, 1, N, Y, N, N, 10G */
1846 FW_PORT_TYPE_FIBER_XAUI = 1, /* Y, 4, N, Y, N, N, 10G */
1847 FW_PORT_TYPE_BT_SGMII = 2, /* Y, 1, No, No, No, No, 1G/100M */
1848 FW_PORT_TYPE_BT_XFI = 3, /* Y, 1, No, No, No, No, 10G */
1849 FW_PORT_TYPE_BT_XAUI = 4, /* Y, 4, No, No, No, No, 10G/1G/100M? */
1850 FW_PORT_TYPE_KX4 = 5, /* No, 4, No, No, Yes, Yes, 10G */
1851 FW_PORT_TYPE_CX4 = 6, /* No, 4, No, No, No, No, 10G */
1852 FW_PORT_TYPE_KX = 7, /* No, 1, No, No, Yes, No, 1G */
1853 FW_PORT_TYPE_KR = 8, /* No, 1, No, No, Yes, Yes, 10G */
1854 FW_PORT_TYPE_SFP = 9, /* No, 1, Yes, No, No, No, 10G */
1855 FW_PORT_TYPE_BP_AP = 10,
1856 /* No, 1, No, No, Yes, Yes, 10G, BP ANGE */
1857 FW_PORT_TYPE_BP4_AP = 11,
1858 /* No, 4, No, No, Yes, Yes, 10G, BP ANGE */
1859 FW_PORT_TYPE_QSFP_10G = 12, /* No, 1, Yes, No, No, No, 10G */
1860 FW_PORT_TYPE_QSA = 13, /* No, 1, Yes, No, No, No, 10G */
1861 FW_PORT_TYPE_QSFP = 14, /* No, 4, Yes, No, No, No, 40G */
1862 FW_PORT_TYPE_BP40_BA = 15,
1863 /* No, 4, No, No, Yes, Yes, 40G/10G/1G, BP ANGE */
1864 FW_PORT_TYPE_KR4_100G = 16, /* No, 4, 100G/40G/25G, Backplane */
1865 FW_PORT_TYPE_CR4_QSFP = 17, /* No, 4, 100G/40G/25G */
1866 FW_PORT_TYPE_CR_QSFP = 18, /* No, 1, 25G Spider cable */
1867 FW_PORT_TYPE_CR2_QSFP = 19, /* No, 2, 50G */
1868 FW_PORT_TYPE_SFP28 = 20, /* No, 1, 25G/10G/1G */
1869 FW_PORT_TYPE_KR_SFP28 = 21, /* No, 1, 25G/10G/1G using Backplane */
1870 FW_PORT_TYPE_NONE = M_FW_PORT_CMD_PTYPE
1873 /* These are read from module's EEPROM and determined once the
1874 * module is inserted.
1876 enum fw_port_module_type {
1877 FW_PORT_MOD_TYPE_NA = 0x0,
1878 FW_PORT_MOD_TYPE_LR = 0x1,
1879 FW_PORT_MOD_TYPE_SR = 0x2,
1880 FW_PORT_MOD_TYPE_ER = 0x3,
1881 FW_PORT_MOD_TYPE_TWINAX_PASSIVE = 0x4,
1882 FW_PORT_MOD_TYPE_TWINAX_ACTIVE = 0x5,
1883 FW_PORT_MOD_TYPE_LRM = 0x6,
1884 FW_PORT_MOD_TYPE_ERROR = M_FW_PORT_CMD_MODTYPE32 - 3,
1885 FW_PORT_MOD_TYPE_UNKNOWN = M_FW_PORT_CMD_MODTYPE32 - 2,
1886 FW_PORT_MOD_TYPE_NOTSUPPORTED = M_FW_PORT_CMD_MODTYPE32 - 1,
1887 FW_PORT_MOD_TYPE_NONE = M_FW_PORT_CMD_MODTYPE32
1890 /* used by FW and tools may use this to generate VPD */
1891 enum fw_port_mod_sub_type {
1892 FW_PORT_MOD_SUB_TYPE_NA,
1893 FW_PORT_MOD_SUB_TYPE_MV88E114X = 0x1,
1894 FW_PORT_MOD_SUB_TYPE_TN8022 = 0x2,
1895 FW_PORT_MOD_SUB_TYPE_AQ1202 = 0x3,
1896 FW_PORT_MOD_SUB_TYPE_88x3120 = 0x4,
1897 FW_PORT_MOD_SUB_TYPE_BCM84834 = 0x5,
1898 FW_PORT_MOD_SUB_TYPE_BCM5482 = 0x6,
1899 FW_PORT_MOD_SUB_TYPE_BCM84856 = 0x7,
1900 FW_PORT_MOD_SUB_TYPE_BT_VSC8634 = 0x8,
1903 * The following will never been in the VPD. They are TWINAX cable
1904 * lengths decoded from SFP+ module i2c PROMs. These should almost
1905 * certainly go somewhere else ...
1907 FW_PORT_MOD_SUB_TYPE_TWINAX_1 = 0x9,
1908 FW_PORT_MOD_SUB_TYPE_TWINAX_3 = 0xA,
1909 FW_PORT_MOD_SUB_TYPE_TWINAX_5 = 0xB,
1910 FW_PORT_MOD_SUB_TYPE_TWINAX_7 = 0xC,
1913 /* link down reason codes (3b) */
1914 enum fw_port_link_dn_rc {
1915 FW_PORT_LINK_DN_RC_NONE,
1916 FW_PORT_LINK_DN_RC_REMFLT, /* Remote fault detected */
1917 FW_PORT_LINK_DN_ANEG_F, /* Auto-negotiation fault */
1918 FW_PORT_LINK_DN_RESERVED3,
1919 FW_PORT_LINK_DN_OVERHEAT, /* Port overheated */
1920 FW_PORT_LINK_DN_UNKNOWN, /* Unable to determine reason */
1921 FW_PORT_LINK_DN_RX_LOS, /* No RX signal detected */
1922 FW_PORT_LINK_DN_RESERVED7
1926 #define FW_NUM_PORT_STATS 50
1927 #define FW_NUM_PORT_TX_STATS 23
1928 #define FW_NUM_PORT_RX_STATS 27
1930 enum fw_port_stats_tx_index {
1931 FW_STAT_TX_PORT_BYTES_IX,
1932 FW_STAT_TX_PORT_FRAMES_IX,
1933 FW_STAT_TX_PORT_BCAST_IX,
1934 FW_STAT_TX_PORT_MCAST_IX,
1935 FW_STAT_TX_PORT_UCAST_IX,
1936 FW_STAT_TX_PORT_ERROR_IX,
1937 FW_STAT_TX_PORT_64B_IX,
1938 FW_STAT_TX_PORT_65B_127B_IX,
1939 FW_STAT_TX_PORT_128B_255B_IX,
1940 FW_STAT_TX_PORT_256B_511B_IX,
1941 FW_STAT_TX_PORT_512B_1023B_IX,
1942 FW_STAT_TX_PORT_1024B_1518B_IX,
1943 FW_STAT_TX_PORT_1519B_MAX_IX,
1944 FW_STAT_TX_PORT_DROP_IX,
1945 FW_STAT_TX_PORT_PAUSE_IX,
1946 FW_STAT_TX_PORT_PPP0_IX,
1947 FW_STAT_TX_PORT_PPP1_IX,
1948 FW_STAT_TX_PORT_PPP2_IX,
1949 FW_STAT_TX_PORT_PPP3_IX,
1950 FW_STAT_TX_PORT_PPP4_IX,
1951 FW_STAT_TX_PORT_PPP5_IX,
1952 FW_STAT_TX_PORT_PPP6_IX,
1953 FW_STAT_TX_PORT_PPP7_IX
1956 enum fw_port_stat_rx_index {
1957 FW_STAT_RX_PORT_BYTES_IX,
1958 FW_STAT_RX_PORT_FRAMES_IX,
1959 FW_STAT_RX_PORT_BCAST_IX,
1960 FW_STAT_RX_PORT_MCAST_IX,
1961 FW_STAT_RX_PORT_UCAST_IX,
1962 FW_STAT_RX_PORT_MTU_ERROR_IX,
1963 FW_STAT_RX_PORT_MTU_CRC_ERROR_IX,
1964 FW_STAT_RX_PORT_CRC_ERROR_IX,
1965 FW_STAT_RX_PORT_LEN_ERROR_IX,
1966 FW_STAT_RX_PORT_SYM_ERROR_IX,
1967 FW_STAT_RX_PORT_64B_IX,
1968 FW_STAT_RX_PORT_65B_127B_IX,
1969 FW_STAT_RX_PORT_128B_255B_IX,
1970 FW_STAT_RX_PORT_256B_511B_IX,
1971 FW_STAT_RX_PORT_512B_1023B_IX,
1972 FW_STAT_RX_PORT_1024B_1518B_IX,
1973 FW_STAT_RX_PORT_1519B_MAX_IX,
1974 FW_STAT_RX_PORT_PAUSE_IX,
1975 FW_STAT_RX_PORT_PPP0_IX,
1976 FW_STAT_RX_PORT_PPP1_IX,
1977 FW_STAT_RX_PORT_PPP2_IX,
1978 FW_STAT_RX_PORT_PPP3_IX,
1979 FW_STAT_RX_PORT_PPP4_IX,
1980 FW_STAT_RX_PORT_PPP5_IX,
1981 FW_STAT_RX_PORT_PPP6_IX,
1982 FW_STAT_RX_PORT_PPP7_IX,
1983 FW_STAT_RX_PORT_LESS_64B_IX
1986 struct fw_port_stats_cmd {
1987 __be32 op_to_portid;
1988 __be32 retval_len16;
1989 union fw_port_stats {
1990 struct fw_port_stats_ctl {
2002 struct fw_port_stats_all {
2011 __be64 tx_128b_255b;
2012 __be64 tx_256b_511b;
2013 __be64 tx_512b_1023b;
2014 __be64 tx_1024b_1518b;
2015 __be64 tx_1519b_max;
2031 __be64 rx_mtu_error;
2032 __be64 rx_mtu_crc_error;
2033 __be64 rx_crc_error;
2034 __be64 rx_len_error;
2035 __be64 rx_sym_error;
2038 __be64 rx_128b_255b;
2039 __be64 rx_256b_511b;
2040 __be64 rx_512b_1023b;
2041 __be64 rx_1024b_1518b;
2042 __be64 rx_1519b_max;
2059 struct fw_rss_ind_tbl_cmd {
2061 __be32 retval_len16;
2069 __be32 iq12_to_iq14;
2070 __be32 iq15_to_iq17;
2071 __be32 iq18_to_iq20;
2072 __be32 iq21_to_iq23;
2073 __be32 iq24_to_iq26;
2074 __be32 iq27_to_iq29;
2079 #define S_FW_RSS_IND_TBL_CMD_VIID 0
2080 #define M_FW_RSS_IND_TBL_CMD_VIID 0xfff
2081 #define V_FW_RSS_IND_TBL_CMD_VIID(x) ((x) << S_FW_RSS_IND_TBL_CMD_VIID)
2082 #define G_FW_RSS_IND_TBL_CMD_VIID(x) \
2083 (((x) >> S_FW_RSS_IND_TBL_CMD_VIID) & M_FW_RSS_IND_TBL_CMD_VIID)
2085 #define S_FW_RSS_IND_TBL_CMD_IQ0 20
2086 #define M_FW_RSS_IND_TBL_CMD_IQ0 0x3ff
2087 #define V_FW_RSS_IND_TBL_CMD_IQ0(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ0)
2088 #define G_FW_RSS_IND_TBL_CMD_IQ0(x) \
2089 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ0) & M_FW_RSS_IND_TBL_CMD_IQ0)
2091 #define S_FW_RSS_IND_TBL_CMD_IQ1 10
2092 #define M_FW_RSS_IND_TBL_CMD_IQ1 0x3ff
2093 #define V_FW_RSS_IND_TBL_CMD_IQ1(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ1)
2094 #define G_FW_RSS_IND_TBL_CMD_IQ1(x) \
2095 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ1) & M_FW_RSS_IND_TBL_CMD_IQ1)
2097 #define S_FW_RSS_IND_TBL_CMD_IQ2 0
2098 #define M_FW_RSS_IND_TBL_CMD_IQ2 0x3ff
2099 #define V_FW_RSS_IND_TBL_CMD_IQ2(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ2)
2100 #define G_FW_RSS_IND_TBL_CMD_IQ2(x) \
2101 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ2) & M_FW_RSS_IND_TBL_CMD_IQ2)
2103 struct fw_rss_glb_config_cmd {
2105 __be32 retval_len16;
2106 union fw_rss_glb_config {
2107 struct fw_rss_glb_config_manual {
2113 struct fw_rss_glb_config_basicvirtual {
2114 __be32 mode_keymode;
2115 __be32 synmapen_to_hashtoeplitz;
2122 #define S_FW_RSS_GLB_CONFIG_CMD_MODE 28
2123 #define M_FW_RSS_GLB_CONFIG_CMD_MODE 0xf
2124 #define G_FW_RSS_GLB_CONFIG_CMD_MODE(x) \
2125 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_MODE) & M_FW_RSS_GLB_CONFIG_CMD_MODE)
2127 #define FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL 1
2129 #define S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN 8
2130 #define V_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(x) \
2131 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN)
2132 #define F_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN V_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(1U)
2134 #define S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 7
2135 #define V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(x) \
2136 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6)
2137 #define F_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 \
2138 V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(1U)
2140 #define S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 6
2141 #define V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(x) \
2142 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6)
2143 #define F_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 \
2144 V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(1U)
2146 #define S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 5
2147 #define V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(x) \
2148 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4)
2149 #define F_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 \
2150 V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(1U)
2152 #define S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 4
2153 #define V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(x) \
2154 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4)
2155 #define F_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 \
2156 V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(1U)
2158 #define S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN 3
2159 #define V_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(x) \
2160 ((x) << S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN)
2161 #define F_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN V_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(1U)
2163 #define S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN 2
2164 #define V_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(x) \
2165 ((x) << S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN)
2166 #define F_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN V_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(1U)
2168 #define S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP 1
2169 #define V_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(x) \
2170 ((x) << S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP)
2171 #define F_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP \
2172 V_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(1U)
2174 #define S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ 0
2175 #define V_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(x) \
2176 ((x) << S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ)
2177 #define F_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ \
2178 V_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(1U)
2180 struct fw_rss_vi_config_cmd {
2182 __be32 retval_len16;
2183 union fw_rss_vi_config {
2184 struct fw_rss_vi_config_manual {
2189 struct fw_rss_vi_config_basicvirtual {
2191 __be32 defaultq_to_udpen;
2198 #define S_FW_RSS_VI_CONFIG_CMD_VIID 0
2199 #define M_FW_RSS_VI_CONFIG_CMD_VIID 0xfff
2200 #define V_FW_RSS_VI_CONFIG_CMD_VIID(x) ((x) << S_FW_RSS_VI_CONFIG_CMD_VIID)
2201 #define G_FW_RSS_VI_CONFIG_CMD_VIID(x) \
2202 (((x) >> S_FW_RSS_VI_CONFIG_CMD_VIID) & M_FW_RSS_VI_CONFIG_CMD_VIID)
2204 #define S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ 16
2205 #define M_FW_RSS_VI_CONFIG_CMD_DEFAULTQ 0x3ff
2206 #define V_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) \
2207 ((x) << S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ)
2208 #define G_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) \
2209 (((x) >> S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ) & \
2210 M_FW_RSS_VI_CONFIG_CMD_DEFAULTQ)
2212 #define S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN 4
2213 #define M_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN 0x1
2214 #define V_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(x) \
2215 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)
2216 #define G_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(x) \
2217 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) & \
2218 M_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)
2219 #define F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN \
2220 V_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(1U)
2222 #define S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN 3
2223 #define M_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN 0x1
2224 #define V_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(x) \
2225 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
2226 #define G_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(x) \
2227 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) & \
2228 M_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
2229 #define F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN \
2230 V_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(1U)
2232 #define S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN 2
2233 #define M_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN 0x1
2234 #define V_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(x) \
2235 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN)
2236 #define G_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(x) \
2237 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) & \
2238 M_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN)
2239 #define F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN \
2240 V_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(1U)
2242 #define S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN 1
2243 #define M_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN 0x1
2244 #define V_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(x) \
2245 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
2246 #define G_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(x) \
2247 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) & \
2248 M_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
2249 #define F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN \
2250 V_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(1U)
2252 #define S_FW_RSS_VI_CONFIG_CMD_UDPEN 0
2253 #define M_FW_RSS_VI_CONFIG_CMD_UDPEN 0x1
2254 #define V_FW_RSS_VI_CONFIG_CMD_UDPEN(x) ((x) << S_FW_RSS_VI_CONFIG_CMD_UDPEN)
2255 #define G_FW_RSS_VI_CONFIG_CMD_UDPEN(x) \
2256 (((x) >> S_FW_RSS_VI_CONFIG_CMD_UDPEN) & M_FW_RSS_VI_CONFIG_CMD_UDPEN)
2257 #define F_FW_RSS_VI_CONFIG_CMD_UDPEN V_FW_RSS_VI_CONFIG_CMD_UDPEN(1U)
2259 struct fw_clip_cmd {
2261 __be32 alloc_to_len16;
2267 #define S_FW_CLIP_CMD_ALLOC 31
2268 #define V_FW_CLIP_CMD_ALLOC(x) ((x) << S_FW_CLIP_CMD_ALLOC)
2269 #define F_FW_CLIP_CMD_ALLOC V_FW_CLIP_CMD_ALLOC(1U)
2271 #define S_FW_CLIP_CMD_FREE 30
2272 #define V_FW_CLIP_CMD_FREE(x) ((x) << S_FW_CLIP_CMD_FREE)
2273 #define F_FW_CLIP_CMD_FREE V_FW_CLIP_CMD_FREE(1U)
2275 /******************************************************************************
2276 * D E B U G C O M M A N D s
2277 ******************************************************/
2279 struct fw_debug_cmd {
2283 struct fw_debug_assert {
2288 __u8 filename_0_7[8];
2289 __u8 filename_8_15[8];
2292 struct fw_debug_prt {
2295 __be32 dprtstrparam0;
2296 __be32 dprtstrparam1;
2297 __be32 dprtstrparam2;
2298 __be32 dprtstrparam3;
2303 #define S_FW_DEBUG_CMD_TYPE 0
2304 #define M_FW_DEBUG_CMD_TYPE 0xff
2305 #define V_FW_DEBUG_CMD_TYPE(x) ((x) << S_FW_DEBUG_CMD_TYPE)
2306 #define G_FW_DEBUG_CMD_TYPE(x) \
2307 (((x) >> S_FW_DEBUG_CMD_TYPE) & M_FW_DEBUG_CMD_TYPE)
2309 /******************************************************************************
2310 * P C I E F W R E G I S T E R
2311 **************************************/
2314 * Register definitions for the PCIE_FW register which the firmware uses
2315 * to retain status across RESETs. This register should be considered
2316 * as a READ-ONLY register for Host Software and only to be used to
2317 * track firmware initialization/error state, etc.
2319 #define S_PCIE_FW_ERR 31
2320 #define M_PCIE_FW_ERR 0x1
2321 #define V_PCIE_FW_ERR(x) ((x) << S_PCIE_FW_ERR)
2322 #define G_PCIE_FW_ERR(x) (((x) >> S_PCIE_FW_ERR) & M_PCIE_FW_ERR)
2323 #define F_PCIE_FW_ERR V_PCIE_FW_ERR(1U)
2325 #define S_PCIE_FW_INIT 30
2326 #define M_PCIE_FW_INIT 0x1
2327 #define V_PCIE_FW_INIT(x) ((x) << S_PCIE_FW_INIT)
2328 #define G_PCIE_FW_INIT(x) (((x) >> S_PCIE_FW_INIT) & M_PCIE_FW_INIT)
2329 #define F_PCIE_FW_INIT V_PCIE_FW_INIT(1U)
2331 #define S_PCIE_FW_HALT 29
2332 #define M_PCIE_FW_HALT 0x1
2333 #define V_PCIE_FW_HALT(x) ((x) << S_PCIE_FW_HALT)
2334 #define G_PCIE_FW_HALT(x) (((x) >> S_PCIE_FW_HALT) & M_PCIE_FW_HALT)
2335 #define F_PCIE_FW_HALT V_PCIE_FW_HALT(1U)
2337 #define S_PCIE_FW_EVAL 24
2338 #define M_PCIE_FW_EVAL 0x7
2339 #define V_PCIE_FW_EVAL(x) ((x) << S_PCIE_FW_EVAL)
2340 #define G_PCIE_FW_EVAL(x) (((x) >> S_PCIE_FW_EVAL) & M_PCIE_FW_EVAL)
2342 #define S_PCIE_FW_MASTER_VLD 15
2343 #define M_PCIE_FW_MASTER_VLD 0x1
2344 #define V_PCIE_FW_MASTER_VLD(x) ((x) << S_PCIE_FW_MASTER_VLD)
2345 #define G_PCIE_FW_MASTER_VLD(x) \
2346 (((x) >> S_PCIE_FW_MASTER_VLD) & M_PCIE_FW_MASTER_VLD)
2347 #define F_PCIE_FW_MASTER_VLD V_PCIE_FW_MASTER_VLD(1U)
2349 #define S_PCIE_FW_MASTER 12
2350 #define M_PCIE_FW_MASTER 0x7
2351 #define V_PCIE_FW_MASTER(x) ((x) << S_PCIE_FW_MASTER)
2352 #define G_PCIE_FW_MASTER(x) (((x) >> S_PCIE_FW_MASTER) & M_PCIE_FW_MASTER)
2354 /******************************************************************************
2355 * B I N A R Y H E A D E R F O R M A T
2356 **********************************************/
2359 * firmware binary header format
2363 __u8 chip; /* terminator chip family */
2364 __be16 len512; /* bin length in units of 512-bytes */
2365 __be32 fw_ver; /* firmware version */
2366 __be32 tp_microcode_ver; /* tcp processor microcode version */
2371 __u8 intfver_iscsipdu;
2373 __u8 intfver_fcoepdu;
2377 __u32 magic; /* runtime or bootstrap fw */
2379 __be32 reserved6[23];
2382 #define S_FW_HDR_FW_VER_MAJOR 24
2383 #define M_FW_HDR_FW_VER_MAJOR 0xff
2384 #define V_FW_HDR_FW_VER_MAJOR(x) \
2385 ((x) << S_FW_HDR_FW_VER_MAJOR)
2386 #define G_FW_HDR_FW_VER_MAJOR(x) \
2387 (((x) >> S_FW_HDR_FW_VER_MAJOR) & M_FW_HDR_FW_VER_MAJOR)
2389 #define S_FW_HDR_FW_VER_MINOR 16
2390 #define M_FW_HDR_FW_VER_MINOR 0xff
2391 #define V_FW_HDR_FW_VER_MINOR(x) \
2392 ((x) << S_FW_HDR_FW_VER_MINOR)
2393 #define G_FW_HDR_FW_VER_MINOR(x) \
2394 (((x) >> S_FW_HDR_FW_VER_MINOR) & M_FW_HDR_FW_VER_MINOR)
2396 #define S_FW_HDR_FW_VER_MICRO 8
2397 #define M_FW_HDR_FW_VER_MICRO 0xff
2398 #define V_FW_HDR_FW_VER_MICRO(x) \
2399 ((x) << S_FW_HDR_FW_VER_MICRO)
2400 #define G_FW_HDR_FW_VER_MICRO(x) \
2401 (((x) >> S_FW_HDR_FW_VER_MICRO) & M_FW_HDR_FW_VER_MICRO)
2403 #define S_FW_HDR_FW_VER_BUILD 0
2404 #define M_FW_HDR_FW_VER_BUILD 0xff
2405 #define V_FW_HDR_FW_VER_BUILD(x) \
2406 ((x) << S_FW_HDR_FW_VER_BUILD)
2407 #define G_FW_HDR_FW_VER_BUILD(x) \
2408 (((x) >> S_FW_HDR_FW_VER_BUILD) & M_FW_HDR_FW_VER_BUILD)
2410 #endif /* _T4FW_INTERFACE_H_ */