1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2017 Cavium, Inc
8 #include <rte_bus_pci.h>
10 #include <octeontx_mbox.h>
12 #include "ssovf_evdev.h"
13 #include "timvf_evdev.h"
15 #ifndef PCI_VENDOR_ID_CAVIUM
16 #define PCI_VENDOR_ID_CAVIUM (0x177D)
19 #define PCI_DEVICE_ID_OCTEONTX_TIM_VF (0xA051)
20 #define TIM_MAX_RINGS (64)
33 struct timvf_res rings[TIM_MAX_RINGS];
36 static struct timdev tdev;
41 uint16_t global_domain = octeontx_get_global_domain();
44 for (i = 0; i < tdev.total_timvfs; i++) {
45 if (tdev.rings[i].domain != global_domain)
47 if (tdev.rings[i].in_use)
50 tdev.rings[i].in_use = true;
51 return tdev.rings[i].vfid;
58 timvf_release_ring(uint8_t tim_ring_id)
60 uint16_t global_domain = octeontx_get_global_domain();
63 for (i = 0; i < tdev.total_timvfs; i++) {
64 if (tdev.rings[i].domain != global_domain)
66 if (tdev.rings[i].vfid == tim_ring_id)
67 tdev.rings[i].in_use = false;
72 timvf_bar(uint8_t vfid, uint8_t bar)
74 uint16_t global_domain = octeontx_get_global_domain();
75 struct timvf_res *res = NULL;
78 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
81 for (i = 0; i < tdev.total_timvfs; i++) {
82 if (tdev.rings[i].domain != global_domain)
84 if (tdev.rings[i].vfid == vfid)
103 timvf_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
107 struct timvf_res *res;
109 RTE_SET_USED(pci_drv);
111 /* For secondary processes, the primary has done all the work */
112 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
115 if (pci_dev->mem_resource[0].addr == NULL ||
116 pci_dev->mem_resource[4].addr == NULL) {
117 timvf_log_err("Empty bars %p %p",
118 pci_dev->mem_resource[0].addr,
119 pci_dev->mem_resource[4].addr);
123 val = rte_read64((uint8_t *)pci_dev->mem_resource[0].addr +
124 0x100 /* TIM_VRINGX_BASE */);
125 vfid = (val >> 23) & 0xff;
126 if (vfid >= TIM_MAX_RINGS) {
127 timvf_log_err("Invalid vfid(%d/%d)", vfid, TIM_MAX_RINGS);
131 res = &tdev.rings[tdev.total_timvfs];
133 res->bar0 = pci_dev->mem_resource[0].addr;
134 res->bar2 = pci_dev->mem_resource[2].addr;
135 res->bar4 = pci_dev->mem_resource[4].addr;
136 res->domain = (val >> 7) & 0xffff;
141 timvf_log_dbg("Domain=%d VFid=%d bar0 %p total_timvfs=%d", res->domain,
142 res->vfid, pci_dev->mem_resource[0].addr,
148 static const struct rte_pci_id pci_timvf_map[] = {
150 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
151 PCI_DEVICE_ID_OCTEONTX_TIM_VF)
158 static struct rte_pci_driver pci_timvf = {
159 .id_table = pci_timvf_map,
160 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_NEED_IOVA_AS_VA,
161 .probe = timvf_probe,
165 RTE_PMD_REGISTER_PCI(octeontx_timvf, pci_timvf);