1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2014 Intel Corporation
6 #ifdef RTE_EXEC_ENV_LINUX
14 #include "virtio_pci.h"
15 #include "virtio_logs.h"
16 #include "virtqueue.h"
19 * Following macros are derived from linux/pci_regs.h, however,
20 * we can't simply include that header here, as there is no such
21 * file for non-Linux platform.
23 #define PCI_CAPABILITY_LIST 0x34
24 #define PCI_CAP_ID_VNDR 0x09
25 #define PCI_CAP_ID_MSIX 0x11
28 * The remaining space is defined by each driver as the per-driver
29 * configuration space.
31 #define VIRTIO_PCI_CONFIG(hw) \
32 (((hw)->use_msix == VIRTIO_MSIX_ENABLED) ? 24 : 20)
35 check_vq_phys_addr_ok(struct virtqueue *vq)
37 /* Virtio PCI device VIRTIO_PCI_QUEUE_PF register is 32bit,
38 * and only accepts 32 bit page frame number.
39 * Check if the allocated physical memory exceeds 16TB.
41 if ((vq->vq_ring_mem + vq->vq_ring_size - 1) >>
42 (VIRTIO_PCI_QUEUE_ADDR_SHIFT + 32)) {
43 PMD_INIT_LOG(ERR, "vring address shouldn't be above 16TB!");
51 * Since we are in legacy mode:
52 * http://ozlabs.org/~rusty/virtio-spec/virtio-0.9.5.pdf
54 * "Note that this is possible because while the virtio header is PCI (i.e.
55 * little) endian, the device-specific region is encoded in the native endian of
56 * the guest (where such distinction is applicable)."
58 * For powerpc which supports both, qemu supposes that cpu is big endian and
59 * enforces this for the virtio-net stuff.
62 legacy_read_dev_config(struct virtio_hw *hw, size_t offset,
63 void *dst, int length)
65 #ifdef RTE_ARCH_PPC_64
71 rte_pci_ioport_read(VTPCI_IO(hw), dst, size,
72 VIRTIO_PCI_CONFIG(hw) + offset);
73 *(uint32_t *)dst = rte_be_to_cpu_32(*(uint32_t *)dst);
74 } else if (length >= 2) {
76 rte_pci_ioport_read(VTPCI_IO(hw), dst, size,
77 VIRTIO_PCI_CONFIG(hw) + offset);
78 *(uint16_t *)dst = rte_be_to_cpu_16(*(uint16_t *)dst);
81 rte_pci_ioport_read(VTPCI_IO(hw), dst, size,
82 VIRTIO_PCI_CONFIG(hw) + offset);
85 dst = (char *)dst + size;
90 rte_pci_ioport_read(VTPCI_IO(hw), dst, length,
91 VIRTIO_PCI_CONFIG(hw) + offset);
96 legacy_write_dev_config(struct virtio_hw *hw, size_t offset,
97 const void *src, int length)
99 #ifdef RTE_ARCH_PPC_64
109 tmp.u32 = rte_cpu_to_be_32(*(const uint32_t *)src);
110 rte_pci_ioport_write(VTPCI_IO(hw), &tmp.u32, size,
111 VIRTIO_PCI_CONFIG(hw) + offset);
112 } else if (length >= 2) {
114 tmp.u16 = rte_cpu_to_be_16(*(const uint16_t *)src);
115 rte_pci_ioport_write(VTPCI_IO(hw), &tmp.u16, size,
116 VIRTIO_PCI_CONFIG(hw) + offset);
119 rte_pci_ioport_write(VTPCI_IO(hw), src, size,
120 VIRTIO_PCI_CONFIG(hw) + offset);
123 src = (const char *)src + size;
128 rte_pci_ioport_write(VTPCI_IO(hw), src, length,
129 VIRTIO_PCI_CONFIG(hw) + offset);
134 legacy_get_features(struct virtio_hw *hw)
138 rte_pci_ioport_read(VTPCI_IO(hw), &dst, 4, VIRTIO_PCI_HOST_FEATURES);
143 legacy_set_features(struct virtio_hw *hw, uint64_t features)
145 if ((features >> 32) != 0) {
147 "only 32 bit features are allowed for legacy virtio!");
150 rte_pci_ioport_write(VTPCI_IO(hw), &features, 4,
151 VIRTIO_PCI_GUEST_FEATURES);
155 legacy_get_status(struct virtio_hw *hw)
159 rte_pci_ioport_read(VTPCI_IO(hw), &dst, 1, VIRTIO_PCI_STATUS);
164 legacy_set_status(struct virtio_hw *hw, uint8_t status)
166 rte_pci_ioport_write(VTPCI_IO(hw), &status, 1, VIRTIO_PCI_STATUS);
170 legacy_get_isr(struct virtio_hw *hw)
174 rte_pci_ioport_read(VTPCI_IO(hw), &dst, 1, VIRTIO_PCI_ISR);
178 /* Enable one vector (0) for Link State Intrerrupt */
180 legacy_set_config_irq(struct virtio_hw *hw, uint16_t vec)
184 rte_pci_ioport_write(VTPCI_IO(hw), &vec, 2, VIRTIO_MSI_CONFIG_VECTOR);
185 rte_pci_ioport_read(VTPCI_IO(hw), &dst, 2, VIRTIO_MSI_CONFIG_VECTOR);
190 legacy_set_queue_irq(struct virtio_hw *hw, struct virtqueue *vq, uint16_t vec)
194 rte_pci_ioport_write(VTPCI_IO(hw), &vq->vq_queue_index, 2,
195 VIRTIO_PCI_QUEUE_SEL);
196 rte_pci_ioport_write(VTPCI_IO(hw), &vec, 2, VIRTIO_MSI_QUEUE_VECTOR);
197 rte_pci_ioport_read(VTPCI_IO(hw), &dst, 2, VIRTIO_MSI_QUEUE_VECTOR);
202 legacy_get_queue_num(struct virtio_hw *hw, uint16_t queue_id)
206 rte_pci_ioport_write(VTPCI_IO(hw), &queue_id, 2, VIRTIO_PCI_QUEUE_SEL);
207 rte_pci_ioport_read(VTPCI_IO(hw), &dst, 2, VIRTIO_PCI_QUEUE_NUM);
212 legacy_setup_queue(struct virtio_hw *hw, struct virtqueue *vq)
216 if (!check_vq_phys_addr_ok(vq))
219 rte_pci_ioport_write(VTPCI_IO(hw), &vq->vq_queue_index, 2,
220 VIRTIO_PCI_QUEUE_SEL);
221 src = vq->vq_ring_mem >> VIRTIO_PCI_QUEUE_ADDR_SHIFT;
222 rte_pci_ioport_write(VTPCI_IO(hw), &src, 4, VIRTIO_PCI_QUEUE_PFN);
228 legacy_del_queue(struct virtio_hw *hw, struct virtqueue *vq)
232 rte_pci_ioport_write(VTPCI_IO(hw), &vq->vq_queue_index, 2,
233 VIRTIO_PCI_QUEUE_SEL);
234 rte_pci_ioport_write(VTPCI_IO(hw), &src, 4, VIRTIO_PCI_QUEUE_PFN);
238 legacy_notify_queue(struct virtio_hw *hw, struct virtqueue *vq)
240 rte_pci_ioport_write(VTPCI_IO(hw), &vq->vq_queue_index, 2,
241 VIRTIO_PCI_QUEUE_NOTIFY);
244 const struct virtio_pci_ops legacy_ops = {
245 .read_dev_cfg = legacy_read_dev_config,
246 .write_dev_cfg = legacy_write_dev_config,
247 .get_status = legacy_get_status,
248 .set_status = legacy_set_status,
249 .get_features = legacy_get_features,
250 .set_features = legacy_set_features,
251 .get_isr = legacy_get_isr,
252 .set_config_irq = legacy_set_config_irq,
253 .set_queue_irq = legacy_set_queue_irq,
254 .get_queue_num = legacy_get_queue_num,
255 .setup_queue = legacy_setup_queue,
256 .del_queue = legacy_del_queue,
257 .notify_queue = legacy_notify_queue,
261 io_write64_twopart(uint64_t val, uint32_t *lo, uint32_t *hi)
263 rte_write32(val & ((1ULL << 32) - 1), lo);
264 rte_write32(val >> 32, hi);
268 modern_read_dev_config(struct virtio_hw *hw, size_t offset,
269 void *dst, int length)
273 uint8_t old_gen, new_gen;
276 old_gen = rte_read8(&hw->common_cfg->config_generation);
279 for (i = 0; i < length; i++)
280 *p++ = rte_read8((uint8_t *)hw->dev_cfg + offset + i);
282 new_gen = rte_read8(&hw->common_cfg->config_generation);
283 } while (old_gen != new_gen);
287 modern_write_dev_config(struct virtio_hw *hw, size_t offset,
288 const void *src, int length)
291 const uint8_t *p = src;
293 for (i = 0; i < length; i++)
294 rte_write8((*p++), (((uint8_t *)hw->dev_cfg) + offset + i));
298 modern_get_features(struct virtio_hw *hw)
300 uint32_t features_lo, features_hi;
302 rte_write32(0, &hw->common_cfg->device_feature_select);
303 features_lo = rte_read32(&hw->common_cfg->device_feature);
305 rte_write32(1, &hw->common_cfg->device_feature_select);
306 features_hi = rte_read32(&hw->common_cfg->device_feature);
308 return ((uint64_t)features_hi << 32) | features_lo;
312 modern_set_features(struct virtio_hw *hw, uint64_t features)
314 rte_write32(0, &hw->common_cfg->guest_feature_select);
315 rte_write32(features & ((1ULL << 32) - 1),
316 &hw->common_cfg->guest_feature);
318 rte_write32(1, &hw->common_cfg->guest_feature_select);
319 rte_write32(features >> 32,
320 &hw->common_cfg->guest_feature);
324 modern_get_status(struct virtio_hw *hw)
326 return rte_read8(&hw->common_cfg->device_status);
330 modern_set_status(struct virtio_hw *hw, uint8_t status)
332 rte_write8(status, &hw->common_cfg->device_status);
336 modern_get_isr(struct virtio_hw *hw)
338 return rte_read8(hw->isr);
342 modern_set_config_irq(struct virtio_hw *hw, uint16_t vec)
344 rte_write16(vec, &hw->common_cfg->msix_config);
345 return rte_read16(&hw->common_cfg->msix_config);
349 modern_set_queue_irq(struct virtio_hw *hw, struct virtqueue *vq, uint16_t vec)
351 rte_write16(vq->vq_queue_index, &hw->common_cfg->queue_select);
352 rte_write16(vec, &hw->common_cfg->queue_msix_vector);
353 return rte_read16(&hw->common_cfg->queue_msix_vector);
357 modern_get_queue_num(struct virtio_hw *hw, uint16_t queue_id)
359 rte_write16(queue_id, &hw->common_cfg->queue_select);
360 return rte_read16(&hw->common_cfg->queue_size);
364 modern_setup_queue(struct virtio_hw *hw, struct virtqueue *vq)
366 uint64_t desc_addr, avail_addr, used_addr;
369 if (!check_vq_phys_addr_ok(vq))
372 desc_addr = vq->vq_ring_mem;
373 avail_addr = desc_addr + vq->vq_nentries * sizeof(struct vring_desc);
374 used_addr = RTE_ALIGN_CEIL(avail_addr + offsetof(struct vring_avail,
375 ring[vq->vq_nentries]),
376 VIRTIO_PCI_VRING_ALIGN);
378 rte_write16(vq->vq_queue_index, &hw->common_cfg->queue_select);
380 io_write64_twopart(desc_addr, &hw->common_cfg->queue_desc_lo,
381 &hw->common_cfg->queue_desc_hi);
382 io_write64_twopart(avail_addr, &hw->common_cfg->queue_avail_lo,
383 &hw->common_cfg->queue_avail_hi);
384 io_write64_twopart(used_addr, &hw->common_cfg->queue_used_lo,
385 &hw->common_cfg->queue_used_hi);
387 notify_off = rte_read16(&hw->common_cfg->queue_notify_off);
388 vq->notify_addr = (void *)((uint8_t *)hw->notify_base +
389 notify_off * hw->notify_off_multiplier);
391 rte_write16(1, &hw->common_cfg->queue_enable);
393 PMD_INIT_LOG(DEBUG, "queue %u addresses:", vq->vq_queue_index);
394 PMD_INIT_LOG(DEBUG, "\t desc_addr: %" PRIx64, desc_addr);
395 PMD_INIT_LOG(DEBUG, "\t aval_addr: %" PRIx64, avail_addr);
396 PMD_INIT_LOG(DEBUG, "\t used_addr: %" PRIx64, used_addr);
397 PMD_INIT_LOG(DEBUG, "\t notify addr: %p (notify offset: %u)",
398 vq->notify_addr, notify_off);
404 modern_del_queue(struct virtio_hw *hw, struct virtqueue *vq)
406 rte_write16(vq->vq_queue_index, &hw->common_cfg->queue_select);
408 io_write64_twopart(0, &hw->common_cfg->queue_desc_lo,
409 &hw->common_cfg->queue_desc_hi);
410 io_write64_twopart(0, &hw->common_cfg->queue_avail_lo,
411 &hw->common_cfg->queue_avail_hi);
412 io_write64_twopart(0, &hw->common_cfg->queue_used_lo,
413 &hw->common_cfg->queue_used_hi);
415 rte_write16(0, &hw->common_cfg->queue_enable);
419 modern_notify_queue(struct virtio_hw *hw __rte_unused, struct virtqueue *vq)
421 rte_write16(vq->vq_queue_index, vq->notify_addr);
424 const struct virtio_pci_ops modern_ops = {
425 .read_dev_cfg = modern_read_dev_config,
426 .write_dev_cfg = modern_write_dev_config,
427 .get_status = modern_get_status,
428 .set_status = modern_set_status,
429 .get_features = modern_get_features,
430 .set_features = modern_set_features,
431 .get_isr = modern_get_isr,
432 .set_config_irq = modern_set_config_irq,
433 .set_queue_irq = modern_set_queue_irq,
434 .get_queue_num = modern_get_queue_num,
435 .setup_queue = modern_setup_queue,
436 .del_queue = modern_del_queue,
437 .notify_queue = modern_notify_queue,
442 vtpci_read_dev_config(struct virtio_hw *hw, size_t offset,
443 void *dst, int length)
445 VTPCI_OPS(hw)->read_dev_cfg(hw, offset, dst, length);
449 vtpci_write_dev_config(struct virtio_hw *hw, size_t offset,
450 const void *src, int length)
452 VTPCI_OPS(hw)->write_dev_cfg(hw, offset, src, length);
456 vtpci_negotiate_features(struct virtio_hw *hw, uint64_t host_features)
461 * Limit negotiated features to what the driver, virtqueue, and
464 features = host_features & hw->guest_features;
465 VTPCI_OPS(hw)->set_features(hw, features);
471 vtpci_reset(struct virtio_hw *hw)
473 VTPCI_OPS(hw)->set_status(hw, VIRTIO_CONFIG_STATUS_RESET);
474 /* flush status write */
475 VTPCI_OPS(hw)->get_status(hw);
479 vtpci_reinit_complete(struct virtio_hw *hw)
481 vtpci_set_status(hw, VIRTIO_CONFIG_STATUS_DRIVER_OK);
485 vtpci_set_status(struct virtio_hw *hw, uint8_t status)
487 if (status != VIRTIO_CONFIG_STATUS_RESET)
488 status |= VTPCI_OPS(hw)->get_status(hw);
490 VTPCI_OPS(hw)->set_status(hw, status);
494 vtpci_get_status(struct virtio_hw *hw)
496 return VTPCI_OPS(hw)->get_status(hw);
500 vtpci_isr(struct virtio_hw *hw)
502 return VTPCI_OPS(hw)->get_isr(hw);
506 get_cfg_addr(struct rte_pci_device *dev, struct virtio_pci_cap *cap)
508 uint8_t bar = cap->bar;
509 uint32_t length = cap->length;
510 uint32_t offset = cap->offset;
513 if (bar >= PCI_MAX_RESOURCE) {
514 PMD_INIT_LOG(ERR, "invalid bar: %u", bar);
518 if (offset + length < offset) {
519 PMD_INIT_LOG(ERR, "offset(%u) + length(%u) overflows",
524 if (offset + length > dev->mem_resource[bar].len) {
526 "invalid cap: overflows bar space: %u > %" PRIu64,
527 offset + length, dev->mem_resource[bar].len);
531 base = dev->mem_resource[bar].addr;
533 PMD_INIT_LOG(ERR, "bar %u base addr is NULL", bar);
537 return base + offset;
540 #define PCI_MSIX_ENABLE 0x8000
543 virtio_read_caps(struct rte_pci_device *dev, struct virtio_hw *hw)
546 struct virtio_pci_cap cap;
549 if (rte_pci_map_device(dev)) {
550 PMD_INIT_LOG(DEBUG, "failed to map pci device!");
554 ret = rte_pci_read_config(dev, &pos, 1, PCI_CAPABILITY_LIST);
557 "failed to read pci capability list, ret %d", ret);
562 ret = rte_pci_read_config(dev, &cap, 2, pos);
565 "failed to read pci cap at pos: %x ret %d",
570 if (cap.cap_vndr == PCI_CAP_ID_MSIX) {
571 /* Transitional devices would also have this capability,
572 * that's why we also check if msix is enabled.
573 * 1st byte is cap ID; 2nd byte is the position of next
574 * cap; next two bytes are the flags.
578 ret = rte_pci_read_config(dev, &flags, sizeof(flags),
580 if (ret != sizeof(flags)) {
582 "failed to read pci cap at pos:"
583 " %x ret %d", pos + 2, ret);
587 if (flags & PCI_MSIX_ENABLE)
588 hw->use_msix = VIRTIO_MSIX_ENABLED;
590 hw->use_msix = VIRTIO_MSIX_DISABLED;
593 if (cap.cap_vndr != PCI_CAP_ID_VNDR) {
595 "[%2x] skipping non VNDR cap id: %02x",
600 ret = rte_pci_read_config(dev, &cap, sizeof(cap), pos);
601 if (ret != sizeof(cap)) {
603 "failed to read pci cap at pos: %x ret %d",
609 "[%2x] cfg type: %u, bar: %u, offset: %04x, len: %u",
610 pos, cap.cfg_type, cap.bar, cap.offset, cap.length);
612 switch (cap.cfg_type) {
613 case VIRTIO_PCI_CAP_COMMON_CFG:
614 hw->common_cfg = get_cfg_addr(dev, &cap);
616 case VIRTIO_PCI_CAP_NOTIFY_CFG:
617 ret = rte_pci_read_config(dev,
618 &hw->notify_off_multiplier,
619 4, pos + sizeof(cap));
622 "failed to read notify_off_multiplier, ret %d",
625 hw->notify_base = get_cfg_addr(dev, &cap);
627 case VIRTIO_PCI_CAP_DEVICE_CFG:
628 hw->dev_cfg = get_cfg_addr(dev, &cap);
630 case VIRTIO_PCI_CAP_ISR_CFG:
631 hw->isr = get_cfg_addr(dev, &cap);
639 if (hw->common_cfg == NULL || hw->notify_base == NULL ||
640 hw->dev_cfg == NULL || hw->isr == NULL) {
641 PMD_INIT_LOG(INFO, "no modern virtio pci device found.");
645 PMD_INIT_LOG(INFO, "found modern virtio pci device.");
647 PMD_INIT_LOG(DEBUG, "common cfg mapped at: %p", hw->common_cfg);
648 PMD_INIT_LOG(DEBUG, "device cfg mapped at: %p", hw->dev_cfg);
649 PMD_INIT_LOG(DEBUG, "isr cfg mapped at: %p", hw->isr);
650 PMD_INIT_LOG(DEBUG, "notify base: %p, notify off multiplier: %u",
651 hw->notify_base, hw->notify_off_multiplier);
658 * if there is error mapping with VFIO/UIO.
659 * if port map error when driver type is KDRV_NONE.
660 * if whitelisted but driver type is KDRV_UNKNOWN.
661 * Return 1 if kernel driver is managing the device.
662 * Return 0 on success.
665 vtpci_init(struct rte_pci_device *dev, struct virtio_hw *hw)
668 * Try if we can succeed reading virtio pci caps, which exists
669 * only on modern pci device. If failed, we fallback to legacy
672 if (virtio_read_caps(dev, hw) == 0) {
673 PMD_INIT_LOG(INFO, "modern virtio pci detected.");
674 virtio_hw_internal[hw->port_id].vtpci_ops = &modern_ops;
679 PMD_INIT_LOG(INFO, "trying with legacy virtio pci.");
680 if (rte_pci_ioport_map(dev, 0, VTPCI_IO(hw)) < 0) {
681 if (dev->kdrv == RTE_KDRV_UNKNOWN &&
682 (!dev->device.devargs ||
683 dev->device.devargs->bus !=
684 rte_bus_find_by_name("pci"))) {
686 "skip kernel managed virtio device.");
692 virtio_hw_internal[hw->port_id].vtpci_ops = &legacy_ops;
698 enum virtio_msix_status
699 vtpci_msix_detect(struct rte_pci_device *dev)
704 ret = rte_pci_read_config(dev, &pos, 1, PCI_CAPABILITY_LIST);
707 "failed to read pci capability list, ret %d", ret);
708 return VIRTIO_MSIX_NONE;
714 ret = rte_pci_read_config(dev, cap, sizeof(cap), pos);
715 if (ret != sizeof(cap)) {
717 "failed to read pci cap at pos: %x ret %d",
722 if (cap[0] == PCI_CAP_ID_MSIX) {
725 ret = rte_pci_read_config(dev, &flags, sizeof(flags),
727 if (ret != sizeof(flags)) {
729 "failed to read pci cap at pos:"
730 " %x ret %d", pos + 2, ret);
734 if (flags & PCI_MSIX_ENABLE)
735 return VIRTIO_MSIX_ENABLED;
737 return VIRTIO_MSIX_DISABLED;
743 return VIRTIO_MSIX_NONE;