Installation
------------
-Section 3 of the DPDK manual provides instuctions on installing and compiling DPDK. The
-default set of bbdev compile flags may be found in config/common_base, where for example
-the flag to build the FPGA 5GNR FEC device, ``CONFIG_RTE_LIBRTE_PMD_BBDEV_FPGA_5GNR_FEC``,
-is already set. It is assumed DPDK has been compiled using for instance:
-
-.. code-block:: console
-
- make install T=x86_64-native-linuxapp-gcc
-
+Section 3 of the DPDK manual provides instructions on installing and compiling DPDK.
DPDK requires hugepages to be configured as detailed in section 2 of the DPDK manual.
The bbdev test application has been tested with a configuration 40 x 1GB hugepages. The
Install the DPDK igb_uio driver, bind it with the PF PCI device ID and use
``lspci`` to confirm the PF device is under use by ``igb_uio`` DPDK UIO driver.
-The igb_uio driver may be bound to the PF PCI device using one of three methods:
+The igb_uio driver may be bound to the PF PCI device using one of two methods:
1. PCI functions (physical or virtual, depending on the use case) can be bound to
.. code-block:: console
- cd <dpdk-top-level-directory>
- insmod ./build/kmod/igb_uio.ko
+ insmod igb_uio.ko
echo "8086 0d8f" > /sys/bus/pci/drivers/igb_uio/new_id
lspci -vd8086:0d8f
where the PCI device ID (example: 0000:06:00.0) is obtained using lspci -vd8086:0d8f
-3. A third way to bind is to use ``dpdk-setup.sh`` tool
-
-.. code-block:: console
-
- cd <dpdk-top-level-directory>
- ./usertools/dpdk-setup.sh
-
- select 'Bind Ethernet/Crypto/Baseband device to IGB UIO module'
- or
- select 'Bind Ethernet/Crypto/Baseband device to VFIO module' depending on driver required
- enter PCI device ID
- select 'Display current Ethernet/Crypto/Baseband device settings' to confirm binding
-
-
In the same way the FPGA 5GNR FEC PF can be bound with vfio, but vfio driver does not
support SR-IOV configuration right out of the box, so it will need to be patched.
echo <num-of-vfs> > /sys/bus/pci/devices/0000\:<b>\:<d>.<f>/sriov_numvfs
+Configure the VFs through PF
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+The PCI virtual functions must be configured before working or getting assigned
+to VMs/Containers. The configuration involves allocating the number of hardware
+queues, priorities, load balance, bandwidth and other settings necessary for the
+device to perform FEC functions.
+
+This configuration needs to be executed at least once after reboot or PCI FLR and can
+be achieved by using the function ``rte_fpga_5gnr_fec_configure()``, which sets up the
+parameters defined in ``rte_fpga_5gnr_fec_conf`` structure:
+
+.. code-block:: c
+
+ struct rte_fpga_5gnr_fec_conf {
+ bool pf_mode_en;
+ uint8_t vf_ul_queues_number[FPGA_5GNR_FEC_NUM_VFS];
+ uint8_t vf_dl_queues_number[FPGA_5GNR_FEC_NUM_VFS];
+ uint8_t ul_bandwidth;
+ uint8_t dl_bandwidth;
+ uint8_t ul_load_balance;
+ uint8_t dl_load_balance;
+ uint16_t flr_time_out;
+ };
+
+- ``pf_mode_en``: identifies whether only PF is to be used, or the VFs. PF and
+ VFs are mutually exclusive and cannot run simultaneously.
+ Set to 1 for PF mode enabled.
+ If PF mode is enabled all queues available in the device are assigned
+ exclusively to PF and 0 queues given to VFs.
+
+- ``vf_*l_queues_number``: defines the hardware queue mapping for every VF.
+
+- ``*l_bandwidth``: in case of congestion on PCIe interface. The device
+ allocates different bandwidth to UL and DL. The weight is configured by this
+ setting. The unit of weight is 3 code blocks. For example, if the code block
+ cbps (code block per second) ratio between UL and DL is 12:1, then the
+ configuration value should be set to 36:3. The schedule algorithm is based
+ on code block regardless the length of each block.
+
+- ``*l_load_balance``: hardware queues are load-balanced in a round-robin
+ fashion. Queues get filled first-in first-out until they reach a pre-defined
+ watermark level, if exceeded, they won't get assigned new code blocks..
+ This watermark is defined by this setting.
+
+ If all hardware queues exceeds the watermark, no code blocks will be
+ streamed in from UL/DL code block FIFO.
+
+- ``flr_time_out``: specifies how many 16.384us to be FLR time out. The
+ time_out = flr_time_out x 16.384us. For instance, if you want to set 10ms for
+ the FLR time out then set this setting to 0x262=610.
+
+
+An example configuration code calling the function ``rte_fpga_5gnr_fec_configure()`` is shown
+below:
+
+.. code-block:: c
+
+ struct rte_fpga_5gnr_fec_conf conf;
+ unsigned int i;
+
+ memset(&conf, 0, sizeof(struct rte_fpga_5gnr_fec_conf));
+ conf.pf_mode_en = 1;
+
+ for (i = 0; i < FPGA_5GNR_FEC_NUM_VFS; ++i) {
+ conf.vf_ul_queues_number[i] = 4;
+ conf.vf_dl_queues_number[i] = 4;
+ }
+ conf.ul_bandwidth = 12;
+ conf.dl_bandwidth = 5;
+ conf.dl_load_balance = 64;
+ conf.ul_load_balance = 64;
+
+ /* setup FPGA PF */
+ ret = rte_fpga_5gnr_fec_configure(info->dev_name, &conf);
+ TEST_ASSERT_SUCCESS(ret,
+ "Failed to configure 4G FPGA PF for bbdev %s",
+ info->dev_name);
+
+
+Test Application
+----------------
+
+BBDEV provides a test application, ``test-bbdev.py`` and range of test data for testing
+the functionality of FPGA 5GNR FEC encode and decode, depending on the device's
+capabilities. The test application is located under app->test-bbdev folder and has the
+following options:
+
+.. code-block:: console
+
+ "-p", "--testapp-path": specifies path to the bbdev test app.
+ "-e", "--eal-params" : EAL arguments which are passed to the test app.
+ "-t", "--timeout" : Timeout in seconds (default=300).
+ "-c", "--test-cases" : Defines test cases to run. Run all if not specified.
+ "-v", "--test-vector" : Test vector path (default=dpdk_path+/app/test-bbdev/test_vectors/bbdev_null.data).
+ "-n", "--num-ops" : Number of operations to process on device (default=32).
+ "-b", "--burst-size" : Operations enqueue/dequeue burst size (default=32).
+ "-l", "--num-lcores" : Number of lcores to run (default=16).
+ "-i", "--init-device" : Initialise PF device with default values.
+
+
+To execute the test application tool using simple decode or encode data,
+type one of the following:
+
+.. code-block:: console
+
+ ./test-bbdev.py -c validation -n 64 -b 1 -v ./ldpc_dec_default.data
+ ./test-bbdev.py -c validation -n 64 -b 1 -v ./ldpc_enc_default.data
+
+
+The test application ``test-bbdev.py``, supports the ability to configure the PF device with
+a default set of values, if the "-i" or "- -init-device" option is included. The default values
+are defined in test_bbdev_perf.c as:
+
+- VF_UL_QUEUE_VALUE 4
+- VF_DL_QUEUE_VALUE 4
+- UL_BANDWIDTH 3
+- DL_BANDWIDTH 3
+- UL_LOAD_BALANCE 128
+- DL_LOAD_BALANCE 128
+- FLR_TIMEOUT 610
+
+
Test Vectors
~~~~~~~~~~~~
In addition to the simple LDPC decoder and LDPC encoder tests, bbdev also provides
a range of additional tests under the test_vectors folder, which may be useful. The results
of these tests will depend on the FPGA 5GNR FEC capabilities.
+
+
+Alternate Baseband Device configuration tool
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+On top of the embedded configuration feature supported in test-bbdev using "- -init-device"
+option, there is also a tool available to perform that device configuration using a companion
+application.
+The ``pf_bb_config`` application notably enables then to run bbdev-test from the VF
+and not only limited to the PF as captured above.
+
+See for more details: https://github.com/intel/pf-bb-config
+
+Specifically for the BBDEV FPGA 5GNR FEC PMD, the command below can be used:
+
+.. code-block:: console
+
+ ./pf_bb_config FPGA_5GNR -c fpga_5gnr/fpga_5gnr_config_vf.cfg
+ ./test-bbdev.py -e="-c 0xff0 -a${VF_PCI_ADDR}" -c validation -n 64 -b 32 -l 1 -v ./ldpc_dec_default.data