#include <rte_log.h>
#include <rte_kvargs.h>
#include <rte_devargs.h>
+#include <rte_bitops.h>
#include "mlx5_prm.h"
#include "mlx5_devx_cmds.h"
PCI_DEVICE_ID_MELLANOX_CONNECTX6DX = 0x101d,
PCI_DEVICE_ID_MELLANOX_CONNECTX6DXVF = 0x101e,
PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF = 0xa2d6,
+ PCI_DEVICE_ID_MELLANOX_CONNECTX6LX = 0x101f,
};
/* Maximum number of simultaneous unicast MAC addresses. */
if (unlikely((op_owner != (!!(idx))) || (op_code == MLX5_CQE_INVALID)))
return MLX5_CQE_STATUS_HW_OWN;
- rte_cio_rmb();
+ rte_io_rmb();
if (unlikely(op_code == MLX5_CQE_RESP_ERR ||
op_code == MLX5_CQE_REQ_ERR))
return MLX5_CQE_STATUS_ERR;
#define MLX5_CLASS_ARG_NAME "class"
enum mlx5_class {
- MLX5_CLASS_NET,
- MLX5_CLASS_VDPA,
MLX5_CLASS_INVALID,
+ MLX5_CLASS_NET = RTE_BIT64(0),
+ MLX5_CLASS_VDPA = RTE_BIT64(1),
+ MLX5_CLASS_REGEX = RTE_BIT64(2),
};
-#define MLX5_DBR_PAGE_SIZE 4096 /* Must be >= 512. */
-#define MLX5_DBR_SIZE 8
-#define MLX5_DBR_PER_PAGE (MLX5_DBR_PAGE_SIZE / MLX5_DBR_SIZE)
-#define MLX5_DBR_BITMAP_SIZE (MLX5_DBR_PER_PAGE / 64)
+#define MLX5_DBR_SIZE RTE_CACHE_LINE_SIZE
+#define MLX5_DBR_PER_PAGE 64
+/* Must be >= CHAR_BIT * sizeof(uint64_t) */
+#define MLX5_DBR_PAGE_SIZE (MLX5_DBR_PER_PAGE * MLX5_DBR_SIZE)
+/* Page size must be >= 512. */
+#define MLX5_DBR_BITMAP_SIZE (MLX5_DBR_PER_PAGE / (CHAR_BIT * sizeof(uint64_t)))
struct mlx5_devx_dbr_page {
/* Door-bell records, must be first member in structure. */
LIST_HEAD(mlx5_dbr_page_list, mlx5_devx_dbr_page);
-__rte_internal
-enum mlx5_class mlx5_class_get(struct rte_devargs *devargs);
__rte_internal
void mlx5_translate_port_name(const char *port_name_in,
struct mlx5_switch_info *port_info_out);
uint64_t offset);
extern uint8_t haswell_broadwell_cpu;
+__rte_internal
+void mlx5_common_init(void);
+
#endif /* RTE_PMD_MLX5_COMMON_H_ */