uint32_t lro_timer_supported_periods[MLX5_LRO_NUM_SUPP_PERIODS];
uint16_t lro_min_mss_size;
uint32_t flex_parser_protocols;
+ uint32_t max_geneve_tlv_options;
+ uint32_t max_geneve_tlv_option_data_len;
uint32_t hairpin:1;
uint32_t log_max_hairpin_queues:5;
uint32_t log_max_hairpin_wq_data_sz:5;
uint32_t scatter_fcs_w_decap_disable:1;
uint32_t flow_hit_aso:1; /* General obj type FLOW_HIT_ASO supported. */
uint32_t regex:1;
+ uint32_t reg_c_preserve:1;
uint32_t regexp_num_of_engines;
uint32_t log_max_ft_sampler_num:8;
+ uint32_t geneve_tlv_opt;
struct mlx5_hca_qos_attr qos;
struct mlx5_hca_vdpa_attr vdpa;
int log_max_qp_sz;
uint32_t log_max_srq;
uint32_t log_max_srq_sz;
uint32_t rss_ind_tbl_cap;
+ uint32_t mmo_dma_en:1;
+ uint32_t mmo_compress_en:1;
+ uint32_t mmo_decompress_en:1;
+ uint32_t compress_min_block_size:4;
+ uint32_t log_max_mmo_dma:5;
+ uint32_t log_max_mmo_compress:5;
+ uint32_t log_max_mmo_decompress:5;
};
struct mlx5_devx_wq_attr {
uint32_t cqe_comp_en:1;
uint32_t mini_cqe_res_format:2;
uint32_t mini_cqe_res_format_ext:2;
- uint32_t cqe_size:3;
uint32_t log_cq_size:5;
uint32_t log_page_size:5;
uint32_t uar_page_id;
uint32_t rx_csum:1;
uint32_t event_mode:3;
uint32_t state:4;
+ uint32_t hw_latency_mode:2;
+ uint32_t hw_max_latency_us:12;
+ uint32_t hw_max_pending_comp:16;
uint32_t dirty_bitmap_dump_enable:1;
uint32_t dirty_bitmap_mkey;
uint32_t dirty_bitmap_size;
__rte_internal
int mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id,
uint32_t arg, uint32_t *data, uint32_t dw_cnt);
+
+__rte_internal
+struct mlx5_devx_obj *
+mlx5_devx_cmd_create_geneve_tlv_option(void *ctx,
+ uint16_t class, uint8_t type, uint8_t len);
+
/**
* Create virtio queue counters object DevX API.
*