uint32_t misc;
} __rte_packed __rte_aligned(MLX5_WSEG_SIZE);
+/*
+ * WQE CSEG opcode field size is 32 bits, divided:
+ * Bits 31:24 OPC_MOD
+ * Bits 23:8 wqe_index
+ * Bits 7:0 OPCODE
+ */
+#define WQE_CSEG_OPC_MOD_OFFSET 24
+#define WQE_CSEG_WQE_INDEX_OFFSET 8
+
/* Header of data segment. Minimal size Data Segment */
struct mlx5_wqe_dseg {
uint32_t bcount;
struct mlx5_ifc_flow_hit_aso_bits flow_hit_aso;
};
-enum mlx5_access_aso_op_mod {
- ASO_OP_MOD_IPSEC = 0x0,
- ASO_OP_MOD_CONNECTION_TRACKING = 0x1,
- ASO_OP_MOD_POLICER = 0x2,
- ASO_OP_MOD_RACE_AVOIDANCE = 0x3,
- ASO_OP_MOD_FLOW_HIT = 0x4,
+enum mlx5_access_aso_opc_mod {
+ ASO_OPC_MOD_IPSEC = 0x0,
+ ASO_OPC_MOD_CONNECTION_TRACKING = 0x1,
+ ASO_OPC_MOD_POLICER = 0x2,
+ ASO_OPC_MOD_RACE_AVOIDANCE = 0x3,
+ ASO_OPC_MOD_FLOW_HIT = 0x4,
};
+#define ASO_CSEG_DATA_MASK_MODE_OFFSET 30
+
enum mlx5_aso_data_mask_mode {
BITWISE_64BIT = 0x0,
BYTEWISE_64BYTE = 0x1,
CALCULATED_64BYTE = 0x2,
};
+#define ASO_CSEG_COND_0_OPER_OFFSET 20
+#define ASO_CSEG_COND_1_OPER_OFFSET 16
+
enum mlx5_aso_pre_cond_op {
ASO_OP_ALWAYS_FALSE = 0x0,
ASO_OP_ALWAYS_TRUE = 0x1,
ASO_OP_CYCLIC_LESSER = 0x9,
};
+#define ASO_CSEG_COND_OPER_OFFSET 6
+
enum mlx5_aso_op {
ASO_OPER_LOGICAL_AND = 0x0,
ASO_OPER_LOGICAL_OR = 0x1,
/* ASO WQE CTRL segment. */
struct mlx5_aso_cseg {
uint32_t va_h;
- uint32_t va_l_ro;
+ uint32_t va_l_r;
uint32_t lkey;
uint32_t operand_masks;
uint32_t condition_0_data;