#include <rte_eventdev.h>
#include <rte_eventdev_pmd.h>
#include <rte_event_eth_rx_adapter.h>
+#include <rte_event_eth_tx_adapter.h>
#include "otx2_common.h"
#include "otx2_dev.h"
#include "otx2_ethdev.h"
#include "otx2_mempool.h"
+#include "otx2_tim_evdev.h"
-#define EVENTDEV_NAME_OCTEONTX2_PMD otx2_eventdev
+#define EVENTDEV_NAME_OCTEONTX2_PMD event_octeontx2
#define sso_func_trace otx2_sso_dbg
#define OTX2_SSO_MAX_VHGRP RTE_EVENT_MAX_QUEUES_PER_DEV
#define OTX2_SSO_MAX_VHWS (UINT8_MAX)
#define OTX2_SSO_FC_NAME "otx2_evdev_xaq_fc"
+#define OTX2_SSO_SQB_LIMIT (0x180)
#define OTX2_SSO_XAQ_SLACK (8)
#define OTX2_SSO_XAQ_CACHE_CNT (0x7)
+#define OTX2_SSO_WQE_SG_PTR (9)
/* SSO LF register offsets (BAR2) */
#define SSO_LF_GGRP_OP_ADD_WORK0 (0x0ull)
rte_iova_t fc_iova;
struct rte_mempool *xaq_pool;
uint64_t rx_offloads;
+ uint64_t tx_offloads;
+ uint64_t adptr_xae_cnt;
uint16_t rx_adptr_pool_cnt;
- uint32_t adptr_xae_cnt;
uint64_t *rx_adptr_pools;
+ uint16_t max_port_id;
+ uint16_t tim_adptr_ring_cnt;
+ uint16_t *timer_adptr_rings;
+ uint64_t *timer_adptr_sz;
/* Dev args */
uint8_t dual_ws;
uint8_t selftest;
/* MSIX offsets */
uint16_t sso_msixoff[OTX2_SSO_MAX_VHGRP];
uint16_t ssow_msixoff[OTX2_SSO_MAX_VHWS];
+ /* PTP timestamp */
+ struct otx2_timesync_info *tstamp;
} __rte_cache_aligned;
#define OTX2_SSOGWS_OPS \
uint64_t xaq_lmt __rte_cache_aligned;
uint64_t *fc_mem;
uintptr_t grps_base[OTX2_SSO_MAX_VHGRP];
+ /* PTP timestamp */
+ struct otx2_timesync_info *tstamp;
+ /* Tx Fastpath data */
+ uint8_t tx_adptr_data[] __rte_cache_aligned;
} __rte_cache_aligned;
struct otx2_ssogws_state {
uint64_t xaq_lmt __rte_cache_aligned;
uint64_t *fc_mem;
uintptr_t grps_base[OTX2_SSO_MAX_VHGRP];
+ /* PTP timestamp */
+ struct otx2_timesync_info *tstamp;
+ /* Tx Fastpath data */
+ uint8_t tx_adptr_data[] __rte_cache_aligned;
} __rte_cache_aligned;
static inline struct otx2_sso_evdev *
const void * const lookup_mem)
{
struct nix_wqe_hdr_s *wqe = (struct nix_wqe_hdr_s *)get_work1;
+ uint64_t val = mbuf_init.value | (uint64_t)port_id << 48;
+
+ if (flags & NIX_RX_OFFLOAD_TSTAMP_F)
+ val |= NIX_TIMESYNC_RX_OFFSET;
otx2_nix_cqe_to_mbuf((struct nix_cqe_hdr_s *)wqe, tag,
(struct rte_mbuf *)mbuf, lookup_mem,
- mbuf_init.value | (uint64_t)port_id << 48, flags);
+ val, flags);
}
uint16_t nb_events);
/* Auto generated API's */
-#define R(name, f5, f4, f3, f2, f1, f0, flags) \
+#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \
uint16_t otx2_ssogws_deq_ ##name(void *port, struct rte_event *ev, \
uint64_t timeout_ticks); \
uint16_t otx2_ssogws_deq_burst_ ##name(void *port, struct rte_event ev[], \
SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
#undef R
+#define T(name, f6, f5, f4, f3, f2, f1, f0, sz, flags) \
+uint16_t otx2_ssogws_tx_adptr_enq_ ## name(void *port, struct rte_event ev[],\
+ uint16_t nb_events); \
+uint16_t otx2_ssogws_tx_adptr_enq_seg_ ## name(void *port, \
+ struct rte_event ev[], \
+ uint16_t nb_events); \
+uint16_t otx2_ssogws_dual_tx_adptr_enq_ ## name(void *port, \
+ struct rte_event ev[], \
+ uint16_t nb_events); \
+uint16_t otx2_ssogws_dual_tx_adptr_enq_seg_ ## name(void *port, \
+ struct rte_event ev[], \
+ uint16_t nb_events); \
+
+SSO_TX_ADPTR_ENQ_FASTPATH_FUNC
+#undef T
+
void sso_updt_xae_cnt(struct otx2_sso_evdev *dev, void *data,
uint32_t event_type);
int sso_xae_reconfigure(struct rte_eventdev *event_dev);
const struct rte_eth_dev *eth_dev);
int otx2_sso_rx_adapter_stop(const struct rte_eventdev *event_dev,
const struct rte_eth_dev *eth_dev);
+int otx2_sso_tx_adapter_caps_get(const struct rte_eventdev *dev,
+ const struct rte_eth_dev *eth_dev,
+ uint32_t *caps);
+int otx2_sso_tx_adapter_queue_add(uint8_t id,
+ const struct rte_eventdev *event_dev,
+ const struct rte_eth_dev *eth_dev,
+ int32_t tx_queue_id);
+
+int otx2_sso_tx_adapter_queue_del(uint8_t id,
+ const struct rte_eventdev *event_dev,
+ const struct rte_eth_dev *eth_dev,
+ int32_t tx_queue_id);
+
/* Clean up API's */
typedef void (*otx2_handle_event_t)(void *arg, struct rte_event ev);
void ssogws_flush_events(struct otx2_ssogws *ws, uint8_t queue_id,