#ifndef _BNXT_RQX_H_
#define _BNXT_RQX_H_
+/* Maximum receive burst supported in vector mode. */
+#define RTE_BNXT_MAX_RX_BURST 64U
+
struct bnxt;
struct bnxt_rx_ring_info;
struct bnxt_cp_ring_info;
uint16_t nb_rx_hold; /* num held free RX desc */
uint16_t rx_free_thresh; /* max free RX desc to hold */
uint16_t queue_id; /* RX queue index */
+#if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
+ uint16_t rxrearm_nb; /* number of descs to reinit. */
+ uint16_t rxrearm_start; /* next desc index to reinit. */
+#endif
uint16_t reg_idx; /* RX queue register index */
uint16_t port_id; /* Device port identifier */
uint8_t crc_len; /* 0 if CRC stripped, 4 otherwise */
uint8_t rx_deferred_start; /* not in global dev start */
+ uint8_t rx_started; /* RX queue is started */
struct bnxt *bp;
int index;
struct bnxt_vnic_info *vnic;
uint32_t rx_buf_size;
- uint32_t rx_buf_use_size; /* useable size */
struct bnxt_rx_ring_info *rx_ring;
struct bnxt_cp_ring_info *cp_ring;
+ struct rte_mbuf fake_mbuf;
rte_atomic64_t rx_mbuf_alloc_fail;
const struct rte_memzone *mz;
};