mb0 = rxep[0].mbuf;
mb1 = rxep[1].mbuf;
- /* load buf_addr(lo 64bit) and buf_physaddr(hi 64bit) */
- RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, buf_physaddr) !=
+ /* load buf_addr(lo 64bit) and buf_iova(hi 64bit) */
+ RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, buf_iova) !=
offsetof(struct rte_mbuf, buf_addr) + 8);
vaddr0 = _mm_loadu_si128((__m128i *)&mb0->buf_addr);
vaddr1 = _mm_loadu_si128((__m128i *)&mb1->buf_addr);
mb2 = rxep[2].mbuf;
mb3 = rxep[3].mbuf;
- /* load buf_addr(lo 64bit) and buf_physaddr(hi 64bit) */
- RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, buf_physaddr) !=
+ /* load buf_addr(lo 64bit) and buf_iova(hi 64bit) */
+ RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, buf_iova) !=
offsetof(struct rte_mbuf, buf_addr) + 8);
vaddr0 = _mm_loadu_si128((__m128i *)&mb0->buf_addr);
vaddr1 = _mm_loadu_si128((__m128i *)&mb1->buf_addr);
(rxq->nb_rx_desc - 1) : (rxq->rxrearm_start - 1));
/* Update the tail pointer on the NIC */
- I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
+ I40E_PCI_REG_WC_WRITE(rxq->qrx_tail, rx_id);
}
#ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
* identifies an FDIR ID match, and zeros the RSS value
* in the mbuf on FDIR match to keep mbuf data clean.
*/
+#define FDIR_BLEND_MASK ((1 << 3) | (1 << 7))
/* Flags:
* - Take flags, shift bits to null out
* otherwise the mb0_1 register RSS field is zeroed.
*/
const __m256i fdir_zero_mask = _mm256_setzero_si256();
- const uint32_t fdir_blend_mask = (1 << 3) | (1 << 7);
__m256i tmp0_1 = _mm256_blend_epi32(fdir_zero_mask,
- fdir_mask, fdir_blend_mask);
+ fdir_mask, FDIR_BLEND_MASK);
__m256i fdir_mb0_1 = _mm256_and_si256(mb0_1, fdir_mask);
mb0_1 = _mm256_andnot_si256(tmp0_1, mb0_1);
__m256i tmp2_3 = _mm256_alignr_epi8(fdir_mask, fdir_mask, 12);
__m256i fdir_mb2_3 = _mm256_and_si256(mb2_3, tmp2_3);
tmp2_3 = _mm256_blend_epi32(fdir_zero_mask, tmp2_3,
- fdir_blend_mask);
+ FDIR_BLEND_MASK);
mb2_3 = _mm256_andnot_si256(tmp2_3, mb2_3);
rx_pkts[i + 2]->hash.fdir.hi = _mm256_extract_epi32(fdir_mb2_3, 3);
rx_pkts[i + 3]->hash.fdir.hi = _mm256_extract_epi32(fdir_mb2_3, 7);
__m256i tmp4_5 = _mm256_alignr_epi8(fdir_mask, fdir_mask, 8);
__m256i fdir_mb4_5 = _mm256_and_si256(mb4_5, tmp4_5);
tmp4_5 = _mm256_blend_epi32(fdir_zero_mask, tmp4_5,
- fdir_blend_mask);
+ FDIR_BLEND_MASK);
mb4_5 = _mm256_andnot_si256(tmp4_5, mb4_5);
rx_pkts[i + 4]->hash.fdir.hi = _mm256_extract_epi32(fdir_mb4_5, 3);
rx_pkts[i + 5]->hash.fdir.hi = _mm256_extract_epi32(fdir_mb4_5, 7);
__m256i tmp6_7 = _mm256_alignr_epi8(fdir_mask, fdir_mask, 4);
__m256i fdir_mb6_7 = _mm256_and_si256(mb6_7, tmp6_7);
tmp6_7 = _mm256_blend_epi32(fdir_zero_mask, tmp6_7,
- fdir_blend_mask);
+ FDIR_BLEND_MASK);
mb6_7 = _mm256_andnot_si256(tmp6_7, mb6_7);
rx_pkts[i + 6]->hash.fdir.hi = _mm256_extract_epi32(fdir_mb6_7, 3);
rx_pkts[i + 7]->hash.fdir.hi = _mm256_extract_epi32(fdir_mb6_7, 7);
((uint64_t)pkt->data_len << I40E_TXD_QW1_TX_BUF_SZ_SHIFT));
__m128i descriptor = _mm_set_epi64x(high_qw,
- pkt->buf_physaddr + pkt->data_off);
+ pkt->buf_iova + pkt->data_off);
_mm_store_si128((__m128i *)txdp, descriptor);
}
((uint64_t)pkt[0]->data_len << I40E_TXD_QW1_TX_BUF_SZ_SHIFT);
__m256i desc2_3 = _mm256_set_epi64x(
- hi_qw3, pkt[3]->buf_physaddr + pkt[3]->data_off,
- hi_qw2, pkt[2]->buf_physaddr + pkt[2]->data_off);
+ hi_qw3, pkt[3]->buf_iova + pkt[3]->data_off,
+ hi_qw2, pkt[2]->buf_iova + pkt[2]->data_off);
__m256i desc0_1 = _mm256_set_epi64x(
- hi_qw1, pkt[1]->buf_physaddr + pkt[1]->data_off,
- hi_qw0, pkt[0]->buf_physaddr + pkt[0]->data_off);
+ hi_qw1, pkt[1]->buf_iova + pkt[1]->data_off,
+ hi_qw0, pkt[0]->buf_iova + pkt[0]->data_off);
_mm256_store_si256((void *)(txdp + 2), desc2_3);
_mm256_store_si256((void *)txdp, desc0_1);
}
txq->tx_tail = tx_id;
- I40E_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
+ I40E_PCI_REG_WC_WRITE(txq->qtx_tail, txq->tx_tail);
return nb_pkts;
}