-/*
- * Copyright (c) 2016 QLogic Corporation.
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright (c) 2016 - 2018 Cavium Inc.
* All rights reserved.
- * www.qlogic.com
- *
- * See LICENSE.qede_pmd for copyright and licensing details.
+ * www.cavium.com
*/
#include <rte_memzone.h>
#include "bcm_osal.h"
#include "ecore.h"
#include "ecore_hw.h"
+#include "ecore_dev_api.h"
#include "ecore_iov_api.h"
#include "ecore_mcp_api.h"
#include "ecore_l2_api.h"
/* Array of memzone pointers */
static const struct rte_memzone *ecore_mz_mapping[RTE_MAX_MEMZONE];
/* Counter to track current memzone allocated */
-uint16_t ecore_mz_count;
+static uint16_t ecore_mz_count;
unsigned long qede_log2_align(unsigned long n)
{
}
OSAL_MEM_ZERO(mz_name, sizeof(*mz_name));
- snprintf(mz_name, sizeof(mz_name) - 1, "%lx",
+ snprintf(mz_name, sizeof(mz_name), "%lx",
(unsigned long)rte_get_timer_cycles());
if (core_id == (unsigned int)LCORE_ID_ANY)
- core_id = 0;
+ core_id = rte_get_master_lcore();
socket_id = rte_lcore_to_socket_id(core_id);
- mz = rte_memzone_reserve_aligned(mz_name, size,
- socket_id, 0, RTE_CACHE_LINE_SIZE);
+ mz = rte_memzone_reserve_aligned(mz_name, size, socket_id,
+ RTE_MEMZONE_IOVA_CONTIG, RTE_CACHE_LINE_SIZE);
if (!mz) {
DP_ERR(p_dev, "Unable to allocate DMA memory "
"of size %zu bytes - %s\n",
*phys = 0;
return OSAL_NULL;
}
- *phys = mz->phys_addr;
+ *phys = mz->iova;
ecore_mz_mapping[ecore_mz_count++] = mz;
DP_VERBOSE(p_dev, ECORE_MSG_SP,
"Allocated dma memory size=%zu phys=0x%lx"
" virt=%p core=%d\n",
- mz->len, (unsigned long)mz->phys_addr, mz->addr, core_id);
+ mz->len, (unsigned long)mz->iova, mz->addr, core_id);
return mz->addr;
}
}
OSAL_MEM_ZERO(mz_name, sizeof(*mz_name));
- snprintf(mz_name, sizeof(mz_name) - 1, "%lx",
+ snprintf(mz_name, sizeof(mz_name), "%lx",
(unsigned long)rte_get_timer_cycles());
if (core_id == (unsigned int)LCORE_ID_ANY)
- core_id = 0;
+ core_id = rte_get_master_lcore();
socket_id = rte_lcore_to_socket_id(core_id);
- mz = rte_memzone_reserve_aligned(mz_name, size, socket_id, 0, align);
+ mz = rte_memzone_reserve_aligned(mz_name, size, socket_id,
+ RTE_MEMZONE_IOVA_CONTIG, align);
if (!mz) {
DP_ERR(p_dev, "Unable to allocate DMA memory "
"of size %zu bytes - %s\n",
*phys = 0;
return OSAL_NULL;
}
- *phys = mz->phys_addr;
+ *phys = mz->iova;
ecore_mz_mapping[ecore_mz_count++] = mz;
DP_VERBOSE(p_dev, ECORE_MSG_SP,
"Allocated aligned dma memory size=%zu phys=0x%lx"
" virt=%p core=%d\n",
- mz->len, (unsigned long)mz->phys_addr, mz->addr, core_id);
+ mz->len, (unsigned long)mz->iova, mz->addr, core_id);
return mz->addr;
}
uint16_t j;
for (j = 0 ; j < ecore_mz_count; j++) {
- if (phys == ecore_mz_mapping[j]->phys_addr) {
+ if (phys == ecore_mz_mapping[j]->iova) {
DP_VERBOSE(p_dev, ECORE_MSG_SP,
"Free memzone %s\n", ecore_mz_mapping[j]->name);
rte_memzone_free(ecore_mz_mapping[j]);
+ while (j < ecore_mz_count - 1) {
+ ecore_mz_mapping[j] = ecore_mz_mapping[j + 1];
+ j++;
+ }
+ ecore_mz_count--;
return;
}
}
DP_ERR(p_hwfn, "HW error occurred [%s]\n", err_str);
ecore_int_attn_clr_enable(p_hwfn->p_dev, true);
}
+
+u32 qede_crc32(u32 crc, u8 *ptr, u32 length)
+{
+ int i;
+
+ while (length--) {
+ crc ^= *ptr++;
+ for (i = 0; i < 8; i++)
+ crc = (crc >> 1) ^ ((crc & 1) ? 0xedb88320 : 0);
+ }
+ return crc;
+}