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net/mlx5: optimize header modify action memory
[dpdk.git]
/
app
/
test-bbdev
/
meson.build
diff --git
a/app/test-bbdev/meson.build
b/app/test-bbdev/meson.build
index
6d50e03
..
edb9dee
100644
(file)
--- a/
app/test-bbdev/meson.build
+++ b/
app/test-bbdev/meson.build
@@
-1,17
+1,25
@@
# SPDX-License-Identifier: BSD-3-Clause
# Copyright(c) 2018 Intel Corporation
# SPDX-License-Identifier: BSD-3-Clause
# Copyright(c) 2018 Intel Corporation
-sources = files('main.c',
- 'test_bbdev.c',
- 'test_bbdev_perf.c',
- 'test_bbdev_vector.c')
+if is_windows
+ build = false
+ reason = 'not supported on Windows'
+ subdir_done()
+endif
+
+sources = files(
+ 'main.c',
+ 'test_bbdev.c',
+ 'test_bbdev_perf.c',
+ 'test_bbdev_vector.c',
+)
deps += ['bbdev', 'bus_vdev']
if dpdk_conf.has('RTE_BASEBAND_FPGA_LTE_FEC')
deps += ['bbdev', 'bus_vdev']
if dpdk_conf.has('RTE_BASEBAND_FPGA_LTE_FEC')
-
deps += ['baseband_fpga_lte_fec']
+ deps += ['baseband_fpga_lte_fec']
endif
if dpdk_conf.has('RTE_BASEBAND_FPGA_5GNR_FEC')
endif
if dpdk_conf.has('RTE_BASEBAND_FPGA_5GNR_FEC')
-
deps += ['baseband_fpga_5gnr_fec']
+ deps += ['baseband_fpga_5gnr_fec']
endif
if dpdk_conf.has('RTE_BASEBAND_ACC100')
endif
if dpdk_conf.has('RTE_BASEBAND_ACC100')
-
deps += ['baseband_acc100']
+ deps += ['baseband_acc100']
endif
endif