- ['RTE_MACHINE', '"thunderx"'],
- ['RTE_USE_C11_MEM_MODEL', false]]
-flags_part_number_thunderx2 = [
- ['RTE_MACHINE', '"thunderx2"'],
- ['RTE_CACHE_LINE_SIZE', 64],
- ['RTE_MAX_NUMA_NODES', 2],
- ['RTE_MAX_LCORE', 256],
- ['RTE_ARM_FEATURE_ATOMICS', true],
- ['RTE_USE_C11_MEM_MODEL', true]]
-flags_part_number_octeontx2 = [
- ['RTE_MACHINE', '"octeontx2"'],
- ['RTE_MAX_NUMA_NODES', 1],
- ['RTE_MAX_LCORE', 36],
- ['RTE_ARM_FEATURE_ATOMICS', true],
- ['RTE_EAL_IGB_UIO', false],
- ['RTE_USE_C11_MEM_MODEL', true]]
-flags_part_number_n1generic = [
- ['RTE_MACHINE', '"neoverse-n1"'],
- ['RTE_MAX_LCORE', 64],
- ['RTE_CACHE_LINE_SIZE', 64],
- ['RTE_ARM_FEATURE_ATOMICS', true],
- ['RTE_USE_C11_MEM_MODEL', true],
- ['RTE_MAX_MEM_MB', 1048576],
- ['RTE_MAX_NUMA_NODES', 1],
- ['RTE_EAL_NUMA_AWARE_HUGEPAGES', false],
- ['RTE_LIBRTE_VHOST_NUMA', false]]
-flags_part_number_n2generic = [
- ['RTE_MACHINE', '"neoverse-n2"'],
- ['RTE_MAX_LCORE', 64],
- ['RTE_CACHE_LINE_SIZE', 64],
- ['RTE_ARM_FEATURE_ATOMICS', true],
- ['RTE_USE_C11_MEM_MODEL', true],
- ['RTE_EAL_NUMA_AWARE_HUGEPAGES', false],
- ['RTE_LIBRTE_VHOST_NUMA', false]]
-
-part_number_config_arm = [
- ['generic', ['-march=armv8-a+crc', '-moutline-atomics']],
- ['native', ['-march=native']],
- ['0xd03', ['-mcpu=cortex-a53']],
- ['0xd04', ['-mcpu=cortex-a35']],
- ['0xd07', ['-mcpu=cortex-a57']],
- ['0xd08', ['-mcpu=cortex-a72']],
- ['0xd09', ['-mcpu=cortex-a73']],
- ['0xd0a', ['-mcpu=cortex-a75']],
- ['0xd0b', ['-mcpu=cortex-a76']],
- ['0xd0c', ['-march=armv8.2-a+crypto', '-mcpu=neoverse-n1'], flags_part_number_n1generic],
- ['0xd49', ['-march=armv8.5-a+crypto+sve2'], flags_part_number_n2generic]]
-
-part_number_config_cavium = [
- ['generic', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']],
- ['native', ['-march=native']],
- ['0xa1', ['-mcpu=thunderxt88'], flags_part_number_thunderx],
- ['0xa2', ['-mcpu=thunderxt81'], flags_part_number_thunderx],
- ['0xa3', ['-mcpu=thunderxt83'], flags_part_number_thunderx],
- ['0xaf', ['-march=armv8.1-a+crc+crypto','-mcpu=thunderx2t99'], flags_part_number_thunderx2],
- ['0xb2', ['-march=armv8.2-a+crc+crypto+lse','-mcpu=octeontx2'], flags_part_number_octeontx2]]
-
-part_number_config_emag = [
- ['generic', ['-march=armv8-a+crc+crypto', '-mtune=emag']],
- ['native', ['-march=native']]]
-
-## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page G7-5321)
-implementer_generic = ['Generic armv8', flags_implementer_generic, part_number_config_arm]
-implementer_0x41 = ['Arm', flags_implementer_arm, part_number_config_arm]
-implementer_0x43 = ['Cavium', flags_implementer_cavium, part_number_config_cavium]
-implementer_0x50 = ['Ampere Computing', flags_implementer_emag, part_number_config_emag]
-implementer_0x56 = ['Marvell ARMADA', flags_implementer_armada, part_number_config_arm]
-implementer_dpaa = ['NXP DPAA', flags_implementer_dpaa, part_number_config_arm]
+ ['RTE_MACHINE', '"thunderx"'],
+ ['RTE_USE_C11_MEM_MODEL', false]
+]
+implementer_cavium = {
+ 'description': 'Cavium',
+ 'flags': [
+ ['RTE_MAX_VFIO_GROUPS', 128],
+ ['RTE_MAX_LCORE', 96],
+ ['RTE_MAX_NUMA_NODES', 2]
+ ],
+ 'part_number_config': {
+ '0xa1': {
+ 'compiler_options': ['-mcpu=thunderxt88'],
+ 'flags': flags_part_number_thunderx
+ },
+ '0xa2': {
+ 'compiler_options': ['-mcpu=thunderxt81'],
+ 'flags': flags_part_number_thunderx
+ },
+ '0xa3': {
+ 'compiler_options': ['-mcpu=thunderxt83'],
+ 'flags': flags_part_number_thunderx
+ },
+ '0xaf': {
+ 'march': 'armv8.1-a',
+ 'march_features': ['crc', 'crypto'],
+ 'compiler_options': ['-mcpu=thunderx2t99'],
+ 'flags': [
+ ['RTE_MACHINE', '"thunderx2"'],
+ ['RTE_ARM_FEATURE_ATOMICS', true],
+ ['RTE_USE_C11_MEM_MODEL', true],
+ ['RTE_CACHE_LINE_SIZE', 64],
+ ['RTE_MAX_LCORE', 256]
+ ]
+ },
+ '0xb2': {
+ 'march': 'armv8.2-a',
+ 'march_features': ['crc', 'crypto', 'lse'],
+ 'compiler_options': ['-mcpu=octeontx2'],
+ 'flags': [
+ ['RTE_MACHINE', '"cn9k"'],
+ ['RTE_ARM_FEATURE_ATOMICS', true],
+ ['RTE_USE_C11_MEM_MODEL', true],
+ ['RTE_MAX_LCORE', 36],
+ ['RTE_MAX_NUMA_NODES', 1]
+ ]
+ }
+ }
+}
+
+implementer_ampere = {
+ 'description': 'Ampere Computing',
+ 'flags': [
+ ['RTE_MACHINE', '"emag"'],
+ ['RTE_CACHE_LINE_SIZE', 64],
+ ['RTE_MAX_LCORE', 32],
+ ['RTE_MAX_NUMA_NODES', 1]
+ ],
+ 'part_number_config': {
+ '0x0': {
+ 'march': 'armv8-a',
+ 'march_features': ['crc', 'crypto'],
+ 'compiler_options': ['-mtune=emag']
+ }
+ }
+}
+
+implementer_hisilicon = {
+ 'description': 'HiSilicon',
+ 'flags': [
+ ['RTE_USE_C11_MEM_MODEL', true],
+ ['RTE_CACHE_LINE_SIZE', 128]
+ ],
+ 'part_number_config': {
+ '0xd01': {
+ 'march': 'armv8.2-a',
+ 'march_features': ['crypto'],
+ 'compiler_options': ['-mtune=tsv110'],
+ 'flags': [
+ ['RTE_MACHINE', '"Kunpeng 920"'],
+ ['RTE_ARM_FEATURE_ATOMICS', true],
+ ['RTE_MAX_LCORE', 256],
+ ['RTE_MAX_NUMA_NODES', 8]
+ ]
+ },
+ '0xd02': {
+ 'march': 'armv8.2-a',
+ 'march_features': ['crypto', 'sve'],
+ 'flags': [
+ ['RTE_MACHINE', '"Kunpeng 930"'],
+ ['RTE_ARM_FEATURE_ATOMICS', true],
+ ['RTE_MAX_LCORE', 1280],
+ ['RTE_MAX_NUMA_NODES', 16]
+ ]
+ }
+ }
+}
+
+implementer_qualcomm = {
+ 'description': 'Qualcomm',
+ 'flags': [
+ ['RTE_MACHINE', '"armv8a"'],
+ ['RTE_USE_C11_MEM_MODEL', true],
+ ['RTE_CACHE_LINE_SIZE', 64],
+ ['RTE_MAX_LCORE', 64],
+ ['RTE_MAX_NUMA_NODES', 1]
+ ],
+ 'part_number_config': {
+ '0x800': {
+ 'march': 'armv8-a',
+ 'march_features': ['crc']
+ },
+ '0xc00': {
+ 'march': 'armv8-a',
+ 'march_features': ['crc']
+ }
+ }
+}
+
+## Arm implementers (ID from MIDR in Arm Architecture Reference Manual)
+implementers = {
+ 'generic': implementer_generic,
+ '0x41': implementer_arm,
+ '0x43': implementer_cavium,
+ '0x48': implementer_hisilicon,
+ '0x50': implementer_ampere,
+ '0x51': implementer_qualcomm
+}
+
+# SoC specific armv8 flags have the highest priority
+# (will overwrite all other flags)
+soc_generic = {
+ 'description': 'Generic un-optimized build for armv8 aarch64 exec mode',
+ 'implementer': 'generic',
+ 'part_number': 'generic'
+}
+
+soc_generic_aarch32 = {
+ 'description': 'Generic un-optimized build for armv8 aarch32 exec mode',
+ 'implementer': 'generic',
+ 'part_number': 'generic_aarch32'
+}
+
+soc_armada = {
+ 'description': 'Marvell ARMADA',
+ 'implementer': '0x41',
+ 'part_number': '0xd08',
+ 'flags': [
+ ['RTE_MAX_LCORE', 16],
+ ['RTE_MAX_NUMA_NODES', 1]
+ ],
+ 'numa': false
+}
+
+soc_bluefield = {
+ 'description': 'NVIDIA BlueField',
+ 'implementer': '0x41',
+ 'part_number': '0xd08',
+ 'flags': [
+ ['RTE_MAX_LCORE', 16],
+ ['RTE_MAX_NUMA_NODES', 1]
+ ],
+ 'numa': false
+}
+
+soc_centriq2400 = {
+ 'description': 'Qualcomm Centriq 2400',
+ 'implementer': '0x51',
+ 'part_number': '0xc00',
+ 'numa': false
+}
+
+soc_cn10k = {
+ 'description' : 'Marvell OCTEON 10',
+ 'implementer' : '0x41',
+ 'flags': [
+ ['RTE_MAX_LCORE', 24],
+ ['RTE_MAX_NUMA_NODES', 1]
+ ],
+ 'part_number': '0xd49',
+ 'extra_march_features': ['crypto'],
+ 'numa': false
+}
+
+soc_dpaa = {
+ 'description': 'NXP DPAA',
+ 'implementer': '0x41',
+ 'part_number': '0xd08',
+ 'flags': [
+ ['RTE_MACHINE', '"dpaa"'],
+ ['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false],
+ ['RTE_MAX_LCORE', 16],
+ ['RTE_MAX_NUMA_NODES', 1]
+ ],
+ 'numa': false
+}
+
+soc_emag = {
+ 'description': 'Ampere eMAG',
+ 'implementer': '0x50',
+ 'part_number': '0x0'
+}
+
+soc_graviton2 = {
+ 'description': 'AWS Graviton2',
+ 'implementer': '0x41',
+ 'part_number': '0xd0c',
+ 'numa': false
+}
+
+soc_kunpeng920 = {
+ 'description': 'HiSilicon Kunpeng 920',
+ 'implementer': '0x48',
+ 'part_number': '0xd01',
+ 'numa': true
+}
+
+soc_kunpeng930 = {
+ 'description': 'HiSilicon Kunpeng 930',
+ 'implementer': '0x48',
+ 'part_number': '0xd02',
+ 'numa': true
+}
+
+soc_n1sdp = {
+ 'description': 'Arm Neoverse N1SDP',
+ 'implementer': '0x41',
+ 'part_number': '0xd0c',
+ 'flags': [
+ ['RTE_MAX_LCORE', 4]
+ ],
+ 'numa': false
+}
+
+soc_n2 = {
+ 'description': 'Arm Neoverse N2',
+ 'implementer': '0x41',
+ 'part_number': '0xd49',
+ 'numa': false
+}
+
+soc_cn9k = {
+ 'description': 'Marvell OCTEON 9',
+ 'implementer': '0x43',
+ 'part_number': '0xb2',
+ 'numa': false
+}
+
+soc_stingray = {
+ 'description': 'Broadcom Stingray',
+ 'implementer': '0x41',
+ 'flags': [
+ ['RTE_MAX_LCORE', 16],
+ ['RTE_MAX_NUMA_NODES', 1]
+ ],
+ 'part_number': '0xd08',
+ 'numa': false
+}
+
+soc_thunderx2 = {
+ 'description': 'Marvell ThunderX2 T99',
+ 'implementer': '0x43',
+ 'part_number': '0xaf'
+}
+
+soc_thunderxt88 = {
+ 'description': 'Marvell ThunderX T88',
+ 'implementer': '0x43',
+ 'part_number': '0xa1'
+}
+
+'''
+Start of SoCs list
+generic: Generic un-optimized build for armv8 aarch64 execution mode.
+generic_aarch32: Generic un-optimized build for armv8 aarch32 execution mode.
+armada: Marvell ARMADA
+bluefield: NVIDIA BlueField
+centriq2400: Qualcomm Centriq 2400
+cn9k: Marvell OCTEON 9
+cn10k: Marvell OCTEON 10
+dpaa: NXP DPAA
+emag: Ampere eMAG
+graviton2: AWS Graviton2
+kunpeng920: HiSilicon Kunpeng 920
+kunpeng930: HiSilicon Kunpeng 930
+n1sdp: Arm Neoverse N1SDP
+n2: Arm Neoverse N2
+stingray: Broadcom Stingray
+thunderx2: Marvell ThunderX2 T99
+thunderxt88: Marvell ThunderX T88
+End of SoCs list
+'''
+# The string above is included in the documentation, keep it in sync with the
+# SoCs list below.
+socs = {
+ 'generic': soc_generic,
+ 'generic_aarch32': soc_generic_aarch32,
+ 'armada': soc_armada,
+ 'bluefield': soc_bluefield,
+ 'centriq2400': soc_centriq2400,
+ 'cn9k': soc_cn9k,
+ 'cn10k' : soc_cn10k,
+ 'dpaa': soc_dpaa,
+ 'emag': soc_emag,
+ 'graviton2': soc_graviton2,
+ 'kunpeng920': soc_kunpeng920,
+ 'kunpeng930': soc_kunpeng930,
+ 'n1sdp': soc_n1sdp,
+ 'n2': soc_n2,
+ 'stingray': soc_stingray,
+ 'thunderx2': soc_thunderx2,
+ 'thunderxt88': soc_thunderxt88
+}