-flags_generic = [
- ['RTE_MACHINE', '"armv8a"'],
- ['RTE_CACHE_LINE_SIZE', 128]]
-flags_cavium = [
- ['RTE_MACHINE', '"thunderx"'],
- ['RTE_CACHE_LINE_SIZE', 128],
- ['RTE_MAX_NUMA_NODES', 2],
- ['RTE_MAX_LCORE', 96],
- ['RTE_MAX_VFIO_GROUPS', 128],
- ['RTE_RING_USE_C11_MEM_MODEL', false]]
-
-## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page G7-5321)
-impl_generic = ['Generic armv8', flags_generic, machine_args_generic]
-impl_0x41 = ['Arm', flags_generic, machine_args_generic]
-impl_0x42 = ['Broadcom', flags_generic, machine_args_generic]
-impl_0x43 = ['Cavium', flags_cavium, machine_args_cavium]
-impl_0x44 = ['DEC', flags_generic, machine_args_generic]
-impl_0x49 = ['Infineon', flags_generic, machine_args_generic]
-impl_0x4d = ['Motorola', flags_generic, machine_args_generic]
-impl_0x4e = ['NVIDIA', flags_generic, machine_args_generic]
-impl_0x50 = ['AppliedMicro', flags_generic, machine_args_generic]
-impl_0x51 = ['Qualcomm', flags_generic, machine_args_generic]
-impl_0x53 = ['Samsung', flags_generic, machine_args_generic]
-impl_0x56 = ['Marvell', flags_generic, machine_args_generic]
-impl_0x69 = ['Intel', flags_generic, machine_args_generic]
-
-
-if cc.get_define('__clang__') != ''
- dpdk_conf.set_quoted('RTE_TOOLCHAIN', 'clang')
- dpdk_conf.set('RTE_TOOLCHAIN_CLANG', 1)
-else
- dpdk_conf.set_quoted('RTE_TOOLCHAIN', 'gcc')
- dpdk_conf.set('RTE_TOOLCHAIN_GCC', 1)
-endif
+implementer_ampere = {
+ 'description': 'Ampere Computing',
+ 'flags': [
+ ['RTE_MACHINE', '"emag"'],
+ ['RTE_CACHE_LINE_SIZE', 64],
+ ['RTE_MAX_LCORE', 32],
+ ['RTE_MAX_NUMA_NODES', 1]
+ ],
+ 'part_number_config': {
+ '0x0': {
+ 'march': 'armv8-a',
+ 'march_features': ['crc', 'crypto'],
+ 'compiler_options': ['-mtune=emag']
+ }
+ }
+}
+
+implementer_hisilicon = {
+ 'description': 'HiSilicon',
+ 'flags': [
+ ['RTE_USE_C11_MEM_MODEL', true],
+ ['RTE_CACHE_LINE_SIZE', 128]
+ ],
+ 'part_number_config': {
+ '0xd01': {
+ 'march': 'armv8.2-a',
+ 'march_features': ['crypto'],
+ 'compiler_options': ['-mtune=tsv110'],
+ 'flags': [
+ ['RTE_MACHINE', '"Kunpeng 920"'],
+ ['RTE_ARM_FEATURE_ATOMICS', true],
+ ['RTE_MAX_LCORE', 256],
+ ['RTE_MAX_NUMA_NODES', 8]
+ ]
+ },
+ '0xd02': {
+ 'march': 'armv8.2-a',
+ 'march_features': ['crypto', 'sve'],
+ 'flags': [
+ ['RTE_MACHINE', '"Kunpeng 930"'],
+ ['RTE_ARM_FEATURE_ATOMICS', true],
+ ['RTE_MAX_LCORE', 1280],
+ ['RTE_MAX_NUMA_NODES', 16]
+ ]
+ }
+ }
+}
+
+implementer_qualcomm = {
+ 'description': 'Qualcomm',
+ 'flags': [
+ ['RTE_MACHINE', '"armv8a"'],
+ ['RTE_USE_C11_MEM_MODEL', true],
+ ['RTE_CACHE_LINE_SIZE', 64],
+ ['RTE_MAX_LCORE', 64],
+ ['RTE_MAX_NUMA_NODES', 1]
+ ],
+ 'part_number_config': {
+ '0x800': {
+ 'march': 'armv8-a',
+ 'march_features': ['crc']
+ },
+ '0xc00': {
+ 'march': 'armv8-a',
+ 'march_features': ['crc']
+ }
+ }
+}
+
+## Arm implementers (ID from MIDR in Arm Architecture Reference Manual)
+implementers = {
+ 'generic': implementer_generic,
+ '0x41': implementer_arm,
+ '0x43': implementer_cavium,
+ '0x48': implementer_hisilicon,
+ '0x50': implementer_ampere,
+ '0x51': implementer_qualcomm
+}
+
+# SoC specific armv8 flags have the highest priority
+# (will overwrite all other flags)
+soc_generic = {
+ 'description': 'Generic un-optimized build for armv8 aarch64 exec mode',
+ 'implementer': 'generic',
+ 'part_number': 'generic'
+}
+
+soc_generic_aarch32 = {
+ 'description': 'Generic un-optimized build for armv8 aarch32 exec mode',
+ 'implementer': 'generic',
+ 'part_number': 'generic_aarch32'
+}
+
+soc_armada = {
+ 'description': 'Marvell ARMADA',
+ 'implementer': '0x41',
+ 'part_number': '0xd08',
+ 'flags': [
+ ['RTE_MAX_LCORE', 16],
+ ['RTE_MAX_NUMA_NODES', 1]
+ ],
+ 'numa': false
+}
+
+soc_bluefield = {
+ 'description': 'NVIDIA BlueField',
+ 'implementer': '0x41',
+ 'part_number': '0xd08',
+ 'flags': [
+ ['RTE_MAX_LCORE', 16],
+ ['RTE_MAX_NUMA_NODES', 1]
+ ],
+ 'numa': false
+}
+
+soc_centriq2400 = {
+ 'description': 'Qualcomm Centriq 2400',
+ 'implementer': '0x51',
+ 'part_number': '0xc00',
+ 'numa': false
+}
+
+soc_cn10k = {
+ 'description' : 'Marvell OCTEON 10',
+ 'implementer' : '0x41',
+ 'flags': [
+ ['RTE_MAX_LCORE', 24],
+ ['RTE_MAX_NUMA_NODES', 1]
+ ],
+ 'part_number': '0xd49',
+ 'extra_march_features': ['crypto'],
+ 'numa': false
+}
+
+soc_dpaa = {
+ 'description': 'NXP DPAA',
+ 'implementer': '0x41',
+ 'part_number': '0xd08',
+ 'flags': [
+ ['RTE_MACHINE', '"dpaa"'],
+ ['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false],
+ ['RTE_MAX_LCORE', 16],
+ ['RTE_MAX_NUMA_NODES', 1]
+ ],
+ 'numa': false
+}
+
+soc_emag = {
+ 'description': 'Ampere eMAG',
+ 'implementer': '0x50',
+ 'part_number': '0x0'
+}
+
+soc_graviton2 = {
+ 'description': 'AWS Graviton2',
+ 'implementer': '0x41',
+ 'part_number': '0xd0c',
+ 'numa': false
+}
+
+soc_kunpeng920 = {
+ 'description': 'HiSilicon Kunpeng 920',
+ 'implementer': '0x48',
+ 'part_number': '0xd01',
+ 'numa': true
+}
+
+soc_kunpeng930 = {
+ 'description': 'HiSilicon Kunpeng 930',
+ 'implementer': '0x48',
+ 'part_number': '0xd02',
+ 'numa': true
+}
+
+soc_n1sdp = {
+ 'description': 'Arm Neoverse N1SDP',
+ 'implementer': '0x41',
+ 'part_number': '0xd0c',
+ 'flags': [
+ ['RTE_MAX_LCORE', 4]
+ ],
+ 'numa': false
+}