+flags_armada = [
+ ['RTE_MACHINE', '"armv8a"'],
+ ['RTE_CACHE_LINE_SIZE', 64],
+ ['RTE_MAX_NUMA_NODES', 1],
+ ['RTE_MAX_LCORE', 16]]
+
+flags_default_extra = []
+flags_thunderx_extra = [
+ ['RTE_MACHINE', '"thunderx"'],
+ ['RTE_USE_C11_MEM_MODEL', false]]
+flags_thunderx2_extra = [
+ ['RTE_MACHINE', '"thunderx2"'],
+ ['RTE_CACHE_LINE_SIZE', 64],
+ ['RTE_MAX_NUMA_NODES', 2],
+ ['RTE_MAX_LCORE', 256],
+ ['RTE_USE_C11_MEM_MODEL', true]]
+flags_octeontx2_extra = [
+ ['RTE_MACHINE', '"octeontx2"'],
+ ['RTE_MAX_NUMA_NODES', 1],
+ ['RTE_MAX_LCORE', 24],
+ ['RTE_EAL_IGB_UIO', false],
+ ['RTE_USE_C11_MEM_MODEL', true]]
+
+machine_args_generic = [
+ ['default', ['-march=armv8-a+crc']],
+ ['native', ['-march=native']],
+ ['0xd03', ['-mcpu=cortex-a53']],
+ ['0xd04', ['-mcpu=cortex-a35']],
+ ['0xd07', ['-mcpu=cortex-a57']],
+ ['0xd08', ['-mcpu=cortex-a72']],
+ ['0xd09', ['-mcpu=cortex-a73']],
+ ['0xd0a', ['-mcpu=cortex-a75']]]
+
+machine_args_cavium = [
+ ['default', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']],
+ ['native', ['-march=native']],
+ ['0xa1', ['-mcpu=thunderxt88'], flags_thunderx_extra],
+ ['0xa2', ['-mcpu=thunderxt81'], flags_thunderx_extra],
+ ['0xa3', ['-mcpu=thunderxt83'], flags_thunderx_extra],
+ ['0xaf', ['-mcpu=thunderx2t99'], flags_thunderx2_extra],
+ ['0xb2', ['-mcpu=octeontx2'], flags_octeontx2_extra]]