+ ['RTE_SCHED_VECTOR', false],
+ ['RTE_ARM_USE_WFE', false],
+ ['RTE_ARCH_ARM64', true],
+ ['RTE_CACHE_LINE_SIZE', 128]
+]
+
+## Part numbers are specific to Arm implementers
+# implementer specific aarch64 flags have middle priority
+# (will overwrite common flags)
+# part number specific aarch64 flags have higher priority
+# (will overwrite both common and implementer specific flags)
+implementer_generic = {
+ 'description': 'Generic armv8',
+ 'flags': [
+ ['RTE_MACHINE', '"armv8a"'],
+ ['RTE_USE_C11_MEM_MODEL', true],
+ ['RTE_MAX_LCORE', 256],
+ ['RTE_MAX_NUMA_NODES', 4]
+ ],
+ 'part_number_config': {
+ 'generic': {'machine_args': ['-march=armv8-a+crc', '-moutline-atomics']}
+ }
+}
+
+part_number_config_arm = {
+ '0xd03': {'machine_args': ['-mcpu=cortex-a53']},
+ '0xd04': {'machine_args': ['-mcpu=cortex-a35']},
+ '0xd07': {'machine_args': ['-mcpu=cortex-a57']},
+ '0xd08': {'machine_args': ['-mcpu=cortex-a72']},
+ '0xd09': {'machine_args': ['-mcpu=cortex-a73']},
+ '0xd0a': {'machine_args': ['-mcpu=cortex-a75']},
+ '0xd0b': {'machine_args': ['-mcpu=cortex-a76']},
+ '0xd0c': {
+ 'machine_args': ['-march=armv8.2-a+crypto', '-mcpu=neoverse-n1'],
+ 'flags': [
+ ['RTE_MACHINE', '"neoverse-n1"'],
+ ['RTE_ARM_FEATURE_ATOMICS', true],
+ ['RTE_MAX_MEM_MB', 1048576],
+ ['RTE_MAX_LCORE', 160],
+ ['RTE_MAX_NUMA_NODES', 2]
+ ]
+ },
+ '0xd49': {
+ 'machine_args': ['-march=armv8.5-a+crypto+sve2'],
+ 'flags': [
+ ['RTE_MACHINE', '"neoverse-n2"'],
+ ['RTE_ARM_FEATURE_ATOMICS', true],
+ ['RTE_MAX_LCORE', 64],
+ ['RTE_MAX_NUMA_NODES', 1]
+ ]
+ }
+}
+implementer_arm = {
+ 'description': 'Arm',
+ 'flags': [
+ ['RTE_MACHINE', '"armv8a"'],
+ ['RTE_USE_C11_MEM_MODEL', true],
+ ['RTE_CACHE_LINE_SIZE', 64],
+ ['RTE_MAX_LCORE', 64],
+ ['RTE_MAX_NUMA_NODES', 4]
+ ],
+ 'part_number_config': part_number_config_arm
+}
+
+flags_part_number_thunderx = [
+ ['RTE_MACHINE', '"thunderx"'],
+ ['RTE_USE_C11_MEM_MODEL', false]
+]
+implementer_cavium = {
+ 'description': 'Cavium',
+ 'flags': [
+ ['RTE_MAX_VFIO_GROUPS', 128],
+ ['RTE_MAX_LCORE', 96],
+ ['RTE_MAX_NUMA_NODES', 2]
+ ],
+ 'part_number_config': {
+ '0xa1': {
+ 'machine_args': ['-mcpu=thunderxt88'],
+ 'flags': flags_part_number_thunderx
+ },
+ '0xa2': {
+ 'machine_args': ['-mcpu=thunderxt81'],
+ 'flags': flags_part_number_thunderx
+ },
+ '0xa3': {
+ 'machine_args': ['-mcpu=thunderxt83'],
+ 'flags': flags_part_number_thunderx
+ },
+ '0xaf': {
+ 'machine_args': ['-march=armv8.1-a+crc+crypto', '-mcpu=thunderx2t99'],
+ 'flags': [
+ ['RTE_MACHINE', '"thunderx2"'],
+ ['RTE_ARM_FEATURE_ATOMICS', true],
+ ['RTE_USE_C11_MEM_MODEL', true],
+ ['RTE_CACHE_LINE_SIZE', 64],
+ ['RTE_MAX_LCORE', 256]
+ ]
+ },
+ '0xb2': {
+ 'machine_args': ['-march=armv8.2-a+crc+crypto+lse', '-mcpu=octeontx2'],
+ 'flags': [
+ ['RTE_MACHINE', '"octeontx2"'],
+ ['RTE_ARM_FEATURE_ATOMICS', true],
+ ['RTE_USE_C11_MEM_MODEL', true],
+ ['RTE_MAX_LCORE', 36],
+ ['RTE_MAX_NUMA_NODES', 1]
+ ]
+ }
+ }
+}
+
+implementer_ampere = {
+ 'description': 'Ampere Computing',
+ 'flags': [
+ ['RTE_MACHINE', '"emag"'],
+ ['RTE_CACHE_LINE_SIZE', 64],
+ ['RTE_MAX_LCORE', 32],
+ ['RTE_MAX_NUMA_NODES', 1]
+ ],
+ 'part_number_config': {
+ '0x0': {'machine_args': ['-march=armv8-a+crc+crypto', '-mtune=emag']}
+ }
+}
+
+implementer_hisilicon = {
+ 'description': 'HiSilicon',
+ 'flags': [
+ ['RTE_USE_C11_MEM_MODEL', true],
+ ['RTE_CACHE_LINE_SIZE', 128]
+ ],
+ 'part_number_config': {
+ '0xd01': {
+ 'machine_args': ['-march=armv8.2-a+crypto', '-mtune=tsv110'],
+ 'flags': [
+ ['RTE_MACHINE', '"Kunpeng 920"'],
+ ['RTE_ARM_FEATURE_ATOMICS', true],
+ ['RTE_MAX_LCORE', 256],
+ ['RTE_MAX_NUMA_NODES', 8]
+ ]
+ },
+ '0xd02': {
+ 'machine_args': ['-march=armv8.2-a+crypto+sve'],
+ 'flags': [
+ ['RTE_MACHINE', '"Kunpeng 930"'],
+ ['RTE_ARM_FEATURE_ATOMICS', true],
+ ['RTE_MAX_LCORE', 1280],
+ ['RTE_MAX_NUMA_NODES', 16]
+ ]
+ }
+ }
+}
+
+implementer_qualcomm = {
+ 'description': 'Qualcomm',
+ 'flags': [
+ ['RTE_MACHINE', '"armv8a"'],
+ ['RTE_USE_C11_MEM_MODEL', true],
+ ['RTE_CACHE_LINE_SIZE', 64],
+ ['RTE_MAX_LCORE', 64],
+ ['RTE_MAX_NUMA_NODES', 1]
+ ],
+ 'part_number_config': {
+ '0xc00': {'machine_args': ['-march=armv8-a+crc']}
+ }
+}
+
+## Arm implementers (ID from MIDR in Arm Architecture Reference Manual)
+implementers = {
+ 'generic': implementer_generic,
+ '0x41': implementer_arm,
+ '0x43': implementer_cavium,
+ '0x48': implementer_hisilicon,
+ '0x50': implementer_ampere,
+ '0x51': implementer_qualcomm
+}
+
+# SoC specific aarch64 flags have the highest priority
+# (will overwrite all other flags)
+soc_generic = {
+ 'description': 'Generic un-optimized build for all aarch64 machines',
+ 'implementer': 'generic',
+ 'part_number': 'generic'
+}
+
+soc_armada = {
+ 'description': 'Marvell ARMADA',
+ 'implementer': '0x41',
+ 'part_number': '0xd08',
+ 'flags': [
+ ['RTE_MAX_LCORE', 16],
+ ['RTE_MAX_NUMA_NODES', 1]
+ ],
+ 'numa': false
+}
+
+soc_bluefield = {
+ 'description': 'NVIDIA BlueField',
+ 'implementer': '0x41',
+ 'part_number': '0xd08',
+ 'flags': [
+ ['RTE_MAX_LCORE', 16],
+ ['RTE_MAX_NUMA_NODES', 1]
+ ],
+ 'numa': false
+}
+
+soc_centriq2400 = {
+ 'description': 'Qualcomm Centriq 2400',
+ 'implementer': '0x51',
+ 'part_number': '0xc00',
+ 'numa': false
+}
+
+soc_cn10k = {
+ 'description' : 'Marvell OCTEON 10',
+ 'implementer' : '0x41',
+ 'flags': [
+ ['RTE_MAX_LCORE', 24],
+ ['RTE_MAX_NUMA_NODES', 1]
+ ],
+ 'part_number': '0xd49',
+ 'numa': false
+}
+
+soc_dpaa = {
+ 'description': 'NXP DPAA',
+ 'implementer': '0x41',
+ 'part_number': '0xd08',
+ 'flags': [
+ ['RTE_MACHINE', '"dpaa"'],
+ ['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false],
+ ['RTE_MAX_LCORE', 16],
+ ['RTE_MAX_NUMA_NODES', 1]
+ ],
+ 'numa': false
+}
+
+soc_emag = {
+ 'description': 'Ampere eMAG',
+ 'implementer': '0x50',
+ 'part_number': '0x0'
+}
+
+soc_graviton2 = {
+ 'description': 'AWS Graviton2',
+ 'implementer': '0x41',
+ 'part_number': '0xd0c',
+ 'numa': false
+}
+
+soc_kunpeng920 = {
+ 'description': 'HiSilicon Kunpeng 920',
+ 'implementer': '0x48',
+ 'part_number': '0xd01',
+ 'numa': true
+}
+
+soc_kunpeng930 = {
+ 'description': 'HiSilicon Kunpeng 930',
+ 'implementer': '0x48',
+ 'part_number': '0xd02',
+ 'numa': true
+}
+
+soc_n1sdp = {
+ 'description': 'Arm Neoverse N1SDP',
+ 'implementer': '0x41',
+ 'part_number': '0xd0c',
+ 'flags': [
+ ['RTE_MAX_LCORE', 4]
+ ],
+ 'numa': false
+}
+
+soc_n2 = {
+ 'description': 'Arm Neoverse N2',
+ 'implementer': '0x41',
+ 'part_number': '0xd49',
+ 'numa': false
+}
+
+soc_octeontx2 = {
+ 'description': 'Marvell OCTEON TX2',
+ 'implementer': '0x43',
+ 'part_number': '0xb2',
+ 'numa': false
+}
+
+soc_stingray = {
+ 'description': 'Broadcom Stingray',
+ 'implementer': '0x41',
+ 'flags': [
+ ['RTE_MAX_LCORE', 16],
+ ['RTE_MAX_NUMA_NODES', 1]
+ ],
+ 'part_number': '0xd08',
+ 'numa': false
+}
+
+soc_thunderx2 = {
+ 'description': 'Marvell ThunderX2 T99',
+ 'implementer': '0x43',
+ 'part_number': '0xaf'
+}
+
+soc_thunderxt88 = {
+ 'description': 'Marvell ThunderX T88',
+ 'implementer': '0x43',
+ 'part_number': '0xa1'
+}
+
+'''
+Start of SoCs list
+generic: Generic un-optimized build for all aarch64 machines.
+armada: Marvell ARMADA
+bluefield: NVIDIA BlueField
+centriq2400: Qualcomm Centriq 2400
+cn10k: Marvell OCTEON 10
+dpaa: NXP DPAA
+emag: Ampere eMAG
+graviton2: AWS Graviton2
+kunpeng920: HiSilicon Kunpeng 920
+kunpeng930: HiSilicon Kunpeng 930
+n1sdp: Arm Neoverse N1SDP
+n2: Arm Neoverse N2
+octeontx2: Marvell OCTEON TX2
+stingray: Broadcom Stingray
+thunderx2: Marvell ThunderX2 T99
+thunderxt88: Marvell ThunderX T88
+End of SoCs list
+'''
+# The string above is included in the documentation, keep it in sync with the
+# SoCs list below.
+socs = {
+ 'generic': soc_generic,
+ 'armada': soc_armada,
+ 'bluefield': soc_bluefield,
+ 'centriq2400': soc_centriq2400,
+ 'cn10k' : soc_cn10k,
+ 'dpaa': soc_dpaa,
+ 'emag': soc_emag,
+ 'graviton2': soc_graviton2,
+ 'kunpeng920': soc_kunpeng920,
+ 'kunpeng930': soc_kunpeng930,
+ 'n1sdp': soc_n1sdp,
+ 'n2': soc_n2,
+ 'octeontx2': soc_octeontx2,
+ 'stingray': soc_stingray,
+ 'thunderx2': soc_thunderx2,
+ 'thunderxt88': soc_thunderxt88
+}
+
+dpdk_conf.set('RTE_ARCH_ARM', 1)