- ['RTE_USE_C11_MEM_MODEL', false]]
-flags_thunderx2_extra = [
- ['RTE_MACHINE', '"thunderx2"'],
- ['RTE_CACHE_LINE_SIZE', 64],
- ['RTE_MAX_NUMA_NODES', 2],
- ['RTE_MAX_LCORE', 256],
- ['RTE_ARM_FEATURE_ATOMICS', true],
- ['RTE_USE_C11_MEM_MODEL', true]]
-flags_octeontx2_extra = [
- ['RTE_MACHINE', '"octeontx2"'],
- ['RTE_MAX_NUMA_NODES', 1],
- ['RTE_MAX_LCORE', 36],
- ['RTE_ARM_FEATURE_ATOMICS', true],
- ['RTE_EAL_IGB_UIO', false],
- ['RTE_USE_C11_MEM_MODEL', true]]
-flags_n1generic_extra = [
- ['RTE_MACHINE', '"neoverse-n1"'],
- ['RTE_MAX_LCORE', 64],
- ['RTE_CACHE_LINE_SIZE', 64],
- ['RTE_ARM_FEATURE_ATOMICS', true],
- ['RTE_USE_C11_MEM_MODEL', true],
- ['RTE_MAX_MEM_MB', 1048576],
- ['RTE_MAX_NUMA_NODES', 1],
- ['RTE_EAL_NUMA_AWARE_HUGEPAGES', false],
- ['RTE_LIBRTE_VHOST_NUMA', false]]
-flags_n2generic_extra = [
- ['RTE_MACHINE', '"neoverse-n2"'],
- ['RTE_MAX_LCORE', 64],
- ['RTE_CACHE_LINE_SIZE', 64],
- ['RTE_ARM_FEATURE_ATOMICS', true],
- ['RTE_USE_C11_MEM_MODEL', true],
- ['RTE_EAL_NUMA_AWARE_HUGEPAGES', false],
- ['RTE_LIBRTE_VHOST_NUMA', false]]
-
-machine_args_generic = [
- ['default', ['-march=armv8-a+crc', '-moutline-atomics']],
- ['native', ['-march=native']],
- ['0xd03', ['-mcpu=cortex-a53']],
- ['0xd04', ['-mcpu=cortex-a35']],
- ['0xd07', ['-mcpu=cortex-a57']],
- ['0xd08', ['-mcpu=cortex-a72']],
- ['0xd09', ['-mcpu=cortex-a73']],
- ['0xd0a', ['-mcpu=cortex-a75']],
- ['0xd0b', ['-mcpu=cortex-a76']],
- ['0xd0c', ['-march=armv8.2-a+crypto', '-mcpu=neoverse-n1'], flags_n1generic_extra],
- ['0xd49', ['-march=armv8.5-a+crypto+sve2'], flags_n2generic_extra]]
-
-machine_args_cavium = [
- ['default', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']],
- ['native', ['-march=native']],
- ['0xa1', ['-mcpu=thunderxt88'], flags_thunderx_extra],
- ['0xa2', ['-mcpu=thunderxt81'], flags_thunderx_extra],
- ['0xa3', ['-mcpu=thunderxt83'], flags_thunderx_extra],
- ['0xaf', ['-march=armv8.1-a+crc+crypto','-mcpu=thunderx2t99'], flags_thunderx2_extra],
- ['0xb2', ['-march=armv8.2-a+crc+crypto+lse','-mcpu=octeontx2'], flags_octeontx2_extra]]
-
-machine_args_emag = [
- ['default', ['-march=armv8-a+crc+crypto', '-mtune=emag']],
- ['native', ['-march=native']]]
-
-## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page G7-5321)
-impl_generic = ['Generic armv8', flags_generic, machine_args_generic]
-impl_0x41 = ['Arm', flags_arm, machine_args_generic]
-impl_0x42 = ['Broadcom', flags_generic, machine_args_generic]
-impl_0x43 = ['Cavium', flags_cavium, machine_args_cavium]
-impl_0x44 = ['DEC', flags_generic, machine_args_generic]
-impl_0x49 = ['Infineon', flags_generic, machine_args_generic]
-impl_0x4d = ['Motorola', flags_generic, machine_args_generic]
-impl_0x4e = ['NVIDIA', flags_generic, machine_args_generic]
-impl_0x50 = ['Ampere Computing', flags_emag, machine_args_emag]
-impl_0x51 = ['Qualcomm', flags_generic, machine_args_generic]
-impl_0x53 = ['Samsung', flags_generic, machine_args_generic]
-impl_0x56 = ['Marvell ARMADA', flags_armada, machine_args_generic]
-impl_0x69 = ['Intel', flags_generic, machine_args_generic]
-impl_dpaa = ['NXP DPAA', flags_dpaa, machine_args_generic]
+ ['RTE_USE_C11_MEM_MODEL', false]
+]
+implementer_cavium = {
+ 'description': 'Cavium',
+ 'flags': [
+ ['RTE_MAX_VFIO_GROUPS', 128],
+ ['RTE_MAX_LCORE', 96],
+ ['RTE_MAX_NUMA_NODES', 2]
+ ],
+ 'part_number_config': {
+ '0xa1': {
+ 'machine_args': ['-mcpu=thunderxt88'],
+ 'flags': flags_part_number_thunderx
+ },
+ '0xa2': {
+ 'machine_args': ['-mcpu=thunderxt81'],
+ 'flags': flags_part_number_thunderx
+ },
+ '0xa3': {
+ 'machine_args': ['-mcpu=thunderxt83'],
+ 'flags': flags_part_number_thunderx
+ },
+ '0xaf': {
+ 'machine_args': ['-march=armv8.1-a+crc+crypto',
+ '-mcpu=thunderx2t99'],
+ 'flags': [
+ ['RTE_MACHINE', '"thunderx2"'],
+ ['RTE_ARM_FEATURE_ATOMICS', true],
+ ['RTE_USE_C11_MEM_MODEL', true],
+ ['RTE_CACHE_LINE_SIZE', 64],
+ ['RTE_MAX_LCORE', 256]
+ ]
+ },
+ '0xb2': {
+ 'machine_args': ['-march=armv8.2-a+crc+crypto+lse',
+ '-mcpu=octeontx2'],
+ 'flags': [
+ ['RTE_MACHINE', '"octeontx2"'],
+ ['RTE_ARM_FEATURE_ATOMICS', true],
+ ['RTE_USE_C11_MEM_MODEL', true],
+ ['RTE_EAL_IGB_UIO', false],
+ ['RTE_MAX_LCORE', 36],
+ ['RTE_MAX_NUMA_NODES', 1]
+ ]
+ }
+ }
+}
+
+implementer_ampere = {
+ 'description': 'Ampere Computing',
+ 'flags': [
+ ['RTE_MACHINE', '"emag"'],
+ ['RTE_CACHE_LINE_SIZE', 64],
+ ['RTE_MAX_LCORE', 32],
+ ['RTE_MAX_NUMA_NODES', 1]
+ ],
+ 'part_number_config': {
+ '0x0': {'machine_args': ['-march=armv8-a+crc+crypto',
+ '-mtune=emag']}
+ }
+}
+
+implementer_marvell = {
+ 'description': 'Marvell ARMADA',
+ 'flags': [
+ ['RTE_MACHINE', '"armv8a"'],
+ ['RTE_CACHE_LINE_SIZE', 64],
+ ['RTE_MAX_LCORE', 16],
+ ['RTE_MAX_NUMA_NODES', 1]
+ ],
+ 'part_number_config': part_number_config_arm
+}
+
+implementer_dpaa = {
+ 'description': 'NXP DPAA',
+ 'flags': [
+ ['RTE_MACHINE', '"dpaa"'],
+ ['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false],
+ ['RTE_USE_C11_MEM_MODEL', true],
+ ['RTE_CACHE_LINE_SIZE', 64],
+ ['RTE_MAX_LCORE', 16],
+ ['RTE_MAX_NUMA_NODES', 1]
+ ],
+ 'part_number_config': part_number_config_arm
+}
+
+## Arm implementers (ID from MIDR in Arm Architecture Reference Manual)
+implementers = {
+ 'generic': implementer_generic,
+ '0x41': implementer_arm,
+ '0x43': implementer_cavium,
+ '0x50': implementer_ampere,
+ '0x56': implementer_marvell,
+ 'dpaa': implementer_dpaa
+}