doc: refer PMD compile/test section from qede guide

[dpdk.git] / doc / guides / prog_guide / lpm6_lib.rst

diff --git a/doc/guides/prog_guide/lpm6_lib.rst b/doc/guides/prog_guide/lpm6_lib.rst
index 87f5066..f791507 100644 (file)
--- a/doc/guides/prog_guide/lpm6_lib.rst
+++ b/doc/guides/prog_guide/lpm6_lib.rst
@@ -53,7 +53,7 @@ several thousand IPv6 rules, but the number can vary depending on the case.
 An LPM prefix is represented by a pair of parameters (128-bit key, depth), with depth in the range of 1 to 128.
 An LPM rule is represented by an LPM prefix and some user data associated with the prefix.
 The prefix serves as the unique identifier for the LPM rule.
 An LPM prefix is represented by a pair of parameters (128-bit key, depth), with depth in the range of 1 to 128.
 An LPM rule is represented by an LPM prefix and some user data associated with the prefix.
 The prefix serves as the unique identifier for the LPM rule.

-In this implementation, the user data is 1-byte long and is called "next hop",
+In this implementation, the user data is 21-bits long and is called "next hop",

 which corresponds to its main use of storing the ID of the next hop in a routing table entry.
 
 The main methods exported for the LPM component are:
 which corresponds to its main use of storing the ID of the next hop in a routing table entry.
 
 The main methods exported for the LPM component are:


@@ -75,7 +75,7 @@ The main methods exported for the LPM component are:
 Implementation Details
 ~~~~~~~~~~~~~~~~~~~~~~
 
 Implementation Details
 ~~~~~~~~~~~~~~~~~~~~~~
 

-This is a modification of the algorithm used for IPv4 (see Section 19.2 "Implementation Details").
+This is a modification of the algorithm used for IPv4 (see :ref:`lpm4_details`).

 In this case, instead of using two levels, one with a tbl24 and a second with a tbl8, 14 levels are used.
 
 The implementation can be seen as a multi-bit trie where the *stride*
 In this case, instead of using two levels, one with a tbl24 and a second with a tbl8, 14 levels are used.
 
 The implementation can be seen as a multi-bit trie where the *stride*