+ Requires max SIMD bitwidth to be at least 256.
+
+* **RTE_ACL_CLASSIFY_NEON**: vector implementation, can process up to 8 flows
+ in parallel. Requires NEON support. Requires max SIMD bitwidth to be at least 128.
+
+* **RTE_ACL_CLASSIFY_ALTIVEC**: vector implementation, can process up to 8
+ flows in parallel. Requires ALTIVEC support. Requires max SIMD bitwidth to be at least 128.
+
+* **RTE_ACL_CLASSIFY_AVX512X16**: vector implementation, can process up to 16
+ flows in parallel. Uses 256-bit width SIMD registers.
+ Requires AVX512 support. Requires max SIMD bitwidth to be at least 256.
+
+* **RTE_ACL_CLASSIFY_AVX512X32**: vector implementation, can process up to 32
+ flows in parallel. Uses 512-bit width SIMD registers.
+ Requires AVX512 support. Requires max SIMD bitwidth to be at least 512.