mempool: support handler operations

[dpdk.git] / doc / guides / prog_guide / writing_efficient_code.rst

diff --git a/doc/guides/prog_guide/writing_efficient_code.rst b/doc/guides/prog_guide/writing_efficient_code.rst
index 9a7b31b..78d2afa 100644 (file)
--- a/doc/guides/prog_guide/writing_efficient_code.rst
+++ b/doc/guides/prog_guide/writing_efficient_code.rst
@@ -113,7 +113,7 @@ it is advised to use the DPDK ring API, which provides a lockless ring implement
 
 The ring supports bulk and burst access,
 meaning that it is possible to read several elements from the ring with only one costly atomic operation
 
 The ring supports bulk and burst access,
 meaning that it is possible to read several elements from the ring with only one costly atomic operation

-(see Chapter 5 "Ring Library").
+(see :doc:`ring_lib`).

 Performance is greatly improved when using bulk access operations.
 
 The code algorithm that dequeues messages may be something similar to the following:
 Performance is greatly improved when using bulk access operations.
 
 The code algorithm that dequeues messages may be something similar to the following:


@@ -215,7 +215,7 @@ Setting the Target CPU Type
 
 The DPDK supports CPU microarchitecture-specific optimizations by means of CONFIG_RTE_MACHINE option
 in the DPDK configuration file.
 
 The DPDK supports CPU microarchitecture-specific optimizations by means of CONFIG_RTE_MACHINE option
 in the DPDK configuration file.

-The degree of optimization depends on the compiler's ability to optimize for a specitic microarchitecture,
+The degree of optimization depends on the compiler's ability to optimize for a specific microarchitecture,

 therefore it is preferable to use the latest compiler versions whenever possible.
 
 If the compiler version does not support the specific feature set (for example, the Intel® AVX instruction set),
 therefore it is preferable to use the latest compiler versions whenever possible.
 
 If the compiler version does not support the specific feature set (for example, the Intel® AVX instruction set),