+#ifdef RTE_LIBRTE_BBDEV_DEBUG
+RTE_LOG_REGISTER(fpga_5gnr_fec_logtype, pmd.bb.fpga_5gnr_fec, DEBUG);
+#else
+RTE_LOG_REGISTER(fpga_5gnr_fec_logtype, pmd.bb.fpga_5gnr_fec, NOTICE);
+#endif
+
+#ifdef RTE_LIBRTE_BBDEV_DEBUG
+
+/* Read Ring Control Register of FPGA 5GNR FEC device */
+static inline void
+print_ring_reg_debug_info(void *mmio_base, uint32_t offset)
+{
+ rte_bbdev_log_debug(
+ "FPGA MMIO base address @ %p | Ring Control Register @ offset = 0x%08"
+ PRIx32, mmio_base, offset);
+ rte_bbdev_log_debug(
+ "RING_BASE_ADDR = 0x%016"PRIx64,
+ fpga_reg_read_64(mmio_base, offset));
+ rte_bbdev_log_debug(
+ "RING_HEAD_ADDR = 0x%016"PRIx64,
+ fpga_reg_read_64(mmio_base, offset +
+ FPGA_5GNR_FEC_RING_HEAD_ADDR));
+ rte_bbdev_log_debug(
+ "RING_SIZE = 0x%04"PRIx16,
+ fpga_reg_read_16(mmio_base, offset +
+ FPGA_5GNR_FEC_RING_SIZE));
+ rte_bbdev_log_debug(
+ "RING_MISC = 0x%02"PRIx8,
+ fpga_reg_read_8(mmio_base, offset +
+ FPGA_5GNR_FEC_RING_MISC));
+ rte_bbdev_log_debug(
+ "RING_ENABLE = 0x%02"PRIx8,
+ fpga_reg_read_8(mmio_base, offset +
+ FPGA_5GNR_FEC_RING_ENABLE));
+ rte_bbdev_log_debug(
+ "RING_FLUSH_QUEUE_EN = 0x%02"PRIx8,
+ fpga_reg_read_8(mmio_base, offset +
+ FPGA_5GNR_FEC_RING_FLUSH_QUEUE_EN));
+ rte_bbdev_log_debug(
+ "RING_SHADOW_TAIL = 0x%04"PRIx16,
+ fpga_reg_read_16(mmio_base, offset +
+ FPGA_5GNR_FEC_RING_SHADOW_TAIL));
+ rte_bbdev_log_debug(
+ "RING_HEAD_POINT = 0x%04"PRIx16,
+ fpga_reg_read_16(mmio_base, offset +
+ FPGA_5GNR_FEC_RING_HEAD_POINT));
+}
+
+/* Read Static Register of FPGA 5GNR FEC device */
+static inline void
+print_static_reg_debug_info(void *mmio_base)
+{
+ uint16_t config = fpga_reg_read_16(mmio_base,
+ FPGA_5GNR_FEC_CONFIGURATION);
+ uint8_t qmap_done = fpga_reg_read_8(mmio_base,
+ FPGA_5GNR_FEC_QUEUE_PF_VF_MAP_DONE);
+ uint16_t lb_factor = fpga_reg_read_16(mmio_base,
+ FPGA_5GNR_FEC_LOAD_BALANCE_FACTOR);
+ uint16_t ring_desc_len = fpga_reg_read_16(mmio_base,
+ FPGA_5GNR_FEC_RING_DESC_LEN);
+ uint16_t flr_time_out = fpga_reg_read_16(mmio_base,
+ FPGA_5GNR_FEC_FLR_TIME_OUT);
+
+ rte_bbdev_log_debug("UL.DL Weights = %u.%u",
+ ((uint8_t)config), ((uint8_t)(config >> 8)));
+ rte_bbdev_log_debug("UL.DL Load Balance = %u.%u",
+ ((uint8_t)lb_factor), ((uint8_t)(lb_factor >> 8)));
+ rte_bbdev_log_debug("Queue-PF/VF Mapping Table = %s",
+ (qmap_done > 0) ? "READY" : "NOT-READY");
+ rte_bbdev_log_debug("Ring Descriptor Size = %u bytes",
+ ring_desc_len*FPGA_RING_DESC_LEN_UNIT_BYTES);
+ rte_bbdev_log_debug("FLR Timeout = %f usec",
+ (float)flr_time_out*FPGA_FLR_TIMEOUT_UNIT);
+}
+
+/* Print decode DMA Descriptor of FPGA 5GNR Decoder device */
+static void
+print_dma_dec_desc_debug_info(union fpga_dma_desc *desc)
+{
+ rte_bbdev_log_debug("DMA response desc %p\n"
+ "\t-- done(%"PRIu32") | iter(%"PRIu32") | et_pass(%"PRIu32")"
+ " | crcb_pass (%"PRIu32") | error(%"PRIu32")\n"
+ "\t-- qm_idx(%"PRIu32") | max_iter(%"PRIu32") | "
+ "bg_idx (%"PRIu32") | harqin_en(%"PRIu32") | zc(%"PRIu32")\n"
+ "\t-- hbstroe_offset(%"PRIu32") | num_null (%"PRIu32") "
+ "| irq_en(%"PRIu32")\n"
+ "\t-- ncb(%"PRIu32") | desc_idx (%"PRIu32") | "
+ "drop_crc24b(%"PRIu32") | RV (%"PRIu32")\n"
+ "\t-- crc24b_ind(%"PRIu32") | et_dis (%"PRIu32")\n"
+ "\t-- harq_input_length(%"PRIu32") | rm_e(%"PRIu32")\n"
+ "\t-- cbs_in_op(%"PRIu32") | in_add (0x%08"PRIx32"%08"PRIx32")"
+ "| out_add (0x%08"PRIx32"%08"PRIx32")",
+ desc,
+ (uint32_t)desc->dec_req.done,
+ (uint32_t)desc->dec_req.iter,
+ (uint32_t)desc->dec_req.et_pass,
+ (uint32_t)desc->dec_req.crcb_pass,
+ (uint32_t)desc->dec_req.error,
+ (uint32_t)desc->dec_req.qm_idx,
+ (uint32_t)desc->dec_req.max_iter,
+ (uint32_t)desc->dec_req.bg_idx,
+ (uint32_t)desc->dec_req.harqin_en,
+ (uint32_t)desc->dec_req.zc,
+ (uint32_t)desc->dec_req.hbstroe_offset,
+ (uint32_t)desc->dec_req.num_null,
+ (uint32_t)desc->dec_req.irq_en,
+ (uint32_t)desc->dec_req.ncb,
+ (uint32_t)desc->dec_req.desc_idx,
+ (uint32_t)desc->dec_req.drop_crc24b,
+ (uint32_t)desc->dec_req.rv,
+ (uint32_t)desc->dec_req.crc24b_ind,
+ (uint32_t)desc->dec_req.et_dis,
+ (uint32_t)desc->dec_req.harq_input_length,
+ (uint32_t)desc->dec_req.rm_e,
+ (uint32_t)desc->dec_req.cbs_in_op,
+ (uint32_t)desc->dec_req.in_addr_hi,
+ (uint32_t)desc->dec_req.in_addr_lw,
+ (uint32_t)desc->dec_req.out_addr_hi,
+ (uint32_t)desc->dec_req.out_addr_lw);
+ uint32_t *word = (uint32_t *) desc;
+ rte_bbdev_log_debug("%08"PRIx32"\n%08"PRIx32"\n%08"PRIx32"\n%08"PRIx32"\n"
+ "%08"PRIx32"\n%08"PRIx32"\n%08"PRIx32"\n%08"PRIx32"\n",
+ word[0], word[1], word[2], word[3],
+ word[4], word[5], word[6], word[7]);
+}
+
+/* Print decode DMA Descriptor of FPGA 5GNR encoder device */
+static void
+print_dma_enc_desc_debug_info(union fpga_dma_desc *desc)
+{
+ rte_bbdev_log_debug("DMA response desc %p\n"
+ "%"PRIu32" %"PRIu32"\n"
+ "K' %"PRIu32" E %"PRIu32" desc %"PRIu32" Z %"PRIu32"\n"
+ "BG %"PRIu32" Qm %"PRIu32" CRC %"PRIu32" IRQ %"PRIu32"\n"
+ "k0 %"PRIu32" Ncb %"PRIu32" F %"PRIu32"\n",
+ desc,
+ (uint32_t)desc->enc_req.done,
+ (uint32_t)desc->enc_req.error,
+
+ (uint32_t)desc->enc_req.k_,
+ (uint32_t)desc->enc_req.rm_e,
+ (uint32_t)desc->enc_req.desc_idx,
+ (uint32_t)desc->enc_req.zc,
+
+ (uint32_t)desc->enc_req.bg_idx,
+ (uint32_t)desc->enc_req.qm_idx,
+ (uint32_t)desc->enc_req.crc_en,
+ (uint32_t)desc->enc_req.irq_en,
+
+ (uint32_t)desc->enc_req.k0,
+ (uint32_t)desc->enc_req.ncb,
+ (uint32_t)desc->enc_req.num_null);
+ uint32_t *word = (uint32_t *) desc;
+ rte_bbdev_log_debug("%08"PRIx32"\n%08"PRIx32"\n%08"PRIx32"\n%08"PRIx32"\n"
+ "%08"PRIx32"\n%08"PRIx32"\n%08"PRIx32"\n%08"PRIx32"\n",
+ word[0], word[1], word[2], word[3],
+ word[4], word[5], word[6], word[7]);
+}
+
+#endif