+static int
+pci_dma_map(struct rte_device *dev, void *addr, uint64_t iova, size_t len)
+{
+ struct rte_pci_device *pdev = RTE_DEV_TO_PCI(dev);
+
+ if (!pdev || !pdev->driver) {
+ rte_errno = EINVAL;
+ return -1;
+ }
+ if (pdev->driver->dma_map)
+ return pdev->driver->dma_map(pdev, addr, iova, len);
+ /**
+ * In case driver don't provides any specific mapping
+ * try fallback to VFIO.
+ */
+ if (pdev->kdrv == RTE_PCI_KDRV_VFIO)
+ return rte_vfio_container_dma_map
+ (RTE_VFIO_DEFAULT_CONTAINER_FD, (uintptr_t)addr,
+ iova, len);
+ rte_errno = ENOTSUP;
+ return -1;
+}
+
+static int
+pci_dma_unmap(struct rte_device *dev, void *addr, uint64_t iova, size_t len)
+{
+ struct rte_pci_device *pdev = RTE_DEV_TO_PCI(dev);
+
+ if (!pdev || !pdev->driver) {
+ rte_errno = EINVAL;
+ return -1;
+ }
+ if (pdev->driver->dma_unmap)
+ return pdev->driver->dma_unmap(pdev, addr, iova, len);
+ /**
+ * In case driver don't provides any specific mapping
+ * try fallback to VFIO.
+ */
+ if (pdev->kdrv == RTE_PCI_KDRV_VFIO)
+ return rte_vfio_container_dma_unmap
+ (RTE_VFIO_DEFAULT_CONTAINER_FD, (uintptr_t)addr,
+ iova, len);
+ rte_errno = ENOTSUP;
+ return -1;
+}
+
+bool
+rte_pci_ignore_device(const struct rte_pci_addr *pci_addr)
+{
+ struct rte_devargs *devargs = pci_devargs_lookup(pci_addr);
+
+ switch (rte_pci_bus.bus.conf.scan_mode) {
+ case RTE_BUS_SCAN_ALLOWLIST:
+ if (devargs && devargs->policy == RTE_DEV_ALLOWED)
+ return false;
+ break;
+ case RTE_BUS_SCAN_UNDEFINED:
+ case RTE_BUS_SCAN_BLOCKLIST:
+ if (devargs == NULL || devargs->policy != RTE_DEV_BLOCKED)
+ return false;
+ break;
+ }
+ return true;
+}
+
+enum rte_iova_mode
+rte_pci_get_iommu_class(void)
+{
+ enum rte_iova_mode iova_mode = RTE_IOVA_DC;
+ const struct rte_pci_device *dev;
+ const struct rte_pci_driver *drv;
+ bool devices_want_va = false;
+ bool devices_want_pa = false;
+ int iommu_no_va = -1;
+
+ FOREACH_DEVICE_ON_PCIBUS(dev) {
+ /*
+ * We can check this only once, because the IOMMU hardware is
+ * the same for all of them.
+ */
+ if (iommu_no_va == -1)
+ iommu_no_va = pci_device_iommu_support_va(dev)
+ ? 0 : 1;
+
+ if (dev->kdrv == RTE_PCI_KDRV_UNKNOWN ||
+ dev->kdrv == RTE_PCI_KDRV_NONE)
+ continue;
+ FOREACH_DRIVER_ON_PCIBUS(drv) {
+ enum rte_iova_mode dev_iova_mode;
+
+ if (!rte_pci_match(drv, dev))
+ continue;
+
+ dev_iova_mode = pci_device_iova_mode(drv, dev);
+ RTE_LOG(DEBUG, EAL, "PCI driver %s for device "
+ PCI_PRI_FMT " wants IOVA as '%s'\n",
+ drv->driver.name,
+ dev->addr.domain, dev->addr.bus,
+ dev->addr.devid, dev->addr.function,
+ dev_iova_mode == RTE_IOVA_DC ? "DC" :
+ (dev_iova_mode == RTE_IOVA_PA ? "PA" : "VA"));
+ if (dev_iova_mode == RTE_IOVA_PA)
+ devices_want_pa = true;
+ else if (dev_iova_mode == RTE_IOVA_VA)
+ devices_want_va = true;
+ }
+ }
+ if (iommu_no_va == 1) {
+ iova_mode = RTE_IOVA_PA;
+ if (devices_want_va) {
+ RTE_LOG(WARNING, EAL, "Some devices want 'VA' but IOMMU does not support 'VA'.\n");
+ RTE_LOG(WARNING, EAL, "The devices that want 'VA' won't initialize.\n");
+ }
+ } else if (devices_want_va && !devices_want_pa) {
+ iova_mode = RTE_IOVA_VA;
+ } else if (devices_want_pa && !devices_want_va) {
+ iova_mode = RTE_IOVA_PA;
+ } else {
+ iova_mode = RTE_IOVA_DC;
+ if (devices_want_va) {
+ RTE_LOG(WARNING, EAL, "Some devices want 'VA' but forcing 'DC' because other devices want 'PA'.\n");
+ RTE_LOG(WARNING, EAL, "Depending on the final decision by the EAL, not all devices may be able to initialize.\n");
+ }
+ }
+ return iova_mode;
+}
+
+off_t
+rte_pci_find_ext_capability(struct rte_pci_device *dev, uint32_t cap)
+{
+ off_t offset = RTE_PCI_CFG_SPACE_SIZE;
+ uint32_t header;
+ int ttl;
+
+ /* minimum 8 bytes per capability */
+ ttl = (RTE_PCI_CFG_SPACE_EXP_SIZE - RTE_PCI_CFG_SPACE_SIZE) / 8;
+
+ if (rte_pci_read_config(dev, &header, 4, offset) < 0) {
+ RTE_LOG(ERR, EAL, "error in reading extended capabilities\n");
+ return -1;
+ }
+
+ /*
+ * If we have no capabilities, this is indicated by cap ID,
+ * cap version and next pointer all being 0.
+ */
+ if (header == 0)
+ return 0;
+
+ while (ttl != 0) {
+ if (RTE_PCI_EXT_CAP_ID(header) == cap)
+ return offset;
+
+ offset = RTE_PCI_EXT_CAP_NEXT(header);
+
+ if (offset < RTE_PCI_CFG_SPACE_SIZE)
+ break;
+
+ if (rte_pci_read_config(dev, &header, 4, offset) < 0) {
+ RTE_LOG(ERR, EAL,
+ "error in reading extended capabilities\n");
+ return -1;
+ }
+
+ ttl--;
+ }
+
+ return 0;
+}
+