- struct mlx5_devx_dbr_page *page;
-
- /* Allocate space for door-bell page and management data. */
- page = rte_calloc_socket(__func__, 1, sizeof(struct mlx5_devx_dbr_page),
- RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
- if (!page) {
- DRV_LOG(ERR, "cannot allocate dbr page");
- return NULL;
- }
- /* Register allocated memory. */
- page->umem = mlx5_glue->devx_umem_reg(ctx, page->dbrs,
- MLX5_DBR_PAGE_SIZE, 0);
- if (!page->umem) {
- DRV_LOG(ERR, "cannot umem reg dbr page");
- rte_free(page);
- return NULL;
- }
- return page;
-}
-
-/**
- * Find the next available door-bell, allocate new page if needed.
- *
- * @param [in] ctx
- * Pointer to device context.
- * @param [in] head
- * Pointer to the head of dbr pages list.
- * @param [out] dbr_page
- * Door-bell page containing the page data.
- *
- * @return
- * Door-bell address offset on success, a negative error value otherwise.
- */
-int64_t
-mlx5_get_dbr(void *ctx, struct mlx5_dbr_page_list *head,
- struct mlx5_devx_dbr_page **dbr_page)
-{
- struct mlx5_devx_dbr_page *page = NULL;
- uint32_t i, j;
-
- LIST_FOREACH(page, head, next)
- if (page->dbr_count < MLX5_DBR_PER_PAGE)
+ void *uar;
+ uint32_t retry, uar_mapping;
+ void *base_addr;
+
+ for (retry = 0; retry < MLX5_ALLOC_UAR_RETRY; ++retry) {
+#ifdef MLX5DV_UAR_ALLOC_TYPE_NC
+ /* Control the mapping type according to the settings. */
+ uar_mapping = (mapping < 0) ?
+ MLX5DV_UAR_ALLOC_TYPE_NC : mapping;
+#else
+ /*
+ * It seems we have no way to control the memory mapping type
+ * for the UAR, the default "Write-Combining" type is supposed.
+ */
+ uar_mapping = 0;
+ RTE_SET_USED(mapping);
+#endif
+ uar = mlx5_glue->devx_alloc_uar(ctx, uar_mapping);
+#ifdef MLX5DV_UAR_ALLOC_TYPE_NC
+ if (!uar &&
+ mapping < 0 &&
+ uar_mapping == MLX5DV_UAR_ALLOC_TYPE_BF) {
+ /*
+ * In some environments like virtual machine the
+ * Write Combining mapped might be not supported and
+ * UAR allocation fails. We tried "Non-Cached" mapping
+ * for the case.
+ */
+ DRV_LOG(WARNING, "Failed to allocate DevX UAR (BF)");
+ uar_mapping = MLX5DV_UAR_ALLOC_TYPE_NC;
+ uar = mlx5_glue->devx_alloc_uar(ctx, uar_mapping);
+ } else if (!uar &&
+ mapping < 0 &&
+ uar_mapping == MLX5DV_UAR_ALLOC_TYPE_NC) {
+ /*
+ * If Verbs/kernel does not support "Non-Cached"
+ * try the "Write-Combining".
+ */
+ DRV_LOG(WARNING, "Failed to allocate DevX UAR (NC)");
+ uar_mapping = MLX5DV_UAR_ALLOC_TYPE_BF;
+ uar = mlx5_glue->devx_alloc_uar(ctx, uar_mapping);
+ }
+#endif
+ if (!uar) {
+ DRV_LOG(ERR, "Failed to allocate DevX UAR (BF/NC)");
+ rte_errno = ENOMEM;
+ goto exit;
+ }
+ base_addr = mlx5_os_get_devx_uar_base_addr(uar);
+ if (base_addr)