+/**
+ * Allocate the User Access Region with DevX on specified device.
+ *
+ * @param [in] ctx
+ * Infiniband device context to perform allocation on.
+ * @param [in] mapping
+ * MLX5DV_UAR_ALLOC_TYPE_BF - allocate as cached memory with write-combining
+ * attributes (if supported by the host), the
+ * writes to the UAR registers must be followed
+ * by write memory barrier.
+ * MLX5DV_UAR_ALLOC_TYPE_NC - allocate as non-cached nenory, all writes are
+ * promoted to the registers immediately, no
+ * memory barriers needed.
+ * mapping < 0 - the first attempt is performed with MLX5DV_UAR_ALLOC_TYPE_BF,
+ * if this fails the next attempt with MLX5DV_UAR_ALLOC_TYPE_NC
+ * is performed. The drivers specifying negative values should
+ * always provide the write memory barrier operation after UAR
+ * register writings.
+ * If there is no definitions for the MLX5DV_UAR_ALLOC_TYPE_xx (older rdma
+ * library headers), the caller can specify 0.
+ *
+ * @return
+ * UAR object pointer on success, NULL otherwise and rte_errno is set.
+ */
+void *
+mlx5_devx_alloc_uar(void *ctx, int mapping)
+{
+ void *uar;
+ uint32_t retry, uar_mapping;
+ void *base_addr;
+
+ for (retry = 0; retry < MLX5_ALLOC_UAR_RETRY; ++retry) {
+#ifdef MLX5DV_UAR_ALLOC_TYPE_NC
+ /* Control the mapping type according to the settings. */
+ uar_mapping = (mapping < 0) ?
+ MLX5DV_UAR_ALLOC_TYPE_NC : mapping;
+#else
+ /*
+ * It seems we have no way to control the memory mapping type
+ * for the UAR, the default "Write-Combining" type is supposed.
+ */
+ uar_mapping = 0;
+ RTE_SET_USED(mapping);