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common/mlx5/linux: replace malloc and free in glue
[dpdk.git]
/
drivers
/
common
/
mlx5
/
mlx5_devx_cmds.h
diff --git
a/drivers/common/mlx5/mlx5_devx_cmds.h
b/drivers/common/mlx5/mlx5_devx_cmds.h
index
ab61454
..
472d1cb
100644
(file)
--- a/
drivers/common/mlx5/mlx5_devx_cmds.h
+++ b/
drivers/common/mlx5/mlx5_devx_cmds.h
@@
-85,6
+85,7
@@
struct mlx5_hca_attr {
uint32_t tunnel_lro_vxlan:1;
uint32_t lro_max_msg_sz_mode:2;
uint32_t lro_timer_supported_periods[MLX5_LRO_NUM_SUPP_PERIODS];
uint32_t tunnel_lro_vxlan:1;
uint32_t lro_max_msg_sz_mode:2;
uint32_t lro_timer_supported_periods[MLX5_LRO_NUM_SUPP_PERIODS];
+ uint16_t lro_min_mss_size;
uint32_t flex_parser_protocols;
uint32_t hairpin:1;
uint32_t log_max_hairpin_queues:5;
uint32_t flex_parser_protocols;
uint32_t hairpin:1;
uint32_t log_max_hairpin_queues:5;
@@
-93,14
+94,17
@@
struct mlx5_hca_attr {
uint32_t vhca_id:16;
uint32_t relaxed_ordering_write:1;
uint32_t relaxed_ordering_read:1;
uint32_t vhca_id:16;
uint32_t relaxed_ordering_write:1;
uint32_t relaxed_ordering_read:1;
+ uint32_t access_register_user:1;
uint32_t wqe_index_ignore:1;
uint32_t cross_channel:1;
uint32_t non_wire_sq:1; /* SQ with non-wire ops is supported. */
uint32_t log_max_static_sq_wq:5; /* Static WQE size SQ. */
uint32_t wqe_index_ignore:1;
uint32_t cross_channel:1;
uint32_t non_wire_sq:1; /* SQ with non-wire ops is supported. */
uint32_t log_max_static_sq_wq:5; /* Static WQE size SQ. */
+ uint32_t num_lag_ports:4; /* Number of ports can be bonded. */
uint32_t dev_freq_khz; /* Timestamp counter frequency, kHz. */
uint32_t scatter_fcs_w_decap_disable:1;
uint32_t regex:1;
uint32_t regexp_num_of_engines;
uint32_t dev_freq_khz; /* Timestamp counter frequency, kHz. */
uint32_t scatter_fcs_w_decap_disable:1;
uint32_t regex:1;
uint32_t regexp_num_of_engines;
+ uint32_t log_max_ft_sampler_num:8;
struct mlx5_hca_qos_attr qos;
struct mlx5_hca_vdpa_attr vdpa;
};
struct mlx5_hca_qos_attr qos;
struct mlx5_hca_vdpa_attr vdpa;
};
@@
-189,6
+193,13
@@
struct mlx5_devx_tir_attr {
struct mlx5_rx_hash_field_select rx_hash_field_selector_inner;
};
struct mlx5_rx_hash_field_select rx_hash_field_selector_inner;
};
+/* TIR attributes structure, used by TIR modify. */
+struct mlx5_devx_modify_tir_attr {
+ uint32_t tirn:24;
+ uint64_t modify_bitmask;
+ struct mlx5_devx_tir_attr tir;
+};
+
/* RQT attributes structure, used by RQT operations. */
struct mlx5_devx_rqt_attr {
uint8_t rq_type;
/* RQT attributes structure, used by RQT operations. */
struct mlx5_devx_rqt_attr {
uint8_t rq_type;
@@
-243,6
+254,8
@@
struct mlx5_devx_cq_attr {
uint32_t db_umem_valid:1;
uint32_t use_first_only:1;
uint32_t overrun_ignore:1;
uint32_t db_umem_valid:1;
uint32_t use_first_only:1;
uint32_t overrun_ignore:1;
+ uint32_t cqe_comp_en:1;
+ uint32_t mini_cqe_res_format:2;
uint32_t cqe_size:3;
uint32_t log_cq_size:5;
uint32_t log_page_size:5;
uint32_t cqe_size:3;
uint32_t log_cq_size:5;
uint32_t log_page_size:5;
@@
-286,6
+299,7
@@
struct mlx5_devx_virtq_attr {
uint32_t size;
uint64_t offset;
} umems[3];
uint32_t size;
uint64_t offset;
} umems[3];
+ uint8_t error_type;
};
};
@@
-431,6
+445,9
@@
__rte_internal
int mlx5_devx_cmd_modify_rqt(struct mlx5_devx_obj *rqt,
struct mlx5_devx_rqt_attr *rqt_attr);
__rte_internal
int mlx5_devx_cmd_modify_rqt(struct mlx5_devx_obj *rqt,
struct mlx5_devx_rqt_attr *rqt_attr);
__rte_internal
+int mlx5_devx_cmd_modify_tir(struct mlx5_devx_obj *tir,
+ struct mlx5_devx_modify_tir_attr *tir_attr);
+__rte_internal
int mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj,
uint32_t ids[], uint32_t num);
int mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj,
uint32_t ids[], uint32_t num);