+
+/* CQ attributes structure, used by CQ operations. */
+struct mlx5_devx_cq_attr {
+ uint32_t q_umem_valid:1;
+ uint32_t db_umem_valid:1;
+ uint32_t use_first_only:1;
+ uint32_t overrun_ignore:1;
+ uint32_t cqe_comp_en:1;
+ uint32_t mini_cqe_res_format:2;
+ uint32_t cqe_size:3;
+ uint32_t log_cq_size:5;
+ uint32_t log_page_size:5;
+ uint32_t uar_page_id;
+ uint32_t q_umem_id;
+ uint64_t q_umem_offset;
+ uint32_t db_umem_id;
+ uint64_t db_umem_offset;
+ uint32_t eqn;
+ uint64_t db_addr;
+};
+
+/* Virtq attributes structure, used by VIRTQ operations. */
+struct mlx5_devx_virtq_attr {
+ uint16_t hw_available_index;
+ uint16_t hw_used_index;
+ uint16_t q_size;
+ uint32_t pd:24;
+ uint32_t virtio_version_1_0:1;
+ uint32_t tso_ipv4:1;
+ uint32_t tso_ipv6:1;
+ uint32_t tx_csum:1;
+ uint32_t rx_csum:1;
+ uint32_t event_mode:3;
+ uint32_t state:4;
+ uint32_t dirty_bitmap_dump_enable:1;
+ uint32_t dirty_bitmap_mkey;
+ uint32_t dirty_bitmap_size;
+ uint32_t mkey;
+ uint32_t qp_id;
+ uint32_t queue_index;
+ uint32_t tis_id;
+ uint32_t counters_obj_id;
+ uint64_t dirty_bitmap_addr;
+ uint64_t type;
+ uint64_t desc_addr;
+ uint64_t used_addr;
+ uint64_t available_addr;
+ struct {
+ uint32_t id;
+ uint32_t size;
+ uint64_t offset;
+ } umems[3];
+};
+
+
+struct mlx5_devx_qp_attr {
+ uint32_t pd:24;
+ uint32_t uar_index:24;
+ uint32_t cqn:24;
+ uint32_t log_page_size:5;
+ uint32_t rq_size:17; /* Must be power of 2. */
+ uint32_t log_rq_stride:3;
+ uint32_t sq_size:17; /* Must be power of 2. */
+ uint32_t dbr_umem_valid:1;
+ uint32_t dbr_umem_id;
+ uint64_t dbr_address;
+ uint32_t wq_umem_id;
+ uint64_t wq_umem_offset;
+};
+
+struct mlx5_devx_virtio_q_couners_attr {
+ uint64_t received_desc;
+ uint64_t completed_desc;
+ uint32_t error_cqes;
+ uint32_t bad_desc_errors;
+ uint32_t exceed_max_chain;
+ uint32_t invalid_buffer;
+};
+
+/*
+ * graph flow match sample attributes structure,
+ * used by flex parser operations.
+ */
+struct mlx5_devx_match_sample_attr {
+ uint32_t flow_match_sample_en:1;
+ uint32_t flow_match_sample_field_offset:16;
+ uint32_t flow_match_sample_offset_mode:4;
+ uint32_t flow_match_sample_field_offset_mask;
+ uint32_t flow_match_sample_field_offset_shift:4;
+ uint32_t flow_match_sample_field_base_offset:8;
+ uint32_t flow_match_sample_tunnel_mode:3;
+ uint32_t flow_match_sample_field_id;
+};
+
+/* graph node arc attributes structure, used by flex parser operations. */
+struct mlx5_devx_graph_arc_attr {
+ uint32_t compare_condition_value:16;
+ uint32_t start_inner_tunnel:1;
+ uint32_t arc_parse_graph_node:8;
+ uint32_t parse_graph_node_handle;
+};
+
+/* Maximal number of samples per graph node. */
+#define MLX5_GRAPH_NODE_SAMPLE_NUM 8
+
+/* Maximal number of input/output arcs per graph node. */
+#define MLX5_GRAPH_NODE_ARC_NUM 8
+
+/* parse graph node attributes structure, used by flex parser operations. */
+struct mlx5_devx_graph_node_attr {
+ uint32_t modify_field_select;
+ uint32_t header_length_mode:4;
+ uint32_t header_length_base_value:16;
+ uint32_t header_length_field_shift:4;
+ uint32_t header_length_field_offset:16;
+ uint32_t header_length_field_mask;
+ struct mlx5_devx_match_sample_attr sample[MLX5_GRAPH_NODE_SAMPLE_NUM];
+ uint32_t next_header_field_offset:16;
+ uint32_t next_header_field_size:5;
+ struct mlx5_devx_graph_arc_attr in[MLX5_GRAPH_NODE_ARC_NUM];
+ struct mlx5_devx_graph_arc_attr out[MLX5_GRAPH_NODE_ARC_NUM];
+};
+