+enum {
+ MLX5_DATA_RATE = 0x0,
+ MLX5_WQE_RATE = 0x1,
+};
+
+struct mlx5_ifc_set_pp_rate_limit_context_bits {
+ u8 rate_limit[0x20];
+ u8 burst_upper_bound[0x20];
+ u8 reserved_at_40[0xC];
+ u8 rate_mode[0x4];
+ u8 typical_packet_size[0x10];
+ u8 reserved_at_60[0x120];
+};
+
+#define MLX5_ACCESS_REGISTER_DATA_DWORD_MAX 8u
+
+#ifdef PEDANTIC
+#pragma GCC diagnostic ignored "-Wpedantic"
+#endif
+struct mlx5_ifc_access_register_out_bits {
+ u8 status[0x8];
+ u8 reserved_at_8[0x18];
+ u8 syndrome[0x20];
+ u8 reserved_at_40[0x40];
+ u8 register_data[0][0x20];
+};
+
+struct mlx5_ifc_access_register_in_bits {
+ u8 opcode[0x10];
+ u8 reserved_at_10[0x10];
+ u8 reserved_at_20[0x10];
+ u8 op_mod[0x10];
+ u8 reserved_at_40[0x10];
+ u8 register_id[0x10];
+ u8 argument[0x20];
+ u8 register_data[0][0x20];
+};
+#ifdef PEDANTIC
+#pragma GCC diagnostic error "-Wpedantic"
+#endif
+
+enum {
+ MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0,
+ MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1,
+};
+
+enum {
+ MLX5_REGISTER_ID_MTUTC = 0x9055,
+ MLX5_CRYPTO_OPERATIONAL_REGISTER_ID = 0xC002,
+ MLX5_CRYPTO_COMMISSIONING_REGISTER_ID = 0xC003,
+ MLX5_IMPORT_KEK_HANDLE_REGISTER_ID = 0xC004,
+ MLX5_CREDENTIAL_HANDLE_REGISTER_ID = 0xC005,
+};
+
+struct mlx5_ifc_register_mtutc_bits {
+ u8 time_stamp_mode[0x2];
+ u8 time_stamp_state[0x2];
+ u8 reserved_at_4[0x18];
+ u8 operation[0x4];
+ u8 freq_adjustment[0x20];
+ u8 reserved_at_40[0x40];
+ u8 utc_sec[0x20];
+ u8 utc_nsec[0x20];
+ u8 time_adjustment[0x20];
+};
+
+#define MLX5_MTUTC_TIMESTAMP_MODE_INTERNAL_TIMER 0
+#define MLX5_MTUTC_TIMESTAMP_MODE_REAL_TIME 1
+
+struct mlx5_ifc_crypto_operational_register_bits {
+ u8 wrapped_crypto_operational[0x1];
+ u8 reserved_at_1[0x1b];
+ u8 kek_size[0x4];
+ u8 reserved_at_20[0x20];
+ u8 credential[0x140];
+ u8 kek[0x100];
+ u8 reserved_at_280[0x180];
+};
+
+struct mlx5_ifc_crypto_commissioning_register_bits {
+ u8 token[0x1]; /* TODO: add size after PRM update */
+};
+
+struct mlx5_ifc_import_kek_handle_register_bits {
+ struct mlx5_ifc_crypto_login_bits crypto_login_object;
+ struct mlx5_ifc_import_kek_bits import_kek_object;
+ u8 reserved_at_200[0x4];
+ u8 write_operation[0x4];
+ u8 import_kek_id[0x18];
+ u8 reserved_at_220[0xe0];
+};
+
+struct mlx5_ifc_credential_handle_register_bits {
+ struct mlx5_ifc_crypto_login_bits crypto_login_object;
+ struct mlx5_ifc_credential_bits credential_object;
+ u8 reserved_at_200[0x4];
+ u8 write_operation[0x4];
+ u8 credential_id[0x18];
+ u8 reserved_at_220[0xe0];
+};
+
+enum {
+ MLX5_REGISTER_ADD_OPERATION = 0x1,
+ MLX5_REGISTER_DELETE_OPERATION = 0x2,
+};
+
+struct mlx5_ifc_parse_graph_arc_bits {
+ u8 start_inner_tunnel[0x1];
+ u8 reserved_at_1[0x7];
+ u8 arc_parse_graph_node[0x8];
+ u8 compare_condition_value[0x10];
+ u8 parse_graph_node_handle[0x20];
+ u8 reserved_at_40[0x40];
+};
+
+struct mlx5_ifc_parse_graph_flow_match_sample_bits {
+ u8 flow_match_sample_en[0x1];
+ u8 reserved_at_1[0x3];
+ u8 flow_match_sample_offset_mode[0x4];
+ u8 reserved_at_5[0x8];
+ u8 flow_match_sample_field_offset[0x10];
+ u8 reserved_at_32[0x4];
+ u8 flow_match_sample_field_offset_shift[0x4];
+ u8 flow_match_sample_field_base_offset[0x8];
+ u8 reserved_at_48[0xd];
+ u8 flow_match_sample_tunnel_mode[0x3];
+ u8 flow_match_sample_field_offset_mask[0x20];
+ u8 flow_match_sample_field_id[0x20];
+};
+
+struct mlx5_ifc_parse_graph_flex_bits {
+ u8 modify_field_select[0x40];
+ u8 reserved_at_64[0x20];
+ u8 header_length_base_value[0x10];
+ u8 reserved_at_112[0x4];
+ u8 header_length_field_shift[0x4];
+ u8 reserved_at_120[0x4];
+ u8 header_length_mode[0x4];
+ u8 header_length_field_offset[0x10];
+ u8 next_header_field_offset[0x10];
+ u8 reserved_at_160[0x1b];
+ u8 next_header_field_size[0x5];
+ u8 header_length_field_mask[0x20];
+ u8 reserved_at_224[0x20];
+ struct mlx5_ifc_parse_graph_flow_match_sample_bits sample_table[0x8];
+ struct mlx5_ifc_parse_graph_arc_bits input_arc[0x8];
+ struct mlx5_ifc_parse_graph_arc_bits output_arc[0x8];
+};
+
+struct mlx5_ifc_create_flex_parser_in_bits {
+ struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
+ struct mlx5_ifc_parse_graph_flex_bits flex;
+};
+
+struct mlx5_ifc_create_flex_parser_out_bits {
+ struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
+ struct mlx5_ifc_parse_graph_flex_bits flex;
+};
+
+struct mlx5_ifc_parse_graph_flex_out_bits {
+ u8 status[0x8];
+ u8 reserved_at_8[0x18];
+ u8 syndrome[0x20];
+ u8 reserved_at_40[0x40];
+ struct mlx5_ifc_parse_graph_flex_bits capability;
+};
+
+struct regexp_params_field_select_bits {
+ u8 reserved_at_0[0x1e];
+ u8 stop_engine[0x1];
+ u8 db_umem_id[0x1];
+};
+
+struct mlx5_ifc_regexp_params_bits {
+ u8 reserved_at_0[0x1f];
+ u8 stop_engine[0x1];
+ u8 db_umem_id[0x20];
+ u8 db_umem_offset[0x40];
+ u8 reserved_at_80[0x100];
+};
+
+struct mlx5_ifc_set_regexp_params_in_bits {
+ u8 opcode[0x10];
+ u8 uid[0x10];
+ u8 reserved_at_20[0x10];
+ u8 op_mod[0x10];
+ u8 reserved_at_40[0x18];
+ u8 engine_id[0x8];
+ struct regexp_params_field_select_bits field_select;
+ struct mlx5_ifc_regexp_params_bits regexp_params;
+};
+
+struct mlx5_ifc_set_regexp_params_out_bits {
+ u8 status[0x8];
+ u8 reserved_at_8[0x18];
+ u8 syndrome[0x20];
+ u8 reserved_at_18[0x40];
+};
+
+struct mlx5_ifc_query_regexp_params_in_bits {
+ u8 opcode[0x10];
+ u8 uid[0x10];
+ u8 reserved_at_20[0x10];
+ u8 op_mod[0x10];
+ u8 reserved_at_40[0x18];
+ u8 engine_id[0x8];
+ u8 reserved[0x20];
+};
+
+struct mlx5_ifc_query_regexp_params_out_bits {
+ u8 status[0x8];
+ u8 reserved_at_8[0x18];
+ u8 syndrome[0x20];
+ u8 reserved[0x40];
+ struct mlx5_ifc_regexp_params_bits regexp_params;
+};
+
+struct mlx5_ifc_set_regexp_register_in_bits {
+ u8 opcode[0x10];
+ u8 uid[0x10];
+ u8 reserved_at_20[0x10];
+ u8 op_mod[0x10];
+ u8 reserved_at_40[0x18];
+ u8 engine_id[0x8];
+ u8 register_address[0x20];
+ u8 register_data[0x20];
+ u8 reserved[0x60];
+};
+
+struct mlx5_ifc_set_regexp_register_out_bits {
+ u8 status[0x8];
+ u8 reserved_at_8[0x18];
+ u8 syndrome[0x20];
+ u8 reserved[0x40];
+};
+
+struct mlx5_ifc_query_regexp_register_in_bits {
+ u8 opcode[0x10];
+ u8 uid[0x10];
+ u8 reserved_at_20[0x10];
+ u8 op_mod[0x10];
+ u8 reserved_at_40[0x18];
+ u8 engine_id[0x8];
+ u8 register_address[0x20];
+};
+
+struct mlx5_ifc_query_regexp_register_out_bits {
+ u8 status[0x8];
+ u8 reserved_at_8[0x18];
+ u8 syndrome[0x20];
+ u8 reserved[0x20];
+ u8 register_data[0x20];
+};
+
+/* Queue counters. */
+struct mlx5_ifc_alloc_q_counter_out_bits {
+ u8 status[0x8];
+ u8 reserved_at_8[0x18];
+ u8 syndrome[0x20];
+ u8 reserved_at_40[0x18];
+ u8 counter_set_id[0x8];
+ u8 reserved_at_60[0x20];
+};
+
+struct mlx5_ifc_alloc_q_counter_in_bits {
+ u8 opcode[0x10];
+ u8 uid[0x10];
+ u8 reserved_at_20[0x10];
+ u8 op_mod[0x10];
+ u8 reserved_at_40[0x40];
+};
+
+struct mlx5_ifc_query_q_counter_out_bits {
+ u8 status[0x8];
+ u8 reserved_at_8[0x18];
+ u8 syndrome[0x20];
+ u8 reserved_at_40[0x40];
+ u8 rx_write_requests[0x20];
+ u8 reserved_at_a0[0x20];
+ u8 rx_read_requests[0x20];
+ u8 reserved_at_e0[0x20];
+ u8 rx_atomic_requests[0x20];
+ u8 reserved_at_120[0x20];
+ u8 rx_dct_connect[0x20];
+ u8 reserved_at_160[0x20];
+ u8 out_of_buffer[0x20];
+ u8 reserved_at_1a0[0x20];
+ u8 out_of_sequence[0x20];
+ u8 reserved_at_1e0[0x20];
+ u8 duplicate_request[0x20];
+ u8 reserved_at_220[0x20];
+ u8 rnr_nak_retry_err[0x20];
+ u8 reserved_at_260[0x20];
+ u8 packet_seq_err[0x20];
+ u8 reserved_at_2a0[0x20];
+ u8 implied_nak_seq_err[0x20];
+ u8 reserved_at_2e0[0x20];
+ u8 local_ack_timeout_err[0x20];
+ u8 reserved_at_320[0xa0];
+ u8 resp_local_length_error[0x20];
+ u8 req_local_length_error[0x20];
+ u8 resp_local_qp_error[0x20];
+ u8 local_operation_error[0x20];
+ u8 resp_local_protection[0x20];
+ u8 req_local_protection[0x20];
+ u8 resp_cqe_error[0x20];
+ u8 req_cqe_error[0x20];
+ u8 req_mw_binding[0x20];
+ u8 req_bad_response[0x20];
+ u8 req_remote_invalid_request[0x20];
+ u8 resp_remote_invalid_request[0x20];
+ u8 req_remote_access_errors[0x20];
+ u8 resp_remote_access_errors[0x20];
+ u8 req_remote_operation_errors[0x20];
+ u8 req_transport_retries_exceeded[0x20];
+ u8 cq_overflow[0x20];
+ u8 resp_cqe_flush_error[0x20];
+ u8 req_cqe_flush_error[0x20];
+ u8 reserved_at_620[0x1e0];
+};
+
+struct mlx5_ifc_query_q_counter_in_bits {
+ u8 opcode[0x10];
+ u8 uid[0x10];
+ u8 reserved_at_20[0x10];
+ u8 op_mod[0x10];
+ u8 reserved_at_40[0x80];
+ u8 clear[0x1];
+ u8 reserved_at_c1[0x1f];
+ u8 reserved_at_e0[0x18];
+ u8 counter_set_id[0x8];
+};
+