+struct mlx5_ifc_flow_hit_aso_bits {
+ u8 modify_field_select[0x40];
+ u8 reserved_at_40[0x48];
+ u8 access_pd[0x18];
+ u8 reserved_at_a0[0x160];
+ u8 flag[0x200];
+};
+
+struct mlx5_ifc_create_flow_hit_aso_in_bits {
+ struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
+ struct mlx5_ifc_flow_hit_aso_bits flow_hit_aso;
+};
+
+struct mlx5_ifc_flow_meter_aso_bits {
+ u8 modify_field_select[0x40];
+ u8 reserved_at_40[0x48];
+ u8 access_pd[0x18];
+ u8 reserved_at_a0[0x160];
+ u8 parameters[0x200];
+};
+
+struct mlx5_ifc_create_flow_meter_aso_in_bits {
+ struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
+ struct mlx5_ifc_flow_meter_aso_bits flow_meter_aso;
+};
+
+struct mlx5_ifc_tcp_window_params_bits {
+ u8 max_ack[0x20];
+ u8 max_win[0x20];
+ u8 reply_end[0x20];
+ u8 sent_end[0x20];
+};
+
+struct mlx5_ifc_conn_track_aso_bits {
+ struct mlx5_ifc_tcp_window_params_bits reply_dir; /* End of DW3. */
+ struct mlx5_ifc_tcp_window_params_bits original_dir; /* End of DW7. */
+ u8 last_end[0x20]; /* End of DW8. */
+ u8 last_ack[0x20]; /* End of DW9. */
+ u8 last_seq[0x20]; /* End of DW10. */
+ u8 last_win[0x10];
+ u8 reserved_at_170[0xa];
+ u8 last_dir[0x1];
+ u8 last_index[0x5]; /* End of DW11. */
+ u8 reserved_at_180[0x40]; /* End of DW13. */
+ u8 reply_direction_tcp_scale[0x4];
+ u8 reply_direction_tcp_close_initiated[0x1];
+ u8 reply_direction_tcp_liberal_enabled[0x1];
+ u8 reply_direction_tcp_data_unacked[0x1];
+ u8 reply_direction_tcp_max_ack[0x1];
+ u8 reserved_at_1c8[0x8];
+ u8 original_direction_tcp_scale[0x4];
+ u8 original_direction_tcp_close_initiated[0x1];
+ u8 original_direction_tcp_liberal_enabled[0x1];
+ u8 original_direction_tcp_data_unacked[0x1];
+ u8 original_direction_tcp_max_ack[0x1];
+ u8 reserved_at_1d8[0x8]; /* End of DW14. */
+ u8 valid[0x1];
+ u8 state[0x3];
+ u8 freeze_track[0x1];
+ u8 reserved_at_1e5[0xb];
+ u8 reserved_at_1f0[0x1];
+ u8 connection_assured[0x1];
+ u8 sack_permitted[0x1];
+ u8 challenged_acked[0x1];
+ u8 heartbeat[0x1];
+ u8 max_ack_window[0x3];
+ u8 reserved_at_1f8[0x1];
+ u8 retransmission_counter[0x3];
+ u8 retranmission_limit_exceeded[0x1];
+ u8 retranmission_limit[0x3]; /* End of DW15. */
+};
+
+struct mlx5_ifc_conn_track_offload_bits {
+ u8 modify_field_select[0x40];
+ u8 reserved_at_40[0x40];
+ u8 reserved_at_80[0x8];
+ u8 conn_track_aso_access_pd[0x18];
+ u8 reserved_at_a0[0x160];
+ struct mlx5_ifc_conn_track_aso_bits conn_track_aso;
+};
+
+struct mlx5_ifc_create_conn_track_aso_in_bits {
+ struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
+ struct mlx5_ifc_conn_track_offload_bits conn_track_offload;
+};
+
+enum mlx5_access_aso_opc_mod {
+ ASO_OPC_MOD_IPSEC = 0x0,
+ ASO_OPC_MOD_CONNECTION_TRACKING = 0x1,
+ ASO_OPC_MOD_POLICER = 0x2,
+ ASO_OPC_MOD_RACE_AVOIDANCE = 0x3,
+ ASO_OPC_MOD_FLOW_HIT = 0x4,
+};
+
+#define ASO_CSEG_DATA_MASK_MODE_OFFSET 30
+
+enum mlx5_aso_data_mask_mode {
+ BITWISE_64BIT = 0x0,
+ BYTEWISE_64BYTE = 0x1,
+ CALCULATED_64BYTE = 0x2,
+};
+
+#define ASO_CSEG_COND_0_OPER_OFFSET 20
+#define ASO_CSEG_COND_1_OPER_OFFSET 16
+
+enum mlx5_aso_pre_cond_op {
+ ASO_OP_ALWAYS_FALSE = 0x0,
+ ASO_OP_ALWAYS_TRUE = 0x1,
+ ASO_OP_EQUAL = 0x2,
+ ASO_OP_NOT_EQUAL = 0x3,
+ ASO_OP_GREATER_OR_EQUAL = 0x4,
+ ASO_OP_LESSER_OR_EQUAL = 0x5,
+ ASO_OP_LESSER = 0x6,
+ ASO_OP_GREATER = 0x7,
+ ASO_OP_CYCLIC_GREATER = 0x8,
+ ASO_OP_CYCLIC_LESSER = 0x9,
+};
+
+#define ASO_CSEG_COND_OPER_OFFSET 6
+
+enum mlx5_aso_op {
+ ASO_OPER_LOGICAL_AND = 0x0,
+ ASO_OPER_LOGICAL_OR = 0x1,
+};
+
+/* ASO WQE CTRL segment. */
+struct mlx5_aso_cseg {
+ uint32_t va_h;
+ uint32_t va_l_r;
+ uint32_t lkey;
+ uint32_t operand_masks;
+ uint32_t condition_0_data;
+ uint32_t condition_0_mask;
+ uint32_t condition_1_data;
+ uint32_t condition_1_mask;
+ uint64_t bitwise_data;
+ uint64_t data_mask;
+} __rte_packed;
+
+/* A meter data segment - 2 per ASO WQE. */
+struct mlx5_aso_mtr_dseg {
+ uint32_t v_bo_sc_bbog_mm;
+ /*
+ * bit 31: valid, 30: bucket overflow, 28-29: start color,
+ * 27: both buckets on green, 24-25: meter mode.
+ */
+ uint32_t reserved;
+ uint32_t cbs_cir;
+ /*
+ * bit 24-28: cbs_exponent, bit 16-23 cbs_mantissa,
+ * bit 8-12: cir_exponent, bit 0-7 cir_mantissa.
+ */
+ uint32_t c_tokens;
+ uint32_t ebs_eir;
+ /*
+ * bit 24-28: ebs_exponent, bit 16-23 ebs_mantissa,
+ * bit 8-12: eir_exponent, bit 0-7 eir_mantissa.
+ */
+ uint32_t e_tokens;
+ uint64_t timestamp;
+} __rte_packed;
+
+#define ASO_DSEG_VALID_OFFSET 31
+#define ASO_DSEG_BO_OFFSET 30
+#define ASO_DSEG_SC_OFFSET 28
+#define ASO_DSEG_BBOG_OFFSET 27
+#define ASO_DSEG_MTR_MODE 24
+#define ASO_DSEG_CBS_EXP_OFFSET 24
+#define ASO_DSEG_CBS_MAN_OFFSET 16
+#define ASO_DSEG_XIR_EXP_MASK 0x1F
+#define ASO_DSEG_XIR_EXP_OFFSET 8
+#define ASO_DSEG_EBS_EXP_OFFSET 24
+#define ASO_DSEG_EBS_MAN_OFFSET 16
+#define ASO_DSEG_EXP_MASK 0x1F
+#define ASO_DSEG_MAN_MASK 0xFF
+
+#define MLX5_ASO_WQE_DSEG_SIZE 0x40
+#define MLX5_ASO_METERS_PER_WQE 2
+#define MLX5_ASO_MTRS_PER_POOL 128
+
+/* ASO WQE data segment. */
+struct mlx5_aso_dseg {
+ union {
+ uint8_t data[MLX5_ASO_WQE_DSEG_SIZE];
+ struct mlx5_aso_mtr_dseg mtrs[MLX5_ASO_METERS_PER_WQE];
+ };
+} __rte_packed;
+
+/* ASO WQE. */
+struct mlx5_aso_wqe {
+ struct mlx5_wqe_cseg general_cseg;
+ struct mlx5_aso_cseg aso_cseg;
+ struct mlx5_aso_dseg aso_dseg;
+} __rte_packed;
+
+enum {
+ MLX5_EVENT_TYPE_OBJECT_CHANGE = 0x27,
+};
+