+struct mlx5_ifc_sqc_bits {
+ u8 rlky[0x1];
+ u8 cd_master[0x1];
+ u8 fre[0x1];
+ u8 flush_in_error_en[0x1];
+ u8 allow_multi_pkt_send_wqe[0x1];
+ u8 min_wqe_inline_mode[0x3];
+ u8 state[0x4];
+ u8 reg_umr[0x1];
+ u8 allow_swp[0x1];
+ u8 hairpin[0x1];
+ u8 non_wire[0x1];
+ u8 static_sq_wq[0x1];
+ u8 reserved_at_11[0x9];
+ u8 ts_format[0x02];
+ u8 reserved_at_1c[0x4];
+ u8 reserved_at_20[0x8];
+ u8 user_index[0x18];
+ u8 reserved_at_40[0x8];
+ u8 cqn[0x18];
+ u8 reserved_at_60[0x8];
+ u8 hairpin_peer_rq[0x18];
+ u8 reserved_at_80[0x10];
+ u8 hairpin_peer_vhca[0x10];
+ u8 reserved_at_a0[0x50];
+ u8 packet_pacing_rate_limit_index[0x10];
+ u8 tis_lst_sz[0x10];
+ u8 reserved_at_110[0x10];
+ u8 reserved_at_120[0x40];
+ u8 reserved_at_160[0x8];
+ u8 tis_num_0[0x18];
+ struct mlx5_ifc_wq_bits wq;
+};
+
+struct mlx5_ifc_query_sq_in_bits {
+ u8 opcode[0x10];
+ u8 reserved_at_10[0x10];
+ u8 reserved_at_20[0x10];
+ u8 op_mod[0x10];
+ u8 reserved_at_40[0x8];
+ u8 sqn[0x18];
+ u8 reserved_at_60[0x20];
+};
+
+struct mlx5_ifc_modify_sq_out_bits {
+ u8 status[0x8];
+ u8 reserved_at_8[0x18];
+ u8 syndrome[0x20];
+ u8 reserved_at_40[0x40];
+};
+
+struct mlx5_ifc_modify_sq_in_bits {
+ u8 opcode[0x10];
+ u8 uid[0x10];
+ u8 reserved_at_20[0x10];
+ u8 op_mod[0x10];
+ u8 sq_state[0x4];
+ u8 reserved_at_44[0x4];
+ u8 sqn[0x18];
+ u8 reserved_at_60[0x20];
+ u8 modify_bitmask[0x40];
+ u8 reserved_at_c0[0x40];
+ struct mlx5_ifc_sqc_bits ctx;
+};
+
+struct mlx5_ifc_create_sq_out_bits {
+ u8 status[0x8];
+ u8 reserved_at_8[0x18];
+ u8 syndrome[0x20];
+ u8 reserved_at_40[0x8];
+ u8 sqn[0x18];
+ u8 reserved_at_60[0x20];
+};
+
+struct mlx5_ifc_create_sq_in_bits {
+ u8 opcode[0x10];
+ u8 uid[0x10];
+ u8 reserved_at_20[0x10];
+ u8 op_mod[0x10];
+ u8 reserved_at_40[0xc0];
+ struct mlx5_ifc_sqc_bits ctx;
+};
+
+enum {
+ MLX5_FLOW_METER_OBJ_MODIFY_FIELD_ACTIVE = (1ULL << 0),
+ MLX5_FLOW_METER_OBJ_MODIFY_FIELD_CBS = (1ULL << 1),
+ MLX5_FLOW_METER_OBJ_MODIFY_FIELD_CIR = (1ULL << 2),
+ MLX5_FLOW_METER_OBJ_MODIFY_FIELD_EBS = (1ULL << 3),
+ MLX5_FLOW_METER_OBJ_MODIFY_FIELD_EIR = (1ULL << 4),
+};
+
+struct mlx5_ifc_flow_meter_parameters_bits {
+ u8 valid[0x1];
+ u8 bucket_overflow[0x1];
+ u8 start_color[0x2];
+ u8 both_buckets_on_green[0x1];
+ u8 meter_mode[0x2];
+ u8 reserved_at_1[0x19];
+ u8 reserved_at_2[0x20];
+ u8 reserved_at_3[0x3];
+ u8 cbs_exponent[0x5];
+ u8 cbs_mantissa[0x8];
+ u8 reserved_at_4[0x3];
+ u8 cir_exponent[0x5];
+ u8 cir_mantissa[0x8];
+ u8 reserved_at_5[0x20];
+ u8 reserved_at_6[0x3];
+ u8 ebs_exponent[0x5];
+ u8 ebs_mantissa[0x8];
+ u8 reserved_at_7[0x3];
+ u8 eir_exponent[0x5];
+ u8 eir_mantissa[0x8];
+ u8 reserved_at_8[0x60];
+};
+#define MLX5_IFC_FLOW_METER_PARAM_MASK UINT64_C(0x80FFFFFF)
+#define MLX5_IFC_FLOW_METER_DISABLE_CBS_CIR_VAL 0x14BF00C8
+
+enum {
+ MLX5_METER_MODE_IP_LEN = 0x0,
+ MLX5_METER_MODE_L2_LEN = 0x1,
+ MLX5_METER_MODE_L2_IPG_LEN = 0x2,
+ MLX5_METER_MODE_PKT = 0x3,
+};
+
+enum {
+ MLX5_CQE_SIZE_64B = 0x0,
+ MLX5_CQE_SIZE_128B = 0x1,
+};
+
+struct mlx5_ifc_cqc_bits {
+ u8 status[0x4];
+ u8 as_notify[0x1];
+ u8 initiator_src_dct[0x1];
+ u8 dbr_umem_valid[0x1];
+ u8 reserved_at_7[0x1];
+ u8 cqe_sz[0x3];
+ u8 cc[0x1];
+ u8 reserved_at_c[0x1];
+ u8 scqe_break_moderation_en[0x1];
+ u8 oi[0x1];
+ u8 cq_period_mode[0x2];
+ u8 cqe_comp_en[0x1];
+ u8 mini_cqe_res_format[0x2];
+ u8 st[0x4];
+ u8 reserved_at_18[0x1];
+ u8 cqe_comp_layout[0x7];
+ u8 dbr_umem_id[0x20];
+ u8 reserved_at_40[0x14];
+ u8 page_offset[0x6];
+ u8 reserved_at_5a[0x2];
+ u8 mini_cqe_res_format_ext[0x2];
+ u8 cq_timestamp_format[0x2];
+ u8 reserved_at_60[0x3];
+ u8 log_cq_size[0x5];
+ u8 uar_page[0x18];
+ u8 reserved_at_80[0x4];
+ u8 cq_period[0xc];
+ u8 cq_max_count[0x10];
+ u8 reserved_at_a0[0x18];
+ u8 c_eqn[0x8];
+ u8 reserved_at_c0[0x3];
+ u8 log_page_size[0x5];
+ u8 reserved_at_c8[0x18];
+ u8 reserved_at_e0[0x20];
+ u8 reserved_at_100[0x8];
+ u8 last_notified_index[0x18];
+ u8 reserved_at_120[0x8];
+ u8 last_solicit_index[0x18];
+ u8 reserved_at_140[0x8];
+ u8 consumer_counter[0x18];
+ u8 reserved_at_160[0x8];
+ u8 producer_counter[0x18];
+ u8 local_partition_id[0xc];
+ u8 process_id[0x14];
+ u8 reserved_at_1A0[0x20];
+ u8 dbr_addr[0x40];
+};
+
+struct mlx5_ifc_health_buffer_bits {
+ u8 reserved_0[0x100];
+ u8 assert_existptr[0x20];
+ u8 assert_callra[0x20];
+ u8 reserved_1[0x40];
+ u8 fw_version[0x20];
+ u8 hw_id[0x20];
+ u8 reserved_2[0x20];
+ u8 irisc_index[0x8];
+ u8 synd[0x8];
+ u8 ext_synd[0x10];
+};
+
+struct mlx5_ifc_initial_seg_bits {
+ u8 fw_rev_minor[0x10];
+ u8 fw_rev_major[0x10];
+ u8 cmd_interface_rev[0x10];
+ u8 fw_rev_subminor[0x10];
+ u8 reserved_0[0x40];
+ u8 cmdq_phy_addr_63_32[0x20];
+ u8 cmdq_phy_addr_31_12[0x14];
+ u8 reserved_1[0x2];
+ u8 nic_interface[0x2];
+ u8 log_cmdq_size[0x4];
+ u8 log_cmdq_stride[0x4];
+ u8 command_doorbell_vector[0x20];
+ u8 reserved_2[0xf00];
+ u8 initializing[0x1];
+ u8 nic_interface_supported[0x7];
+ u8 reserved_4[0x18];
+ struct mlx5_ifc_health_buffer_bits health_buffer;
+ u8 no_dram_nic_offset[0x20];
+ u8 reserved_5[0x6de0];
+ u8 internal_timer_h[0x20];
+ u8 internal_timer_l[0x20];
+ u8 reserved_6[0x20];
+ u8 reserved_7[0x1f];
+ u8 clear_int[0x1];
+ u8 health_syndrome[0x8];
+ u8 health_counter[0x18];
+ u8 reserved_8[0x17fc0];
+};
+
+struct mlx5_ifc_create_cq_out_bits {
+ u8 status[0x8];
+ u8 reserved_at_8[0x18];
+ u8 syndrome[0x20];
+ u8 reserved_at_40[0x8];
+ u8 cqn[0x18];
+ u8 reserved_at_60[0x20];
+};
+
+struct mlx5_ifc_create_cq_in_bits {
+ u8 opcode[0x10];
+ u8 uid[0x10];
+ u8 reserved_at_20[0x10];
+ u8 op_mod[0x10];
+ u8 reserved_at_40[0x40];
+ struct mlx5_ifc_cqc_bits cq_context;
+ u8 cq_umem_offset[0x40];
+ u8 cq_umem_id[0x20];
+ u8 cq_umem_valid[0x1];
+ u8 reserved_at_2e1[0x1f];
+ u8 reserved_at_300[0x580];
+ u8 pas[];
+};
+
+enum {
+ MLX5_GENERAL_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b,
+ MLX5_GENERAL_OBJ_TYPE_DEK = 0x000c,
+ MLX5_GENERAL_OBJ_TYPE_VIRTQ = 0x000d,
+ MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c,
+ MLX5_GENERAL_OBJ_TYPE_IMPORT_KEK = 0x001d,
+ MLX5_GENERAL_OBJ_TYPE_CREDENTIAL = 0x001e,
+ MLX5_GENERAL_OBJ_TYPE_CRYPTO_LOGIN = 0x001f,
+ MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH = 0x0022,
+ MLX5_GENERAL_OBJ_TYPE_FLOW_METER_ASO = 0x0024,
+ MLX5_GENERAL_OBJ_TYPE_FLOW_HIT_ASO = 0x0025,
+ MLX5_GENERAL_OBJ_TYPE_CONN_TRACK_OFFLOAD = 0x0031,
+};
+
+struct mlx5_ifc_general_obj_in_cmd_hdr_bits {
+ u8 opcode[0x10];
+ u8 reserved_at_10[0x20];
+ u8 obj_type[0x10];
+ u8 obj_id[0x20];
+ u8 reserved_at_60[0x3];
+ u8 log_obj_range[0x5];
+ u8 reserved_at_58[0x18];
+};
+
+struct mlx5_ifc_general_obj_out_cmd_hdr_bits {
+ u8 status[0x8];
+ u8 reserved_at_8[0x18];
+ u8 syndrome[0x20];
+ u8 obj_id[0x20];
+ u8 reserved_at_60[0x20];
+};
+
+struct mlx5_ifc_virtio_q_counters_bits {
+ u8 modify_field_select[0x40];
+ u8 reserved_at_40[0x40];
+ u8 received_desc[0x40];
+ u8 completed_desc[0x40];
+ u8 error_cqes[0x20];
+ u8 bad_desc_errors[0x20];
+ u8 exceed_max_chain[0x20];
+ u8 invalid_buffer[0x20];
+ u8 reserved_at_180[0x50];
+};
+
+struct mlx5_ifc_geneve_tlv_option_bits {
+ u8 modify_field_select[0x40];
+ u8 reserved_at_40[0x18];
+ u8 geneve_option_fte_index[0x8];
+ u8 option_class[0x10];
+ u8 option_type[0x8];
+ u8 reserved_at_78[0x3];
+ u8 option_data_length[0x5];
+ u8 reserved_at_80[0x180];
+};
+
+struct mlx5_ifc_create_virtio_q_counters_in_bits {
+ struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
+ struct mlx5_ifc_virtio_q_counters_bits virtio_q_counters;
+};
+
+struct mlx5_ifc_query_virtio_q_counters_out_bits {
+ struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
+ struct mlx5_ifc_virtio_q_counters_bits virtio_q_counters;
+};
+
+struct mlx5_ifc_create_geneve_tlv_option_in_bits {
+ struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
+ struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt;
+};
+
+enum {
+ MLX5_CRYPTO_KEY_SIZE_128b = 0x0,
+ MLX5_CRYPTO_KEY_SIZE_256b = 0x1,
+};
+
+enum {
+ MLX5_CRYPTO_KEY_PURPOSE_TLS = 0x1,
+ MLX5_CRYPTO_KEY_PURPOSE_IPSEC = 0x2,
+ MLX5_CRYPTO_KEY_PURPOSE_AES_XTS = 0x3,
+ MLX5_CRYPTO_KEY_PURPOSE_MACSEC = 0x4,
+ MLX5_CRYPTO_KEY_PURPOSE_GCM = 0x5,
+ MLX5_CRYPTO_KEY_PURPOSE_PSP = 0x6,
+};
+
+struct mlx5_ifc_dek_bits {
+ u8 modify_field_select[0x40];
+ u8 state[0x8];
+ u8 reserved_at_48[0xc];
+ u8 key_size[0x4];
+ u8 has_keytag[0x1];
+ u8 reserved_at_59[0x3];
+ u8 key_purpose[0x4];
+ u8 reserved_at_60[0x8];
+ u8 pd[0x18];
+ u8 reserved_at_80[0x100];
+ u8 opaque[0x40];
+ u8 reserved_at_1c0[0x40];
+ u8 key[0x400];
+ u8 reserved_at_600[0x200];
+};
+
+struct mlx5_ifc_create_dek_in_bits {
+ struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
+ struct mlx5_ifc_dek_bits dek;
+};
+
+struct mlx5_ifc_import_kek_bits {
+ u8 modify_field_select[0x40];
+ u8 state[0x8];
+ u8 reserved_at_48[0xc];
+ u8 key_size[0x4];
+ u8 reserved_at_58[0x1a8];
+ u8 key[0x400];
+ u8 reserved_at_600[0x200];
+};
+
+struct mlx5_ifc_create_import_kek_in_bits {
+ struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
+ struct mlx5_ifc_import_kek_bits import_kek;
+};
+
+enum {
+ MLX5_CREDENTIAL_ROLE_OFFICER = 0x0,
+ MLX5_CREDENTIAL_ROLE_USER = 0x1,
+};
+
+struct mlx5_ifc_credential_bits {
+ u8 modify_field_select[0x40];
+ u8 state[0x8];
+ u8 reserved_at_48[0x10];
+ u8 credential_role[0x8];
+ u8 reserved_at_60[0x1a0];
+ u8 credential[0x180];
+ u8 reserved_at_380[0x480];
+};
+
+struct mlx5_ifc_create_credential_in_bits {
+ struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
+ struct mlx5_ifc_credential_bits credential;
+};
+
+struct mlx5_ifc_crypto_login_bits {
+ u8 modify_field_select[0x40];
+ u8 reserved_at_40[0x48];
+ u8 credential_pointer[0x18];
+ u8 reserved_at_a0[0x8];
+ u8 session_import_kek_ptr[0x18];
+ u8 reserved_at_c0[0x140];
+ u8 credential[0x180];
+ u8 reserved_at_380[0x480];
+};
+
+struct mlx5_ifc_create_crypto_login_in_bits {
+ struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
+ struct mlx5_ifc_crypto_login_bits crypto_login;
+};
+
+enum {
+ MLX5_VIRTQ_STATE_INIT = 0,
+ MLX5_VIRTQ_STATE_RDY = 1,
+ MLX5_VIRTQ_STATE_SUSPEND = 2,
+ MLX5_VIRTQ_STATE_ERROR = 3,
+};
+
+enum {
+ MLX5_VIRTQ_MODIFY_TYPE_STATE = (1UL << 0),
+ MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_PARAMS = (1UL << 3),
+ MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_DUMP_ENABLE = (1UL << 4),
+};
+
+struct mlx5_ifc_virtio_q_bits {
+ u8 virtio_q_type[0x8];
+ u8 reserved_at_8[0x5];
+ u8 event_mode[0x3];
+ u8 queue_index[0x10];
+ u8 full_emulation[0x1];
+ u8 virtio_version_1_0[0x1];
+ u8 reserved_at_22[0x2];
+ u8 offload_type[0x4];
+ u8 event_qpn_or_msix[0x18];
+ u8 doorbell_stride_idx[0x10];
+ u8 queue_size[0x10];
+ u8 device_emulation_id[0x20];
+ u8 desc_addr[0x40];
+ u8 used_addr[0x40];
+ u8 available_addr[0x40];
+ u8 virtio_q_mkey[0x20];
+ u8 reserved_at_160[0x18];
+ u8 error_type[0x8];
+ u8 umem_1_id[0x20];
+ u8 umem_1_size[0x20];
+ u8 umem_1_offset[0x40];
+ u8 umem_2_id[0x20];
+ u8 umem_2_size[0x20];
+ u8 umem_2_offset[0x40];
+ u8 umem_3_id[0x20];
+ u8 umem_3_size[0x20];
+ u8 umem_3_offset[0x40];
+ u8 counter_set_id[0x20];
+ u8 reserved_at_320[0x8];
+ u8 pd[0x18];
+ u8 reserved_at_340[0x2];
+ u8 queue_period_mode[0x2];
+ u8 queue_period_us[0xc];
+ u8 queue_max_count[0x10];
+ u8 reserved_at_360[0xa0];
+};
+
+struct mlx5_ifc_virtio_net_q_bits {
+ u8 modify_field_select[0x40];
+ u8 reserved_at_40[0x40];
+ u8 tso_ipv4[0x1];
+ u8 tso_ipv6[0x1];
+ u8 tx_csum[0x1];
+ u8 rx_csum[0x1];
+ u8 reserved_at_84[0x6];
+ u8 dirty_bitmap_dump_enable[0x1];
+ u8 vhost_log_page[0x5];
+ u8 reserved_at_90[0xc];
+ u8 state[0x4];
+ u8 reserved_at_a0[0x8];
+ u8 tisn_or_qpn[0x18];
+ u8 dirty_bitmap_mkey[0x20];
+ u8 dirty_bitmap_size[0x20];
+ u8 dirty_bitmap_addr[0x40];
+ u8 hw_available_index[0x10];
+ u8 hw_used_index[0x10];
+ u8 reserved_at_160[0xa0];
+ struct mlx5_ifc_virtio_q_bits virtio_q_context;
+};
+
+struct mlx5_ifc_create_virtq_in_bits {
+ struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
+ struct mlx5_ifc_virtio_net_q_bits virtq;
+};
+
+struct mlx5_ifc_query_virtq_out_bits {
+ struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
+ struct mlx5_ifc_virtio_net_q_bits virtq;
+};
+
+struct mlx5_ifc_flow_hit_aso_bits {
+ u8 modify_field_select[0x40];
+ u8 reserved_at_40[0x48];
+ u8 access_pd[0x18];
+ u8 reserved_at_a0[0x160];
+ u8 flag[0x200];
+};
+
+struct mlx5_ifc_create_flow_hit_aso_in_bits {
+ struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
+ struct mlx5_ifc_flow_hit_aso_bits flow_hit_aso;
+};
+
+struct mlx5_ifc_flow_meter_aso_bits {
+ u8 modify_field_select[0x40];
+ u8 reserved_at_40[0x48];
+ u8 access_pd[0x18];
+ u8 reserved_at_a0[0x160];
+ u8 parameters[0x200];
+};
+
+struct mlx5_ifc_create_flow_meter_aso_in_bits {
+ struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
+ struct mlx5_ifc_flow_meter_aso_bits flow_meter_aso;
+};
+
+struct mlx5_ifc_tcp_window_params_bits {
+ u8 max_ack[0x20];
+ u8 max_win[0x20];
+ u8 reply_end[0x20];
+ u8 sent_end[0x20];
+};
+
+struct mlx5_ifc_conn_track_aso_bits {
+ struct mlx5_ifc_tcp_window_params_bits reply_dir; /* End of DW3. */
+ struct mlx5_ifc_tcp_window_params_bits original_dir; /* End of DW7. */
+ u8 last_end[0x20]; /* End of DW8. */
+ u8 last_ack[0x20]; /* End of DW9. */
+ u8 last_seq[0x20]; /* End of DW10. */
+ u8 last_win[0x10];
+ u8 reserved_at_170[0xa];
+ u8 last_dir[0x1];
+ u8 last_index[0x5]; /* End of DW11. */
+ u8 reserved_at_180[0x40]; /* End of DW13. */
+ u8 reply_direction_tcp_scale[0x4];
+ u8 reply_direction_tcp_close_initiated[0x1];
+ u8 reply_direction_tcp_liberal_enabled[0x1];
+ u8 reply_direction_tcp_data_unacked[0x1];
+ u8 reply_direction_tcp_max_ack[0x1];
+ u8 reserved_at_1c8[0x8];
+ u8 original_direction_tcp_scale[0x4];
+ u8 original_direction_tcp_close_initiated[0x1];
+ u8 original_direction_tcp_liberal_enabled[0x1];
+ u8 original_direction_tcp_data_unacked[0x1];
+ u8 original_direction_tcp_max_ack[0x1];
+ u8 reserved_at_1d8[0x8]; /* End of DW14. */
+ u8 valid[0x1];
+ u8 state[0x3];
+ u8 freeze_track[0x1];
+ u8 reserved_at_1e5[0xb];
+ u8 reserved_at_1f0[0x1];
+ u8 connection_assured[0x1];
+ u8 sack_permitted[0x1];
+ u8 challenged_acked[0x1];
+ u8 heartbeat[0x1];
+ u8 max_ack_window[0x3];
+ u8 reserved_at_1f8[0x1];
+ u8 retransmission_counter[0x3];
+ u8 retranmission_limit_exceeded[0x1];
+ u8 retranmission_limit[0x3]; /* End of DW15. */
+};
+
+struct mlx5_ifc_conn_track_offload_bits {
+ u8 modify_field_select[0x40];
+ u8 reserved_at_40[0x40];
+ u8 reserved_at_80[0x8];
+ u8 conn_track_aso_access_pd[0x18];
+ u8 reserved_at_a0[0x160];
+ struct mlx5_ifc_conn_track_aso_bits conn_track_aso;
+};
+
+struct mlx5_ifc_create_conn_track_aso_in_bits {
+ struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
+ struct mlx5_ifc_conn_track_offload_bits conn_track_offload;
+};
+
+enum mlx5_access_aso_opc_mod {
+ ASO_OPC_MOD_IPSEC = 0x0,
+ ASO_OPC_MOD_CONNECTION_TRACKING = 0x1,
+ ASO_OPC_MOD_POLICER = 0x2,
+ ASO_OPC_MOD_RACE_AVOIDANCE = 0x3,
+ ASO_OPC_MOD_FLOW_HIT = 0x4,
+};
+
+#define ASO_CSEG_DATA_MASK_MODE_OFFSET 30
+
+enum mlx5_aso_data_mask_mode {
+ BITWISE_64BIT = 0x0,
+ BYTEWISE_64BYTE = 0x1,
+ CALCULATED_64BYTE = 0x2,
+};
+
+#define ASO_CSEG_COND_0_OPER_OFFSET 20
+#define ASO_CSEG_COND_1_OPER_OFFSET 16
+
+enum mlx5_aso_pre_cond_op {
+ ASO_OP_ALWAYS_FALSE = 0x0,
+ ASO_OP_ALWAYS_TRUE = 0x1,
+ ASO_OP_EQUAL = 0x2,
+ ASO_OP_NOT_EQUAL = 0x3,
+ ASO_OP_GREATER_OR_EQUAL = 0x4,
+ ASO_OP_LESSER_OR_EQUAL = 0x5,
+ ASO_OP_LESSER = 0x6,
+ ASO_OP_GREATER = 0x7,
+ ASO_OP_CYCLIC_GREATER = 0x8,
+ ASO_OP_CYCLIC_LESSER = 0x9,
+};
+
+#define ASO_CSEG_COND_OPER_OFFSET 6
+
+enum mlx5_aso_op {
+ ASO_OPER_LOGICAL_AND = 0x0,
+ ASO_OPER_LOGICAL_OR = 0x1,
+};
+
+/* ASO WQE CTRL segment. */
+struct mlx5_aso_cseg {
+ uint32_t va_h;
+ uint32_t va_l_r;
+ uint32_t lkey;
+ uint32_t operand_masks;
+ uint32_t condition_0_data;
+ uint32_t condition_0_mask;
+ uint32_t condition_1_data;
+ uint32_t condition_1_mask;
+ uint64_t bitwise_data;
+ uint64_t data_mask;
+} __rte_packed;
+
+/* A meter data segment - 2 per ASO WQE. */
+struct mlx5_aso_mtr_dseg {
+ uint32_t v_bo_sc_bbog_mm;
+ /*
+ * bit 31: valid, 30: bucket overflow, 28-29: start color,
+ * 27: both buckets on green, 24-25: meter mode.
+ */
+ uint32_t reserved;
+ uint32_t cbs_cir;
+ /*
+ * bit 24-28: cbs_exponent, bit 16-23 cbs_mantissa,
+ * bit 8-12: cir_exponent, bit 0-7 cir_mantissa.
+ */
+ uint32_t c_tokens;
+ uint32_t ebs_eir;
+ /*
+ * bit 24-28: ebs_exponent, bit 16-23 ebs_mantissa,
+ * bit 8-12: eir_exponent, bit 0-7 eir_mantissa.
+ */
+ uint32_t e_tokens;
+ uint64_t timestamp;
+} __rte_packed;
+
+#define ASO_DSEG_VALID_OFFSET 31
+#define ASO_DSEG_BO_OFFSET 30
+#define ASO_DSEG_SC_OFFSET 28
+#define ASO_DSEG_BBOG_OFFSET 27
+#define ASO_DSEG_MTR_MODE 24
+#define ASO_DSEG_CBS_EXP_OFFSET 24
+#define ASO_DSEG_CBS_MAN_OFFSET 16
+#define ASO_DSEG_XIR_EXP_MASK 0x1F
+#define ASO_DSEG_XIR_EXP_OFFSET 8
+#define ASO_DSEG_EBS_EXP_OFFSET 24
+#define ASO_DSEG_EBS_MAN_OFFSET 16
+#define ASO_DSEG_EXP_MASK 0x1F
+#define ASO_DSEG_MAN_MASK 0xFF
+
+#define MLX5_ASO_WQE_DSEG_SIZE 0x40
+#define MLX5_ASO_METERS_PER_WQE 2
+#define MLX5_ASO_MTRS_PER_POOL 128
+
+/* ASO WQE data segment. */
+struct mlx5_aso_dseg {
+ union {
+ uint8_t data[MLX5_ASO_WQE_DSEG_SIZE];
+ struct mlx5_aso_mtr_dseg mtrs[MLX5_ASO_METERS_PER_WQE];
+ };
+} __rte_packed;
+
+/* ASO WQE. */
+struct mlx5_aso_wqe {
+ struct mlx5_wqe_cseg general_cseg;
+ struct mlx5_aso_cseg aso_cseg;
+ struct mlx5_aso_dseg aso_dseg;
+} __rte_packed;
+
+enum {
+ MLX5_EVENT_TYPE_OBJECT_CHANGE = 0x27,
+};
+
+enum {
+ MLX5_QP_ST_RC = 0x0,
+};
+
+enum {
+ MLX5_QP_PM_MIGRATED = 0x3,
+};
+
+enum {
+ MLX5_NON_ZERO_RQ = 0x0,
+ MLX5_SRQ_RQ = 0x1,
+ MLX5_CRQ_RQ = 0x2,
+ MLX5_ZERO_LEN_RQ = 0x3,
+};
+
+struct mlx5_ifc_ads_bits {
+ u8 fl[0x1];
+ u8 free_ar[0x1];
+ u8 reserved_at_2[0xe];
+ u8 pkey_index[0x10];
+ u8 reserved_at_20[0x8];
+ u8 grh[0x1];
+ u8 mlid[0x7];
+ u8 rlid[0x10];
+ u8 ack_timeout[0x5];
+ u8 reserved_at_45[0x3];
+ u8 src_addr_index[0x8];
+ u8 reserved_at_50[0x4];
+ u8 stat_rate[0x4];
+ u8 hop_limit[0x8];
+ u8 reserved_at_60[0x4];
+ u8 tclass[0x8];
+ u8 flow_label[0x14];
+ u8 rgid_rip[16][0x8];
+ u8 reserved_at_100[0x4];
+ u8 f_dscp[0x1];
+ u8 f_ecn[0x1];
+ u8 reserved_at_106[0x1];
+ u8 f_eth_prio[0x1];
+ u8 ecn[0x2];
+ u8 dscp[0x6];
+ u8 udp_sport[0x10];
+ u8 dei_cfi[0x1];
+ u8 eth_prio[0x3];
+ u8 sl[0x4];
+ u8 vhca_port_num[0x8];
+ u8 rmac_47_32[0x10];
+ u8 rmac_31_0[0x20];
+};
+
+struct mlx5_ifc_qpc_bits {
+ u8 state[0x4];
+ u8 lag_tx_port_affinity[0x4];
+ u8 st[0x8];
+ u8 reserved_at_10[0x3];
+ u8 pm_state[0x2];
+ u8 reserved_at_15[0x1];
+ u8 req_e2e_credit_mode[0x2];
+ u8 offload_type[0x4];
+ u8 end_padding_mode[0x2];
+ u8 reserved_at_1e[0x2];
+ u8 wq_signature[0x1];
+ u8 block_lb_mc[0x1];
+ u8 atomic_like_write_en[0x1];
+ u8 latency_sensitive[0x1];
+ u8 reserved_at_24[0x1];
+ u8 drain_sigerr[0x1];
+ u8 reserved_at_26[0x2];
+ u8 pd[0x18];
+ u8 mtu[0x3];
+ u8 log_msg_max[0x5];
+ u8 reserved_at_48[0x1];
+ u8 log_rq_size[0x4];
+ u8 log_rq_stride[0x3];
+ u8 no_sq[0x1];
+ u8 log_sq_size[0x4];
+ u8 reserved_at_55[0x3];
+ u8 ts_format[0x2];
+ u8 reserved_at_5a[0x1];
+ u8 rlky[0x1];
+ u8 ulp_stateless_offload_mode[0x4];
+ u8 counter_set_id[0x8];
+ u8 uar_page[0x18];
+ u8 reserved_at_80[0x8];
+ u8 user_index[0x18];
+ u8 reserved_at_a0[0x3];
+ u8 log_page_size[0x5];
+ u8 remote_qpn[0x18];
+ struct mlx5_ifc_ads_bits primary_address_path;
+ struct mlx5_ifc_ads_bits secondary_address_path;
+ u8 log_ack_req_freq[0x4];
+ u8 reserved_at_384[0x4];
+ u8 log_sra_max[0x3];
+ u8 reserved_at_38b[0x2];
+ u8 retry_count[0x3];
+ u8 rnr_retry[0x3];
+ u8 reserved_at_393[0x1];
+ u8 fre[0x1];
+ u8 cur_rnr_retry[0x3];
+ u8 cur_retry_count[0x3];
+ u8 reserved_at_39b[0x5];
+ u8 reserved_at_3a0[0x20];
+ u8 reserved_at_3c0[0x8];
+ u8 next_send_psn[0x18];
+ u8 reserved_at_3e0[0x8];
+ u8 cqn_snd[0x18];
+ u8 reserved_at_400[0x8];
+ u8 deth_sqpn[0x18];
+ u8 reserved_at_420[0x20];
+ u8 reserved_at_440[0x8];
+ u8 last_acked_psn[0x18];
+ u8 reserved_at_460[0x8];
+ u8 ssn[0x18];
+ u8 reserved_at_480[0x8];
+ u8 log_rra_max[0x3];
+ u8 reserved_at_48b[0x1];
+ u8 atomic_mode[0x4];
+ u8 rre[0x1];
+ u8 rwe[0x1];
+ u8 rae[0x1];
+ u8 reserved_at_493[0x1];
+ u8 page_offset[0x6];
+ u8 reserved_at_49a[0x3];
+ u8 cd_slave_receive[0x1];
+ u8 cd_slave_send[0x1];
+ u8 cd_master[0x1];
+ u8 reserved_at_4a0[0x3];
+ u8 min_rnr_nak[0x5];
+ u8 next_rcv_psn[0x18];
+ u8 reserved_at_4c0[0x8];
+ u8 xrcd[0x18];
+ u8 reserved_at_4e0[0x8];
+ u8 cqn_rcv[0x18];
+ u8 dbr_addr[0x40];
+ u8 q_key[0x20];
+ u8 reserved_at_560[0x5];
+ u8 rq_type[0x3];
+ u8 srqn_rmpn_xrqn[0x18];
+ u8 reserved_at_580[0x8];
+ u8 rmsn[0x18];
+ u8 hw_sq_wqebb_counter[0x10];
+ u8 sw_sq_wqebb_counter[0x10];
+ u8 hw_rq_counter[0x20];
+ u8 sw_rq_counter[0x20];
+ u8 reserved_at_600[0x20];
+ u8 reserved_at_620[0xf];
+ u8 cgs[0x1];
+ u8 cs_req[0x8];
+ u8 cs_res[0x8];
+ u8 dc_access_key[0x40];
+ u8 reserved_at_680[0x3];
+ u8 dbr_umem_valid[0x1];
+ u8 reserved_at_684[0x9c];
+ u8 dbr_umem_id[0x20];
+};
+
+struct mlx5_ifc_create_qp_out_bits {
+ u8 status[0x8];
+ u8 reserved_at_8[0x18];
+ u8 syndrome[0x20];
+ u8 reserved_at_40[0x8];
+ u8 qpn[0x18];
+ u8 reserved_at_60[0x20];
+};
+
+struct mlx5_ifc_qpc_extension_bits {
+ u8 reserved_at_0[0x2];
+ u8 mmo[0x1];
+ u8 reserved_at_3[0x5fd];
+};
+
+#ifdef PEDANTIC
+#pragma GCC diagnostic ignored "-Wpedantic"
+#endif
+struct mlx5_ifc_qpc_pas_list_bits {
+ u8 pas[0][0x40];
+};
+
+#ifdef PEDANTIC
+#pragma GCC diagnostic ignored "-Wpedantic"
+#endif
+struct mlx5_ifc_qpc_extension_and_pas_list_bits {
+ struct mlx5_ifc_qpc_extension_bits qpc_data_extension;
+ u8 pas[0][0x40];
+};
+
+
+#ifdef PEDANTIC
+#pragma GCC diagnostic ignored "-Wpedantic"
+#endif
+struct mlx5_ifc_create_qp_in_bits {
+ u8 opcode[0x10];
+ u8 uid[0x10];
+ u8 reserved_at_20[0x10];
+ u8 op_mod[0x10];
+ u8 qpc_ext[0x1];
+ u8 reserved_at_41[0x3f];
+ u8 opt_param_mask[0x20];
+ u8 reserved_at_a0[0x20];
+ struct mlx5_ifc_qpc_bits qpc;
+ u8 wq_umem_offset[0x40];
+ u8 wq_umem_id[0x20];
+ u8 wq_umem_valid[0x1];
+ u8 reserved_at_861[0x1f];
+ union {
+ struct mlx5_ifc_qpc_pas_list_bits qpc_pas_list;
+ struct mlx5_ifc_qpc_extension_and_pas_list_bits
+ qpc_extension_and_pas_list;
+ };
+};
+#ifdef PEDANTIC
+#pragma GCC diagnostic error "-Wpedantic"
+#endif
+
+struct mlx5_ifc_sqerr2rts_qp_out_bits {
+ u8 status[0x8];
+ u8 reserved_at_8[0x18];
+ u8 syndrome[0x20];
+ u8 reserved_at_40[0x40];
+};
+
+struct mlx5_ifc_sqerr2rts_qp_in_bits {
+ u8 opcode[0x10];
+ u8 uid[0x10];
+ u8 reserved_at_20[0x10];
+ u8 op_mod[0x10];
+ u8 reserved_at_40[0x8];
+ u8 qpn[0x18];
+ u8 reserved_at_60[0x20];
+ u8 opt_param_mask[0x20];
+ u8 reserved_at_a0[0x20];
+ struct mlx5_ifc_qpc_bits qpc;
+ u8 reserved_at_800[0x80];
+};
+
+struct mlx5_ifc_sqd2rts_qp_out_bits {
+ u8 status[0x8];
+ u8 reserved_at_8[0x18];
+ u8 syndrome[0x20];
+ u8 reserved_at_40[0x40];
+};
+
+struct mlx5_ifc_sqd2rts_qp_in_bits {
+ u8 opcode[0x10];
+ u8 uid[0x10];
+ u8 reserved_at_20[0x10];
+ u8 op_mod[0x10];
+ u8 reserved_at_40[0x8];
+ u8 qpn[0x18];
+ u8 reserved_at_60[0x20];
+ u8 opt_param_mask[0x20];
+ u8 reserved_at_a0[0x20];
+ struct mlx5_ifc_qpc_bits qpc;
+ u8 reserved_at_800[0x80];
+};
+
+struct mlx5_ifc_rts2rts_qp_out_bits {
+ u8 status[0x8];
+ u8 reserved_at_8[0x18];
+ u8 syndrome[0x20];
+ u8 reserved_at_40[0x40];
+};
+
+struct mlx5_ifc_rts2rts_qp_in_bits {
+ u8 opcode[0x10];
+ u8 uid[0x10];
+ u8 reserved_at_20[0x10];
+ u8 op_mod[0x10];
+ u8 reserved_at_40[0x8];
+ u8 qpn[0x18];
+ u8 reserved_at_60[0x20];
+ u8 opt_param_mask[0x20];
+ u8 reserved_at_a0[0x20];
+ struct mlx5_ifc_qpc_bits qpc;
+ u8 reserved_at_800[0x80];
+};
+
+struct mlx5_ifc_rtr2rts_qp_out_bits {
+ u8 status[0x8];
+ u8 reserved_at_8[0x18];
+ u8 syndrome[0x20];
+ u8 reserved_at_40[0x40];
+};
+
+struct mlx5_ifc_rtr2rts_qp_in_bits {
+ u8 opcode[0x10];
+ u8 uid[0x10];
+ u8 reserved_at_20[0x10];
+ u8 op_mod[0x10];