+#define SYM_ENQ_THRESHOLD_NAME "qat_sym_enq_threshold"
+#define ASYM_ENQ_THRESHOLD_NAME "qat_asym_enq_threshold"
+#define COMP_ENQ_THRESHOLD_NAME "qat_comp_enq_threshold"
+#define MAX_QP_THRESHOLD_SIZE 32
+
+/**
+ * Function prototypes for GENx specific device operations.
+ **/
+typedef int (*qat_dev_reset_ring_pairs_t)
+ (struct qat_pci_device *);
+typedef const struct rte_mem_resource* (*qat_dev_get_transport_bar_t)
+ (struct rte_pci_device *);
+typedef int (*qat_dev_get_misc_bar_t)
+ (struct rte_mem_resource **, struct rte_pci_device *);
+typedef int (*qat_dev_read_config_t)
+ (struct qat_pci_device *);
+typedef int (*qat_dev_get_extra_size_t)(void);
+
+struct qat_dev_hw_spec_funcs {
+ qat_dev_reset_ring_pairs_t qat_dev_reset_ring_pairs;
+ qat_dev_get_transport_bar_t qat_dev_get_transport_bar;
+ qat_dev_get_misc_bar_t qat_dev_get_misc_bar;
+ qat_dev_read_config_t qat_dev_read_config;
+ qat_dev_get_extra_size_t qat_dev_get_extra_size;
+};
+
+extern struct qat_dev_hw_spec_funcs *qat_dev_hw_spec[];
+
+struct qat_dev_cmd_param {
+ const char *name;
+ uint16_t val;
+};
+
+struct qat_device_info {
+ const struct rte_memzone *mz;
+ /**< mz to store the qat_pci_device so it can be
+ * shared across processes
+ */
+ struct rte_pci_device *pci_dev;
+ struct rte_device sym_rte_dev;
+ /**< This represents the crypto sym subset of this pci device.
+ * Register with this rather than with the one in
+ * pci_dev so that its driver can have a crypto-specific name
+ */
+
+ struct rte_device asym_rte_dev;
+ /**< This represents the crypto asym subset of this pci device.
+ * Register with this rather than with the one in
+ * pci_dev so that its driver can have a crypto-specific name
+ */
+
+ struct rte_device comp_rte_dev;
+ /**< This represents the compression subset of this pci device.
+ * Register with this rather than with the one in
+ * pci_dev so that its driver can have a compression-specific name
+ */
+};
+
+extern struct qat_device_info qat_pci_devs[];
+
+struct qat_cryptodev_private;
+struct qat_comp_dev_private;
+