+ uint8_t nb_queues;
+ /**< Number of crypto queues attached */
+ uint16_t lf_msixoff[OTX2_CPT_MAX_LFS];
+ /**< MSI-X offsets */
+ uint8_t lf_blkaddr[OTX2_CPT_MAX_LFS];
+ /**< CPT0/1 BLKADDR of LFs */
+ uint8_t cpt_revision;
+ /**< CPT revision */
+ uint8_t err_intr_registered:1;
+ /**< Are error interrupts registered? */
+ union cpt_eng_caps hw_caps[CPT_MAX_ENG_TYPES];
+ /**< CPT device capabilities */
+};
+
+struct cpt_meta_info {
+ uint64_t deq_op_info[5];
+ uint64_t comp_code_sz;
+ union cpt_res_s cpt_res __rte_aligned(16);
+ struct cpt_request_info cpt_req;