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net/mlx5: add new memory region support
[dpdk.git]
/
drivers
/
crypto
/
qat
/
qat_crypto.c
diff --git
a/drivers/crypto/qat/qat_crypto.c
b/drivers/crypto/qat/qat_crypto.c
index
61760b6
..
d9ce2a1
100644
(file)
--- a/
drivers/crypto/qat/qat_crypto.c
+++ b/
drivers/crypto/qat/qat_crypto.c
@@
-1,5
+1,5
@@
/* SPDX-License-Identifier: BSD-3-Clause
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2015-201
7
Intel Corporation
+ * Copyright(c) 2015-201
8
Intel Corporation
*/
#include <stdio.h>
*/
#include <stdio.h>
@@
-1010,10
+1010,10
@@
void rxq_free_desc(struct qat_qp *qp, struct qat_queue *q)
void *cur_desc = (uint8_t *)q->base_addr + old_head;
if (new_head < old_head) {
void *cur_desc = (uint8_t *)q->base_addr + old_head;
if (new_head < old_head) {
- memset(cur_desc, ADF_RING_EMPTY_SIG, max_head - old_head);
- memset(q->base_addr, ADF_RING_EMPTY_SIG, new_head);
+ memset(cur_desc, ADF_RING_EMPTY_SIG
_BYTE
, max_head - old_head);
+ memset(q->base_addr, ADF_RING_EMPTY_SIG
_BYTE
, new_head);
} else {
} else {
- memset(cur_desc, ADF_RING_EMPTY_SIG, new_head - old_head);
+ memset(cur_desc, ADF_RING_EMPTY_SIG
_BYTE
, new_head - old_head);
}
q->nb_processed_responses = 0;
q->csr_head = new_head;
}
q->nb_processed_responses = 0;
q->csr_head = new_head;
@@
-1342,7
+1342,9
@@
qat_write_hw_desc_entry(struct rte_crypto_op *op, uint8_t *out_msg,
}
min_ofs = auth_ofs;
}
min_ofs = auth_ofs;
- auth_param->auth_res_addr = op->sym->auth.digest.phys_addr;
+ if (likely(ctx->qat_hash_alg != ICP_QAT_HW_AUTH_ALGO_NULL))
+ auth_param->auth_res_addr =
+ op->sym->auth.digest.phys_addr;
}
}