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net/mlx5: fix setting of Rx hash fields
[dpdk.git]
/
drivers
/
event
/
octeontx2
/
otx2_evdev.h
diff --git
a/drivers/event/octeontx2/otx2_evdev.h
b/drivers/event/octeontx2/otx2_evdev.h
index
9c9718f
..
ef523dc
100644
(file)
--- a/
drivers/event/octeontx2/otx2_evdev.h
+++ b/
drivers/event/octeontx2/otx2_evdev.h
@@
-14,8
+14,9
@@
#include "otx2_dev.h"
#include "otx2_ethdev.h"
#include "otx2_mempool.h"
#include "otx2_dev.h"
#include "otx2_ethdev.h"
#include "otx2_mempool.h"
+#include "otx2_tim_evdev.h"
-#define EVENTDEV_NAME_OCTEONTX2_PMD
otx2_eventdev
+#define EVENTDEV_NAME_OCTEONTX2_PMD
event_octeontx2
#define sso_func_trace otx2_sso_dbg
#define sso_func_trace otx2_sso_dbg
@@
-25,6
+26,7
@@
#define OTX2_SSO_SQB_LIMIT (0x180)
#define OTX2_SSO_XAQ_SLACK (8)
#define OTX2_SSO_XAQ_CACHE_CNT (0x7)
#define OTX2_SSO_SQB_LIMIT (0x180)
#define OTX2_SSO_XAQ_SLACK (8)
#define OTX2_SSO_XAQ_CACHE_CNT (0x7)
+#define OTX2_SSO_WQE_SG_PTR (9)
/* SSO LF register offsets (BAR2) */
#define SSO_LF_GGRP_OP_ADD_WORK0 (0x0ull)
/* SSO LF register offsets (BAR2) */
#define SSO_LF_GGRP_OP_ADD_WORK0 (0x0ull)
@@
-136,9
+138,12
@@
struct otx2_sso_evdev {
struct rte_mempool *xaq_pool;
uint64_t rx_offloads;
uint64_t tx_offloads;
struct rte_mempool *xaq_pool;
uint64_t rx_offloads;
uint64_t tx_offloads;
+ uint64_t adptr_xae_cnt;
uint16_t rx_adptr_pool_cnt;
uint16_t rx_adptr_pool_cnt;
- uint32_t adptr_xae_cnt;
uint64_t *rx_adptr_pools;
uint64_t *rx_adptr_pools;
+ uint16_t tim_adptr_ring_cnt;
+ uint16_t *timer_adptr_rings;
+ uint64_t *timer_adptr_sz;
/* Dev args */
uint8_t dual_ws;
uint8_t selftest;
/* Dev args */
uint8_t dual_ws;
uint8_t selftest;
@@
-222,10
+227,14
@@
otx2_wqe_to_mbuf(uint64_t get_work1, const uint64_t mbuf, uint8_t port_id,
const void * const lookup_mem)
{
struct nix_wqe_hdr_s *wqe = (struct nix_wqe_hdr_s *)get_work1;
const void * const lookup_mem)
{
struct nix_wqe_hdr_s *wqe = (struct nix_wqe_hdr_s *)get_work1;
+ uint64_t val = mbuf_init.value | (uint64_t)port_id << 48;
+
+ if (flags & NIX_RX_OFFLOAD_TSTAMP_F)
+ val |= NIX_TIMESYNC_RX_OFFSET;
otx2_nix_cqe_to_mbuf((struct nix_cqe_hdr_s *)wqe, tag,
(struct rte_mbuf *)mbuf, lookup_mem,
otx2_nix_cqe_to_mbuf((struct nix_cqe_hdr_s *)wqe, tag,
(struct rte_mbuf *)mbuf, lookup_mem,
-
mbuf_init.value | (uint64_t)port_id << 48
, flags);
+
val
, flags);
}
}
@@
-326,7
+335,7
@@
uint16_t otx2_ssogws_dual_deq_seg_timeout_burst_ ##name(void *port, \
SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
#undef R
SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
#undef R
-#define T(name, f
4, f3, f2, f1, f0, sz, flags)
\
+#define T(name, f
5, f4, f3, f2, f1, f0, sz, flags)
\
uint16_t otx2_ssogws_tx_adptr_enq_ ## name(void *port, struct rte_event ev[],\
uint16_t nb_events); \
uint16_t otx2_ssogws_tx_adptr_enq_seg_ ## name(void *port, \
uint16_t otx2_ssogws_tx_adptr_enq_ ## name(void *port, struct rte_event ev[],\
uint16_t nb_events); \
uint16_t otx2_ssogws_tx_adptr_enq_seg_ ## name(void *port, \