+static inline int
+tim_get_msix_offsets(void)
+{
+ struct otx2_tim_evdev *dev = tim_priv_get();
+ struct otx2_mbox *mbox = dev->mbox;
+ struct msix_offset_rsp *msix_rsp;
+ int i, rc;
+
+ /* Get TIM MSIX vector offsets */
+ otx2_mbox_alloc_msg_msix_offset(mbox);
+ rc = otx2_mbox_process_msg(mbox, (void *)&msix_rsp);
+
+ for (i = 0; i < dev->nb_rings; i++)
+ dev->tim_msixoff[i] = msix_rsp->timlf_msixoff[i];
+
+ return rc;
+}
+
+static void
+tim_set_fp_ops(struct otx2_tim_ring *tim_ring)
+{
+ uint8_t prod_flag = !tim_ring->prod_type_sp;
+
+ /* [MOD/AND] [DFB/FB] [SP][MP]*/
+ const rte_event_timer_arm_burst_t arm_burst[2][2][2][2] = {
+#define FP(_name, _f4, _f3, _f2, _f1, flags) \
+ [_f4][_f3][_f2][_f1] = otx2_tim_arm_burst_ ## _name,
+TIM_ARM_FASTPATH_MODES
+#undef FP
+ };
+
+ const rte_event_timer_arm_tmo_tick_burst_t arm_tmo_burst[2][2][2] = {
+#define FP(_name, _f3, _f2, _f1, flags) \
+ [_f3][_f2][_f1] = otx2_tim_arm_tmo_tick_burst_ ## _name,
+TIM_ARM_TMO_FASTPATH_MODES
+#undef FP
+ };
+
+ otx2_tim_ops.arm_burst =
+ arm_burst[tim_ring->enable_stats][tim_ring->optimized]
+ [tim_ring->ena_dfb][prod_flag];
+ otx2_tim_ops.arm_tmo_tick_burst =
+ arm_tmo_burst[tim_ring->enable_stats][tim_ring->optimized]
+ [tim_ring->ena_dfb];
+ otx2_tim_ops.cancel_burst = otx2_tim_timer_cancel_burst;
+}
+
+static void
+otx2_tim_ring_info_get(const struct rte_event_timer_adapter *adptr,
+ struct rte_event_timer_adapter_info *adptr_info)
+{
+ struct otx2_tim_ring *tim_ring = adptr->data->adapter_priv;
+
+ adptr_info->max_tmo_ns = tim_ring->max_tout;
+ adptr_info->min_resolution_ns = tim_ring->tck_nsec;
+ rte_memcpy(&adptr_info->conf, &adptr->data->conf,
+ sizeof(struct rte_event_timer_adapter_conf));
+}
+
+static void
+tim_optimze_bkt_param(struct otx2_tim_ring *tim_ring)
+{
+ uint64_t tck_nsec;
+ uint32_t hbkts;
+ uint32_t lbkts;
+
+ hbkts = rte_align32pow2(tim_ring->nb_bkts);
+ tck_nsec = RTE_ALIGN_MUL_CEIL(tim_ring->max_tout / (hbkts - 1), 10);
+
+ if ((tck_nsec < TICK2NSEC(OTX2_TIM_MIN_TMO_TKS,
+ tim_ring->tenns_clk_freq) ||
+ hbkts > OTX2_TIM_MAX_BUCKETS))
+ hbkts = 0;
+
+ lbkts = rte_align32prevpow2(tim_ring->nb_bkts);
+ tck_nsec = RTE_ALIGN_MUL_CEIL((tim_ring->max_tout / (lbkts - 1)), 10);
+
+ if ((tck_nsec < TICK2NSEC(OTX2_TIM_MIN_TMO_TKS,
+ tim_ring->tenns_clk_freq) ||
+ lbkts > OTX2_TIM_MAX_BUCKETS))
+ lbkts = 0;
+
+ if (!hbkts && !lbkts)
+ return;
+
+ if (!hbkts) {
+ tim_ring->nb_bkts = lbkts;
+ goto end;
+ } else if (!lbkts) {
+ tim_ring->nb_bkts = hbkts;
+ goto end;
+ }
+
+ tim_ring->nb_bkts = (hbkts - tim_ring->nb_bkts) <
+ (tim_ring->nb_bkts - lbkts) ? hbkts : lbkts;
+end:
+ tim_ring->optimized = true;
+ tim_ring->tck_nsec = RTE_ALIGN_MUL_CEIL((tim_ring->max_tout /
+ (tim_ring->nb_bkts - 1)), 10);
+ otx2_tim_dbg("Optimized configured values");
+ otx2_tim_dbg("Nb_bkts : %" PRIu32 "", tim_ring->nb_bkts);
+ otx2_tim_dbg("Tck_nsec : %" PRIu64 "", tim_ring->tck_nsec);
+}
+